leo/linreceiver-vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

decoder

Browse Source
This commit is contained in:
leo 2023-09-25 17:34:48 +02:00
parent 8d7b623e09
commit ecd3c51465
Signed by: leo
GPG Key ID: 0DD993BFB2B307DB
1 changed files with 13 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
ReceptionTrame_lib/receptionTrame_op.vhd
View File

@ -40,6 +40,8 @@ END receptionTrame_op;
ARCHITECTURE arch OF receptionTrame_op IS ARCHITECTURE arch OF receptionTrame_op IS
SIGNAL LinSynchro_int : std_logic; SIGNAL LinSynchro_int : std_logic;
SIGNAL octetRecu_int : std_logic_vector(7 downto 0);
SIGNAL nbDataField_INIT : integer;
COMPONENT D_FF COMPONENT D_FF
PORT( PORT(
@ -65,6 +67,7 @@ END COMPONENT;
BEGIN BEGIN
LinSynchro <= LinSynchro_int; LinSynchro <= LinSynchro_int;
octetRecu <= octetRecu_int;
-- Lin sync D-FF, with asynchronous reset -- Lin sync D-FF, with asynchronous reset
Lin_in_sync : D_FF Lin_in_sync : D_FF
@ -85,7 +88,16 @@ Lin_para : shift_register
H_EN => octetRecu_EN, H_EN => octetRecu_EN,
nRst => nCLR, nRst => nCLR,
D => LinSynchro_int, D => LinSynchro_int,
Q => octetRecu Q => octetRecu_int
); );
-- Decoder
WITH octetRecu_int(5 downto 4) SELECT
nbDataField_INIT <=
1 when "00",
1 when "01",
3 when "10",
7 when "11",
0 when others;
END ARCHITECTURE arch; END ARCHITECTURE arch;