decoder

ReceptionTrame_lib/receptionTrame_op.vhd

@@ -40,6 +40,8 @@ END receptionTrame_op;
 
 ARCHITECTURE arch OF receptionTrame_op IS
 SIGNAL LinSynchro_int : std_logic;
+SIGNAL octetRecu_int : std_logic_vector(7 downto 0);
+SIGNAL nbDataField_INIT : integer;
 
 COMPONENT D_FF
   PORT(
@@ -65,6 +67,7 @@ END COMPONENT;
 BEGIN
 
 LinSynchro <= LinSynchro_int;
+octetRecu <= octetRecu_int;
 
 -- Lin sync D-FF, with asynchronous reset
 Lin_in_sync : D_FF
@@ -85,7 +88,16 @@ Lin_para : shift_register
     H_EN => octetRecu_EN,
     nRst => nCLR,
     D => LinSynchro_int,
-    Q => octetRecu
+    Q => octetRecu_int
   );
 
+-- Decoder
+WITH octetRecu_int(5 downto 4) SELECT
+  nbDataField_INIT <= 
+    1 when "00",
+    1 when "01",
+    3 when "10",
+    7 when "11",
+    0 when others;
+
 END ARCHITECTURE arch;