linreceiver-vhdl/internalstate_struct.vhd

-- VHDL Entity RecepteurLIN_lib.InternalState.interface
--
-- Created:
--          by - e208835u.UNKNOWN (irb013-09)
--          at - 12:48:12 17/10/2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY InternalState IS
   PORT( 
      Errors_SET          : IN     std_logic_vector (3 DOWNTO 1);
      EtatLu_RST          : IN     std_logic;
      H                   : IN     std_logic;
      MessageReceived_SET : IN     std_logic;
      NbByteDec           : IN     std_logic;
      NbByteInc           : IN     std_logic;
      NbRecByte_RST       : IN     std_logic;
      nCLR                : IN     std_logic;
      EtatLu              : OUT    std_logic_vector (7 DOWNTO 0)
   );

-- Declarations

END InternalState ;

--
-- VHDL Architecture RecepteurLIN_lib.InternalState.struct
--
-- Created:
--          by - e208835u.UNKNOWN (irb013-09)
--          at - 12:48:12 17/10/2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ARCHITECTURE struct OF InternalState IS

   -- Architecture declarations

   -- Internal signal declarations
   SIGNAL dout  : std_logic_vector(3 DOWNTO 0);
   SIGNAL dout1 : std_logic;
   SIGNAL dout2 : std_logic;


   -- ModuleWare signal declarations(v1.12) for instance 'U_1' of 'cntr'
   SIGNAL mw_U_1n_cnt : std_logic_vector(3 DOWNTO 0);
   SIGNAL mw_U_1c_cnt : std_logic_vector(3 DOWNTO 0);

   -- ModuleWare signal declarations(v1.12) for instance 'U_0' of 'rsff'
   SIGNAL mw_U_0reg_cval : std_logic;

   -- ModuleWare signal declarations(v1.12) for instance 'U_4' of 'rsff'
   SIGNAL mw_U_4reg_cval : std_logic;

   -- ModuleWare signal declarations(v1.12) for instance 'U_5' of 'rsff'
   SIGNAL mw_U_5reg_cval : std_logic;

   -- ModuleWare signal declarations(v1.12) for instance 'U_6' of 'rsff'
   SIGNAL mw_U_6reg_cval : std_logic;


BEGIN

   -- ModuleWare code(v1.12) for instance 'U_1' of 'cntr'
   EtatLu(3 DOWNTO 0) <= mw_U_1c_cnt;
   u_1clock_proc: PROCESS (H, nCLR)
   BEGIN
      IF (nCLR = '0') THEN
         mw_U_1c_cnt <= "0000";
      ELSIF (H'EVENT AND H='1') THEN
         IF (dout1 = '1') THEN
            mw_U_1c_cnt <= mw_U_1n_cnt;
         END IF;
      END IF;
   END PROCESS u_1clock_proc;
   u_1combo_proc: PROCESS (NbRecByte_RST, dout, dout2, mw_U_1c_cnt)
   -- up = '1', dn = '0'
   BEGIN
      IF (NbRecByte_RST = '1') THEN
         mw_U_1n_cnt <= dout;
      ELSE
         IF (dout2 = '1') THEN
            IF (mw_U_1c_cnt = "1111") THEN
               mw_U_1n_cnt <= (OTHERS => '0');
            ELSE
               mw_U_1n_cnt <= (unsigned(mw_U_1c_cnt) + '1');
            END IF;
         ELSE
            IF (mw_U_1c_cnt = "0000") THEN
               mw_U_1n_cnt <= "0000";
            ELSE
               mw_U_1n_cnt <= (unsigned(mw_U_1c_cnt) - '1');
            END IF;
         END IF;
      END IF;
   END PROCESS u_1combo_proc;

   -- ModuleWare code(v1.12) for instance 'U_2' of 'constval'
   dout <= "0000";

   -- ModuleWare code(v1.12) for instance 'U_7' of 'inv'
   dout2 <= NOT(NbByteDec);

   -- ModuleWare code(v1.12) for instance 'U_3' of 'or'
   dout1 <= NbByteInc OR NbByteDec;

   -- ModuleWare code(v1.12) for instance 'U_0' of 'rsff'
   EtatLu(4) <= mw_U_0reg_cval;
   u_0seq_proc: PROCESS (H, nCLR)
   BEGIN
      IF (nCLR = '0') THEN
         mw_U_0reg_cval <= '0';
      ELSIF (H'EVENT AND H='1') THEN
         IF (EtatLu_RST = '1') THEN
            mw_U_0reg_cval <= '0';
         ELSIF (MessageReceived_SET = '1') THEN
            mw_U_0reg_cval <= '1';
         END IF;
      END IF;
   END PROCESS u_0seq_proc;

   -- ModuleWare code(v1.12) for instance 'U_4' of 'rsff'
   EtatLu(7) <= mw_U_4reg_cval;
   u_4seq_proc: PROCESS (H, nCLR)
   BEGIN
      IF (nCLR = '0') THEN
         mw_U_4reg_cval <= '0';
      ELSIF (H'EVENT AND H='1') THEN
         IF (EtatLu_RST = '1') THEN
            mw_U_4reg_cval <= '0';
         ELSIF (Errors_SET(3) = '1') THEN
            mw_U_4reg_cval <= '1';
         END IF;
      END IF;
   END PROCESS u_4seq_proc;

   -- ModuleWare code(v1.12) for instance 'U_5' of 'rsff'
   EtatLu(6) <= mw_U_5reg_cval;
   u_5seq_proc: PROCESS (H, nCLR)
   BEGIN
      IF (nCLR = '0') THEN
         mw_U_5reg_cval <= '0';
      ELSIF (H'EVENT AND H='1') THEN
         IF (EtatLu_RST = '1') THEN
            mw_U_5reg_cval <= '0';
         ELSIF (Errors_SET(2) = '1') THEN
            mw_U_5reg_cval <= '1';
         END IF;
      END IF;
   END PROCESS u_5seq_proc;

   -- ModuleWare code(v1.12) for instance 'U_6' of 'rsff'
   EtatLu(5) <= mw_U_6reg_cval;
   u_6seq_proc: PROCESS (H, nCLR)
   BEGIN
      IF (nCLR = '0') THEN
         mw_U_6reg_cval <= '0';
      ELSIF (H'EVENT AND H='1') THEN
         IF (EtatLu_RST = '1') THEN
            mw_U_6reg_cval <= '0';
         ELSIF (Errors_SET(1) = '1') THEN
            mw_U_6reg_cval <= '1';
         END IF;
      END IF;
   END PROCESS u_6seq_proc;

   -- Instance port mappings.

END struct;