106 lines
2.3 KiB
VHDL
106 lines
2.3 KiB
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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ENTITY EnvTest_InterfaceMicroprocesseur IS
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GENERIC(
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CLOCK_PERIOD : time := 50 ns;
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RESET_OFFSET : time := 500 ns;
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RESET_DURATION : time := 300 ns;
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ACCESS_TIME : time := 40 ns;
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HOLD_TIME : time := 70 ns
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);
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PORT(
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M_Received : IN std_logic;
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CnD : OUT std_logic;
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H : OUT std_logic;
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RnW : OUT std_logic;
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nCS : OUT std_logic;
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nRST : OUT std_logic;
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D07 : INOUT std_logic_vector (7 DOWNTO 0)
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);
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-- Declarations
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END EnvTest_InterfaceMicroprocesseur ;
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--
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ARCHITECTURE arch OF EnvTest_InterfaceMicroprocesseur IS
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TYPE DefState IS (Waiting, DataReading, StateReading, FilterWriting);
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SIGNAL ProcessorState : DefState;
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BEGIN
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ClockGeneratorProc : PROCESS
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BEGIN
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H <= '0';
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WAIT FOR CLOCK_PERIOD/2;
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H <= '1';
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WAIT FOR CLOCK_PERIOD/2;
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END PROCESS ClockGeneratorProc;
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ResetGeneratorProc : PROCESS
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BEGIN
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nRST <= '1';
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WAIT FOR RESET_OFFSET;
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nRST <= '0';
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WAIT FOR RESET_DURATION;
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nRST <= '1';
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WAIT;
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END PROCESS ResetGeneratorProc;
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ProcessorBehaviorProc : PROCESS
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BEGIN
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D07 <= (others => 'Z');
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--Waiting cycle--
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ProcessorState <= Waiting;
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nCS <= '1';
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CnD <= '1';
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RnW <= '1';
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WAIT FOR RESET_OFFSET+RESET_DURATION+2*CLOCK_PERIOD;
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--Reading data cycle--
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ProcessorState <= DataReading;
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WAIT FOR ACCESS_TIME;
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nCS <= '0';
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CnD <= '0';
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RnW <= '1';
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WAIT FOR 2*CLOCK_PERIOD;
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--Waiting cycle--
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ProcessorState <= Waiting;
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nCS <= '1';
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CnD <= '1';
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RnW <= '1';
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WAIT FOR 2*CLOCK_PERIOD-ACCESS_TIME;
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--Reading state cycle--
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ProcessorState <= StateReading;
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WAIT FOR ACCESS_TIME;
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nCS <= '0';
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CnD <= '1';
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RnW <= '1';
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WAIT FOR 2*CLOCK_PERIOD;
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--Waiting cycle--
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ProcessorState <= Waiting;
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nCS <= '1';
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CnD <= '1';
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RnW <= '1';
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WAIT FOR 2*CLOCK_PERIOD-ACCESS_TIME;
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--Writing cycle--
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ProcessorState <= FilterWriting;
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WAIT FOR ACCESS_TIME;
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nCS <= '0';
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CnD <= '0';
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RnW <= '0';
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D07 <= (others => '1');
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WAIT FOR 2*CLOCK_PERIOD;
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--Waiting cycle--
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ProcessorState <= Waiting;
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nCS <= '1';
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CnD <= '1';
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RnW <= '1';
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WAIT FOR HOLD_TIME;
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D07 <= (others => 'Z');
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WAIT;
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END PROCESS ProcessorBehaviorProc;
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END ARCHITECTURE arch;
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