linreceiver-vhdl/ReceptionTrame_lib/receptionTrame_com.vhd

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY receptionTrame_com IS
  PORT(
    H: IN std_logic;
    nRST: IN std_logic;
    LinSynchro: IN std_logic;

    octetRecu_EN: OUT std_logic;
    
    n_SELECT: OUT std_logic;
    n_LOAD: OUT std_logic;
    n_EN: OUT std_logic;

    nbBit_SELECT: OUT std_logic;
    nbBit_LOAD: OUT std_logic;
    nbBit_EN: OUT std_logic;

    identifier_EN: OUT std_logic;

    nbData_LOAD: OUT std_logic;
    nbData_EN: OUT std_logic;
    
    n_0: IN std_logic;
    nbBit_0: IN std_logic;
    nbData_0: IN std_logic
  );
END receptionTrame_com;

ARCHITECTURE arch of receptionTrame_com IS
TYPE state IS (waiting, syncBreak0, syncBreak1, syncFieldWait, syncFieldStart, syncFieldData, syncFieldStop, idFieldWait);
SIGNAL cState, nState : state;
BEGIN

stateUpd : PROCESS(H, nRST)
BEGIN
  IF(nRST = '0') THEN
    cState <= waiting;
  ELSIF(rising_edge(H)) THEN
    cState <= nState;
  END IF;
END process stateUpd;

nStateUpd : PROCESS(LinSynchro, cState, n_0, nbBit_0)
BEGIN
nState <= cState;
CASE cState IS
  WHEN waiting =>
    if(LinSynchro = '0') THEN
      nState <= syncBreak0;
    END IF;
    
  WHEN syncBreak0 =>
    if(LinSynchro = '1') THEN
      if(nbBit_0 = '1') THEN
        nState <= syncBreak1;
      else
        nState <= waiting;
      END IF;
    END IF;
    
  WHEN syncBreak1 =>
    if(n_0 = '1') THEN
      if(LinSynchro = '1') THEN
        nState <= syncFieldWait;
      else
        nState <= waiting;
      end if;
    END IF;

  WHEN syncFieldWAit =>
    if(LinSynchro = '0') THEN
      nState <= syncFieldStart;
    END IF;

  WHEN syncFieldStart =>
    if(n_0 = '1') THEN
      IF(LinSynchro = '0') THEN
        nState <= syncFieldData;
      else
        nState <= waiting;
      END IF;
    end if;

  WHEN syncFieldData =>
    if(nbBit_0 = '1') THEN
      nState <= syncFieldStop;
    END IF;

  WHEN syncFieldStop =>
    if(n_0 = '1') THEN
      if(LinSynchro = '1') THEN
        nState <= idFieldWait;
      else
        nState <= waiting;
      end if;
    end if;

  WHEN others =>
  end CASE;
END PROCESS nStateUpd;

RCS : PROCESS(cState, LinSynchro, n_0)
BEGIN
  CASE cState IS
    WHEN waiting =>
      if(LinSynchro = '0') THEN
        n_LOAD <= '1';
        n_SELECT <= '1';
        nbBit_LOAD <= '1';
        nbBit_SELECT <= '0';
      end IF;
    WHEN syncBreak0 =>
      if(LinSynchro = '1') then
        if(nbBit_0 = '1') then
          n_LOAD <= '1';
          n_SELECT <= '0';
        else
          -- ERROR sync break
        end if;
      else
        if(n_0 = '1') then
          n_select <= '0';
          n_LOAD <= '1';
          nbBit_EN <= '1';
        else
          n_LOAD <= '0';
          nbBit_EN <= '0';
        end if;
        n_EN <= '1';
        nbBit_LOAD <= '0';
      end if;
    WHEN syncBreak1 =>
      if(n_0 = '1') then
        if(LinSynchro = '0') then
          -- ERROR sync stop
        end if;
      else
        n_LOAD <= '0';
        n_EN <= '1';
      end if;
    WHEN syncFieldWait =>
      if(LinSynchro = '0') then
          n_LOAD <= '1';
          n_SELECT <= '1';
      end if;
    WHEN syncFieldStart =>
      if(n_0 = '1') then
        if(LinSynchro = '0') then
          n_SELECT <= '0';
          n_LOAD <= '1';
          nbBit_SELECT <= '1';
          nbBit_LOAD <= '1';
        else
          -- ERROR start bit
        end if;
      else
        n_LOAD <= '0';
        n_EN <= '1';
      end if;
    WHEN syncFieldData =>
      if(nbBit_0 = '1') then
        n_SELECT <= '0';
        n_LOAD <= '1';
        octetRecu_EN <= '0';
      else
        if(n_0 = '1') then
          n_LOAD <= '1';
          n_SELECT <= '0';
          nbBit_EN <= '1';
          octetRecu_EN <= '1';
        else
          n_LOAD <= '0';
          nbBit_EN <= '0';
          octetRecu_EN <= '0';
        end if;
        nbBit_LOAD <= '0';
      end if;
    WHEN others =>
      
  end CASE;
END PROCESS RCS;

END ARCHITECTURE arch;