linreceiver-vhdl/ReceptionTrame_lib/receptionTrame_tb.vhd

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY receptionTrame_tb IS
  GENERIC(
    CLOCK_PERIOD: time := 52 us;
    UC_CLK_PERIOD: time := 43 ns
  );
END receptionTrame_tb;

ARCHITECTURE arch of receptionTrame_tb IS
SIGNAL Lin: std_logic;
SIGNAL H: std_logic;

SIGNAL octetRecu_EN : std_logic;
SIGNAL n_SELECT: std_logic;
SIGNAL n_LOAD: std_logic;
SIGNAL n_EN: std_logic;

SIGNAL nbBit_SELECT: std_logic;
SIGNAL nbBit_LOAD: std_logic;
SIGNAL nbBit_EN: std_logic;

SIGNAL identifier_EN: std_logic;

SIGNAL nbData_LOAD: std_logic;
SIGNAL nbData_EN: std_logic;

SIGNAL LinSynchro: std_logic;
    
SIGNAL n_0: std_logic;
SIGNAL nbBit_0: std_logic;
SIGNAL nbData_0: std_logic;

COMPONENT receptionTrame_op
  GENERIC(
    N: integer := 1200;
    N_WIDTH : integer := 11
  );
  PORT(
    H: IN std_logic;
    nCLR: IN std_logic;
    Lin: IN std_logic;

    octetRecu_EN : IN std_logic;
    
    n_SELECT: IN std_logic;
    n_LOAD: IN std_logic;
    n_EN: IN std_logic;

    nbBit_SELECT: IN std_logic;
    nbBit_LOAD: IN std_logic;
    nbBit_EN: IN std_logic;

    identifier_EN: IN std_logic;

    nbData_LOAD: IN std_logic;
    nbData_EN: IN std_logic;

    LinSynchro: OUT std_logic;
    
    n_0: OUT std_logic;
    nbBit_0: OUT std_logic;
    nbData_0: OUT std_logic;

    identifier: OUT std_logic_vector(5 downto 0);
    octetRecu: OUT std_logic_vector(7 downto 0)
  );
END COMPONENT;

COMPONENT receptionTrame_com
  PORT(
    H: IN std_logic;
    nRST: IN std_logic;
    LinSynchro: IN std_logic;

    octetRecu_EN: OUT std_logic;
    
    n_SELECT: OUT std_logic;
    n_LOAD: OUT std_logic;
    n_EN: OUT std_logic;

    nbBit_SELECT: OUT std_logic;
    nbBit_LOAD: OUT std_logic;
    nbBit_EN: OUT std_logic;

    identifier_EN: OUT std_logic;

    nbData_LOAD: OUT std_logic;
    nbData_EN: OUT std_logic;
    
    n_0: IN std_logic;
    nbBit_0: IN std_logic;
    nbData_0: IN std_logic
  );
END COMPONENT receptionTrame_com;
BEGIN

U0 : receptionTrame_op
  GENERIC MAP(
    N => 1200,
    N_WIDTH => 11
  )
  PORT MAP(
    H => H,
    nCLR => '1',
    Lin => Lin,

    octetRecu_EN => octetRecu_EN,
    n_SELECT => n_SELECT,
    n_LOAD => n_LOAD,
    n_EN => n_EN,
    nbBit_SELECT => nbBit_SELECT,
    nbBit_LOAD => nbBit_LOAD,
    nbBit_EN => nbBit_EN,
    identifier_EN => identifier_EN,
    nbData_LOAD => nbData_LOAD,
    nbData_EN => nbData_EN,
    LinSynchro => LinSynchro,
    n_0 => n_0,
    nbBit_0 => nbBit_0,
    nbData_0 => nbData_0
  );

U1 : receptionTrame_com
  PORT MAP(
    H => H,
    nRST => '1',
    LinSynchro => LinSynchro,

    octetRecu_EN => octetRecu_EN,
    
    n_SELECT => n_SELECT,
    n_LOAD => n_LOAD,
    n_EN => n_EN,

    nbBit_SELECT => nbBit_SELECT,
    nbBit_LOAD => nbBit_LOAD,
    nbBit_EN => nbBit_EN,

    identifier_EN => identifier_EN,

    nbData_LOAD => nbData_LOAD,
    nbData_EN => nbData_EN,
    
    n_0 => n_0,
    nbBit_0 => nbBit_0,
    nbData_0 => nbData_0
  );

clkGen : PROCESS
BEGIN
  H <= '1';
  WAIT FOR UC_CLK_PERIOD / 2;
  H <= '0';
  WAIT FOR UC_CLK_PERIOD / 2;
END PROCESS clkGen;

linFrame : PROCESS
BEGIN
  Lin <= '1';
  WAIT FOR 100 us;
  -- Sync Break
  Lin <= '0';
  WAIT FOR 14 * CLOCK_PERIOD;
  Lin <= '1';
  WAIT FOR 2 * CLOCK_PERIOD;

  -- Sync field
  for i in 4 downto 0 loop
    Lin <= '0';
    WAIT FOR CLOCK_PERIOD;
    Lin <= '1';
    WAIT FOR CLOCK_PERIOD;
  end loop;

  -- ID field (0x0, 2 data byte)
  Lin <= '0';
  WAIT FOR CLOCK_PERIOD;
  Lin <= '0';
  WAIT FOR 8 * CLOCK_PERIOD;
  Lin <= '1';
  WAIT FOR CLOCK_PERIOD;

  -- data fields (both 0x00)
  Lin <= '0';
  WAIT FOR 8 * CLOCK_PERIOD;
  Lin <= '1';
  WAIT FOR CLOCK_PERIOD;

  Lin <= '0';
  WAIT FOR 8 * CLOCK_PERIOD;
  Lin <= '1';
  WAIT FOR CLOCK_PERIOD;

  -- checksum (0x0)
  Lin <= '0';
  WAIT FOR 8 * CLOCK_PERIOD;
  Lin <= '1';
  WAIT FOR CLOCK_PERIOD;

  report "Finished"  severity failure ;

END PROCESS;

END ARCHITECTURE arch;