161 lines
3.1 KiB
VHDL
161 lines
3.1 KiB
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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ENTITY receptionTrame IS
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PORT(
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H: IN std_logic;
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nCLR: IN std_logic;
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Lin: IN std_logic;
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AdrSel: IN std_logic_vector;
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RecByte: OUT std_logic_vector(7 downto 0);
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RecByte_WR: OUT std_logic;
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RecBytes_RST: OUT std_logic;
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Err_SET: OUT std_logic_vector(2 downto 0);
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NbByteInc: OUT std_logic;
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MsgReceived_SET: OUT std_logic;
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NbRecByte_RST: OUT std_logic
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);
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END receptionTrame;
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ARCHITECTURE arch OF receptionTrame IS
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SIGNAL octetRecu_EN : std_logic;
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SIGNAL n_SELECT: std_logic;
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SIGNAL n_LOAD: std_logic;
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SIGNAL n_EN: std_logic;
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SIGNAL nbBit_SELECT: std_logic;
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SIGNAL nbBit_LOAD: std_logic;
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SIGNAL nbBit_EN: std_logic;
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SIGNAL identifier_EN: std_logic;
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SIGNAL nbData_LOAD: std_logic;
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SIGNAL nbData_EN: std_logic;
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SIGNAL LinSynchro: std_logic;
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SIGNAL n_0: std_logic;
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SIGNAL nbBit_0: std_logic;
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SIGNAL nbData_0: std_logic;
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COMPONENT receptionTrame_op
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GENERIC(
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N: integer := 1200;
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N_WIDTH : integer := 11
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);
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PORT(
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H: IN std_logic;
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nCLR: IN std_logic;
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Lin: IN std_logic;
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octetRecu_EN : IN std_logic;
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n_SELECT: IN std_logic;
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n_LOAD: IN std_logic;
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n_EN: IN std_logic;
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nbBit_SELECT: IN std_logic;
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nbBit_LOAD: IN std_logic;
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nbBit_EN: IN std_logic;
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identifier_EN: IN std_logic;
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nbData_LOAD: IN std_logic;
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nbData_EN: IN std_logic;
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LinSynchro: OUT std_logic;
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n_0: OUT std_logic;
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nbBit_0: OUT std_logic;
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nbData_0: OUT std_logic;
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identifier: OUT std_logic_vector(5 downto 0);
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octetRecu: OUT std_logic_vector(7 downto 0)
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);
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END COMPONENT;
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COMPONENT receptionTrame_com
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PORT(
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H: IN std_logic;
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nRST: IN std_logic;
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LinSynchro: IN std_logic;
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octetRecu_EN: OUT std_logic;
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n_SELECT: OUT std_logic;
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n_LOAD: OUT std_logic;
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n_EN: OUT std_logic;
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nbBit_SELECT: OUT std_logic;
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nbBit_LOAD: OUT std_logic;
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nbBit_EN: OUT std_logic;
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identifier_EN: OUT std_logic;
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nbData_LOAD: OUT std_logic;
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nbData_EN: OUT std_logic;
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n_0: IN std_logic;
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nbBit_0: IN std_logic;
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nbData_0: IN std_logic
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);
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END COMPONENT receptionTrame_com;
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BEGIN
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U0 : receptionTrame_op
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GENERIC MAP(
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N => 1200,
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N_WIDTH => 11
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)
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PORT MAP(
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H => H,
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nCLR => '1',
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Lin => Lin,
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octetRecu_EN => octetRecu_EN,
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n_SELECT => n_SELECT,
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n_LOAD => n_LOAD,
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n_EN => n_EN,
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nbBit_SELECT => nbBit_SELECT,
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nbBit_LOAD => nbBit_LOAD,
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nbBit_EN => nbBit_EN,
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identifier_EN => identifier_EN,
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nbData_LOAD => nbData_LOAD,
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nbData_EN => nbData_EN,
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LinSynchro => LinSynchro,
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n_0 => n_0,
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nbBit_0 => nbBit_0,
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nbData_0 => nbData_0
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);
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U1 : receptionTrame_com
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PORT MAP(
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H => H,
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nRST => '1',
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LinSynchro => LinSynchro,
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octetRecu_EN => octetRecu_EN,
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n_SELECT => n_SELECT,
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n_LOAD => n_LOAD,
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n_EN => n_EN,
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nbBit_SELECT => nbBit_SELECT,
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nbBit_LOAD => nbBit_LOAD,
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nbBit_EN => nbBit_EN,
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identifier_EN => identifier_EN,
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nbData_LOAD => nbData_LOAD,
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nbData_EN => nbData_EN,
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n_0 => n_0,
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nbBit_0 => nbBit_0,
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nbData_0 => nbData_0
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);
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END ARCHITECTURE arch; |