226 lines
7.5 KiB
VHDL
226 lines
7.5 KiB
VHDL
-- VHDL Entity RecepteurLIN_lib.FrameReception.symbol
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--
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-- Created:
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-- by - e208835u.UNKNOWN (irb013-09)
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-- at - 12:46:30 17/10/2023
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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ENTITY FrameReception IS
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PORT(
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H : IN std_logic;
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Lin : IN std_logic;
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SelAdr : IN std_logic_vector (7 DOWNTO 0);
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nRST : IN std_logic;
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ErrorSet : OUT std_logic_vector (3 DOWNTO 1);
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MsgRcv_SET : OUT std_logic;
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NbRecByte_Inc : OUT std_logic;
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RecByte : OUT std_logic_vector (7 DOWNTO 0);
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RecByte_RST : OUT std_logic;
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RecByte_WR : OUT std_logic
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);
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-- Declarations
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END FrameReception ;
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--
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-- VHDL Architecture RecepteurLIN_lib.FrameReception.struct
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--
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-- Created:
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-- by - e208835u.UNKNOWN (irb013-09)
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-- at - 12:46:30 17/10/2023
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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-- LIBRARY RecepteurLIN_lib;
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ARCHITECTURE struct OF FrameReception IS
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-- Architecture declarations
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-- Internal signal declarations
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SIGNAL BitNb_EN : std_logic;
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SIGNAL BitNb_SELECT : std_logic;
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SIGNAL BitsNb_0 : std_logic;
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SIGNAL BitsNb_LOAD : std_logic;
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SIGNAL DataFieldNb : std_logic_vector(2 DOWNTO 0);
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SIGNAL DataFieldNb_0 : std_logic;
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SIGNAL DataFieldNb_LOAD : std_logic;
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SIGNAL IdentifierField : std_logic_vector(5 DOWNTO 0);
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SIGNAL LinSynchro : std_logic;
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SIGNAL dout : std_logic;
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SIGNAL identifier_EN : std_logic;
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SIGNAL n_0 : std_logic;
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SIGNAL n_EN : std_logic;
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SIGNAL n_LOAD : std_logic;
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SIGNAL n_SELECT : std_logic;
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SIGNAL nbData_EN : std_logic;
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SIGNAL octetRecu_EN : std_logic;
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SIGNAL RecByte_WR_int : std_logic;
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-- Component Declarations
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COMPONENT Command_Unit
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PORT (
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BitNb_0 : IN std_logic;
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DataNb_0 : IN std_logic;
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H : IN std_logic;
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LinSynchro : IN std_logic;
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nRST : IN std_logic;
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n_0 : IN std_logic;
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BitNb_EN : OUT std_logic;
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BitNb_LOAD : OUT std_logic;
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BitNb_SELECT : OUT std_logic;
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ErrorSet : OUT std_logic_vector (3 DOWNTO 1);
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IdentifierField_EN : OUT std_logic;
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MsgRcv_SET : OUT std_logic;
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RecByte_RST : OUT std_logic := '0';
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RecByte_WR : OUT std_logic;
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n_EN : OUT std_logic;
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n_LOAD : OUT std_logic;
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n_SELECT : OUT std_logic;
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nbData_EN : OUT std_logic;
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nbData_LOAD : OUT std_logic;
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octetRecu_EN : OUT std_logic
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);
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END COMPONENT;
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COMPONENT FrameReceptionOP
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GENERIC (
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N : std_logic_vector := "10000000000"
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);
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PORT (
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BitsNb_EN : IN std_logic ;
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BitsNb_LOAD : IN std_logic ;
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BitsNb_SELECT : IN std_logic ;
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DataFieldNb_EN : IN std_logic ;
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DataFieldNb_LOAD : IN std_logic ;
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H : IN std_logic ;
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IdentifierField_EN : IN std_logic ;
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Lin : IN std_logic ;
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RecByte_EN : IN std_logic ;
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nCLR : IN std_logic ;
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n_EN : IN std_logic ;
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n_LOAD : IN std_logic ;
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n_SELECT : IN std_logic ;
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BitsNb_0 : OUT std_logic ;
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DataFieldNb : OUT std_logic_vector (2 DOWNTO 0);
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DataFieldNb_0 : OUT std_logic ;
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IdentifierField : OUT std_logic_vector (5 DOWNTO 0);
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LinSynchro : OUT std_logic ;
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RecByte : OUT std_logic_vector (7 DOWNTO 0);
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n_0 : OUT std_logic
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);
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END COMPONENT;
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-- Optional embedded configurations
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-- pragma synthesis_off
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-- FOR ALL : Command_Unit USE ENTITY RecepteurLIN_lib.Command_Unit;
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-- FOR ALL : FrameReceptionOP USE ENTITY RecepteurLIN_lib.FrameReceptionOP;
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-- pragma synthesis_on
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BEGIN
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NbRecByte_Inc <= RecByte_WR_int;
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RecByte_WR <= RecByte_WR_int;
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-- ModuleWare code(v1.12) for instance 'U_2' of 'pbuf'
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-- u_2seq_proc: PROCESS (octetRecu_EN)
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-- BEGIN
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-- IF (octetRecu_EN ='1' ) THEN
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-- NbRecByte_Inc <= '1';
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-- ELSIF (octetRecu_EN ='H' ) THEN
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-- NbRecByte_Inc <= '1';
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-- ELSIF (octetRecu_EN ='0' ) THEN
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-- NbRecByte_Inc <= '0';
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-- ELSIF (octetRecu_EN ='L' ) THEN
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-- NbRecByte_Inc <= '0';
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-- ELSIF (octetRecu_EN ='U' ) THEN
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-- NbRecByte_Inc <= 'U';
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-- ELSIF (octetRecu_EN ='X' ) THEN
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-- NbRecByte_Inc <= 'X';
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-- ELSIF (octetRecu_EN ='Z' ) THEN
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-- NbRecByte_Inc <= 'X';
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-- END IF;
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-- END PROCESS u_2seq_proc;
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-- ModuleWare code(v1.12) for instance 'U_3' of 'pbuf'
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u_3seq_proc: PROCESS (octetRecu_EN)
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BEGIN
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IF (octetRecu_EN ='1' ) THEN
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dout <= '1';
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ELSIF (octetRecu_EN ='H' ) THEN
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dout <= '1';
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ELSIF (octetRecu_EN ='0' ) THEN
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dout <= '0';
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ELSIF (octetRecu_EN ='L' ) THEN
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dout <= '0';
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ELSIF (octetRecu_EN ='U' ) THEN
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dout <= 'U';
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ELSIF (octetRecu_EN ='X' ) THEN
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dout <= 'X';
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ELSIF (octetRecu_EN ='Z' ) THEN
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dout <= 'X';
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END IF;
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END PROCESS u_3seq_proc;
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-- Instance port mappings.
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U_0 : Command_Unit
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PORT MAP (
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H => H,
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nRST => nRST,
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LinSynchro => LinSynchro,
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octetRecu_EN => octetRecu_EN,
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n_SELECT => n_SELECT,
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n_LOAD => n_LOAD,
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n_EN => n_EN,
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BitNb_SELECT => BitNb_SELECT,
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BitNb_LOAD => BitsNb_LOAD,
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BitNb_EN => BitNb_EN,
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IdentifierField_EN => identifier_EN,
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nbData_LOAD => DataFieldNb_LOAD,
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nbData_EN => nbData_EN,
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n_0 => n_0,
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BitNb_0 => BitsNb_0,
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DataNb_0 => DataFieldNb_0,
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RecByte_WR => RecByte_WR_int,
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RecByte_RST => RecByte_RST,
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ErrorSet => ErrorSet,
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MsgRcv_SET => MsgRcv_SET
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);
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U_1 : FrameReceptionOP
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GENERIC MAP (
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N => "10000000000"
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)
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PORT MAP (
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BitsNb_EN => BitNb_EN,
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BitsNb_LOAD => BitsNb_LOAD,
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BitsNb_SELECT => BitNb_SELECT,
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DataFieldNb_EN => nbData_EN,
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DataFieldNb_LOAD => DataFieldNb_LOAD,
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H => H,
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IdentifierField_EN => identifier_EN,
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Lin => Lin,
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RecByte_EN => dout,
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nCLR => nRST,
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n_EN => n_EN,
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n_LOAD => n_LOAD,
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n_SELECT => n_SELECT,
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BitsNb_0 => BitsNb_0,
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DataFieldNb => DataFieldNb,
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DataFieldNb_0 => DataFieldNb_0,
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IdentifierField => IdentifierField,
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LinSynchro => LinSynchro,
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RecByte => RecByte,
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n_0 => n_0
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);
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END struct;
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