linreceiver-vhdl/STDLIB_lib/stdlib_tb.vhd

LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;

ENTITY stdlib_tb IS
  GENERIC(
    CLOCK_PERIOD : time := 10 ns
  );
END stdlib_tb;

ARCHITECTURE arch of stdlib_tb IS
SIGNAL CLK : std_logic;

SIGNAL D_FF_D : std_logic;
SIGNAL D_FF_Rst : std_logic;
SIGNAL D_FF_Q : std_logic;

SIGNAL D_FFb_D : std_logic_vector(7 downto 0);
SIGNAL D_FFb_Rst : std_logic;
SIGNAL D_FFb_Q : std_logic_vector(7 downto 0);

SIGNAL SR_D : std_logic;
SIGNAL SR_Rst : std_logic;
SIGNAL SR_Q : std_logic_vector(7 downto 0);

SIGNAL CNT_Rst : std_logic;
SIGNAL CNT_INIT : unsigned(2 downto 0);
SIGNAL CNT_LOAD : std_logic;
SIGNAL CNT_max : std_logic;

COMPONENT D_FF
  PORT(
    H: IN std_logic;
    H_EN: IN std_logic;
    D: IN std_logic;
    nRst: IN std_logic;
    Q: OUT std_logic
  );
END COMPONENT;

COMPONENT D_FF_BANK
  PORT(
    H: IN std_logic;
    H_EN: IN std_logic;
    D: IN std_logic_vector;
    nRst: IN std_logic;
    Q: OUT std_logic_vector
  );
END COMPONENT;

COMPONENT shift_register
  GENERIC(
    WIDTH: integer
  );
  PORT(
    H: IN std_logic;
    H_EN: IN std_logic;
    nRst : IN std_logic;
    D: IN std_logic;
    Q: OUT std_logic_vector
  );
END COMPONENT;

COMPONENT counter
  GENERIC(
    WIDTH: integer;
    MAX_VAL: integer
  );
  PORT(
    H: IN std_logic;
    H_EN: IN std_logic;
    nRst: IN std_logic;
    INIT: IN unsigned(WIDTH-1 downto 0);
    LOAD: IN std_logic;
    upnDown: IN std_logic;

    val: OUT unsigned(WIDTH-1 downto 0);
    max: OUT std_logic
  );
END COMPONENT;

BEGIN

CLK_gen : PROCESS
BEGIN
  CLK <= '0';
  WAIT FOR CLOCK_PERIOD/2;
  CLK <= '1';
  WAIT FOR CLOCK_PERIOD/2;
END PROCESS CLK_gen;

D_FF_test : PROCESS
BEGIN
  D_FF_Rst <= '0';
  
  WAIT UNTIL CLK = '1';
  D_FF_Rst <= '1';
  D_FF_D <= '1';
  
  WAIT UNTIL CLK = '0';
  assert D_FF_Q = '0' report "D_FF set before clk" severity error;

  WAIT UNTIL CLK = '0';
  assert D_FF_Q = '1' report "D_FF not set" severity error;
  D_FF_Rst <= '0';
  
  WAIT UNTIL CLK = '0';
  assert D_FF_Q = '0' report "D_FF reset error" severity error;
END PROCESS D_FF_test;

D_FFb_test : PROCESS
BEGIN
  D_FFb_Rst <= '0';
  
  WAIT UNTIL CLK = '1';
  D_FFb_Rst <= '1';
  D_FFb_D <= "01010101";
  
  WAIT UNTIL CLK = '0';
  assert D_FFb_Q = "00000000" report "D_FF_bank set before clk" severity error;

  WAIT UNTIL CLK = '0';
  assert D_FFb_Q = "01010101" report "D_FF_bank not set" severity error;
  D_FFb_Rst <= '0';
  
  WAIT UNTIL CLK = '0';
  assert D_FFb_Q = "00000000" report "D_FF_bank reset error" severity error;
END PROCESS D_FFb_test;

SR_test : PROCESS
BEGIN
  SR_Rst <= '0';
  SR_D <= '1';

  WAIT UNTIL CLK = '1';
  SR_Rst <= '1';
  for i in SR_Q'RANGE loop
    SR_D <= not SR_D;
    WAIT UNTIL CLK = '1';
  end loop;
  WAIT UNTIL CLK = '1';
  assert SR_Q = "01010101" report "shift register wrong output" severity error;
  SR_Rst <= '0';

  WAIT UNTIL CLK = '0';
  assert SR_Q = "00000000" report "shft register reset error" severity error;
END PROCESS SR_test;

CNT_test : PROCESS
BEGIN
  CNT_Rst <= '0';
  CNT_INIT <= to_unsigned(7, 3);
  
  WAIT UNTIL CLK = '1';
  CNT_Rst <= '1';
  
  WAIT UNTIL CLK = '1';
  assert CNT_max = '1' report "counter reset error" severity error;
  CNT_LOAD <= '1';
  
  WAIT UNTIL CLK = '1';
  WAIT UNTIL CLK = '0';
  CNT_LOAD <= '0';
  WAIT UNTIL CLK = '1';

  for i in 6 downto 0 loop
    assert CNT_max = '0' report "counter count down error" severity error;
    WAIT UNTIL CLK = '1';
  end loop;

  assert CNT_max = '1' report "counter count down to zero error" severity error;
  
END PROCESS CNT_test;

U0 : D_FF
  PORT MAP (
    H => CLK,
    H_EN => '1',
    D => D_FF_D,
    nRst => D_FF_Rst,
    Q => D_FF_Q
  );

U1 : D_FF_BANK
  PORT MAP(
    H => CLK,
    H_EN => '1',
    D => D_FFb_D,
    nRst => D_FFb_Rst,
    Q => D_FFb_Q
  );

U2 : shift_register
  GENERIC MAP(
    WIDTH => SR_Q'LENGTH
  )
  PORT MAP(
    H => CLK,
    H_EN => '1',
    nRst => SR_Rst,
    D => SR_D,
    Q => SR_Q
  );

U3 : counter
  GENERIC MAP(
    WIDTH => 3,
    MAX_VAL => 0
  )
  PORT MAP(
    H => CLK,
    H_EN => '1',
    nRst => CNT_Rst,
    INIT => CNT_INIT,
    LOAD => CNT_LOAD,
    upnDown => '0',
    val => OPEN,
    max => CNT_max
  );

END ARCHITECTURE arch;