38 lines
631 B
VHDL
38 lines
631 B
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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ENTITY D_FF_BANK IS
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PORT(
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H: IN std_logic;
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H_EN: IN std_logic;
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nRst : IN std_logic;
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D: IN std_logic_vector;
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Q: OUT std_logic_vector
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);
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END D_FF_BANK;
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ARCHITECTURE arch OF D_FF_BANK IS
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COMPONENT D_FF
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PORT(
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H: IN std_logic;
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H_EN: IN std_logic;
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D: IN std_logic;
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nRst: IN std_logic;
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Q: OUT std_logic
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);
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END COMPONENT;
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BEGIN
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bank_generate : for i in D'RANGE generate
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DFF_X : D_FF port map(
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H => H,
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H_EN => H_EN,
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D => D(i),
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nRst => nRst,
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Q => Q(i)
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);
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end generate;
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END ARCHITECTURE arch; |