linreceiver-vhdl/ReceptionTrame_lib/receptionTrame_op.vhd
2023-09-25 18:38:01 +02:00

105 lines
1.9 KiB
VHDL

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY receptionTrame_op IS
GENERIC(
N: integer := 1200
);
PORT(
H: IN std_logic;
nCLR: IN std_logic;
Lin: IN std_logic;
octetRecu_EN : IN std_logic;
n_SELECT: IN std_logic;
n_LOAD: IN std_logic;
n_EN: IN std_logic;
nbBit_SELECT: IN std_logic;
nbBit_LOAD: IN std_logic;
nbBit_EN: IN std_logic;
identifier_EN: IN std_logic;
nbData_LOAD: IN std_logic;
nbData_EN: IN std_logic;
LinSynchro: OUT std_logic;
n_0: OUT std_logic;
nbBit_0: OUT std_logic;
nbData_0: OUT std_logic;
identifier: OUT std_logic_vector(5 downto 0);
octetRecu: OUT std_logic_vector(7 downto 0)
);
END receptionTrame_op;
ARCHITECTURE arch OF receptionTrame_op IS
SIGNAL LinSynchro_int : std_logic;
SIGNAL octetRecu_int : std_logic_vector(7 downto 0);
SIGNAL nbDataField_INIT : integer;
COMPONENT D_FF
PORT(
H: IN std_logic;
D: IN std_logic;
nRst: IN std_logic;
Q: OUT std_logic
);
END COMPONENT;
COMPONENT shift_register
GENERIC (
WIDTH: integer
);
PORT(
H: IN std_logic;
H_EN: IN std_logic;
nRst : IN std_logic;
D: IN std_logic;
Q: OUT std_logic_vector
);
END COMPONENT;
BEGIN
LinSynchro <= LinSynchro_int;
octetRecu <= octetRecu_int;
-- Lin sync D-FF, with asynchronous reset
Lin_in_sync : D_FF
PORT MAP(
H => H,
D => Lin,
nRst => nCLR,
Q => LinSynchro_int
);
-- Lin serial->parallel shift reg
Lin_para : shift_register
GENERIC MAP(
WIDTH => 8
)
PORT MAP(
H => H,
H_EN => octetRecu_EN,
nRst => nCLR,
D => LinSynchro_int,
Q => octetRecu_int
);
-- Decoder
WITH octetRecu_int(5 downto 4) SELECT
nbDataField_INIT <=
1 when "00",
1 when "01",
3 when "10",
7 when "11",
0 when others;
-- nbDataField counter
END ARCHITECTURE arch;