152 lines
3.8 KiB
VHDL
152 lines
3.8 KiB
VHDL
--
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-- VHDL Architecture RecepteurLIN_lib.InterfaceMicroprocesseur.arch
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--
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-- Created:
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-- by - lenours-s.UNKNOWN (IREENA-SLN-B)
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-- at - 11:25:52 13/05/2014
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--
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-- using Mentor Graphics HDL Designer(TM) 2013.1 (Build 6)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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ENTITY InterfaceMicroprocesseur IS
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PORT(
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CnD : IN std_logic;
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OctetLu : IN std_logic_vector (7 DOWNTO 0);
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EtatLu : IN std_logic_vector (7 DOWNTO 0);
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H : IN std_logic;
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RnW : IN std_logic;
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nCS : IN std_logic;
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nRST : IN std_logic;
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DecNbOctet : OUT std_logic;
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SelAdr : OUT std_logic_vector (7 DOWNTO 0);
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M_Received : OUT std_logic;
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EtatLu_RST : OUT std_logic;
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OctetLu_RD : OUT std_logic;
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D07 : INOUT std_logic_vector (7 DOWNTO 0)
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);
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-- Declarations
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END InterfaceMicroprocesseur ;
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--
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ARCHITECTURE arch OF InterfaceMicroprocesseur IS
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--Architecture declarations
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TYPE DefEtat IS (Attente, LectureData, LectureEtat, EcritureFiltre);
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SIGNAL EtatCourant, EtatSuivant : DefEtat;
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SIGNAL nCS_Synchro, RnW_Synchro, CnD_Synchro : STD_LOGIC;
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SIGNAL D07_Synchro : STD_LOGIC_VECTOR(7 DOWNTO 0);
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BEGIN
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ClockedProc : PROCESS(H, nRST)
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BEGIN
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IF (nRST='0') THEN
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EtatCourant <= Attente;
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ELSIF (H'EVENT AND H='1') THEN
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EtatCourant <= EtatSuivant;
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END IF;
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END PROCESS ClockedProc;
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InputProc_Synchro : PROCESS(H, nRST)
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BEGIN
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IF (nRST='0') THEN
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nCS_Synchro <= '1';
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RnW_Synchro <= '1';
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CnD_Synchro <= '1';
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D07_Synchro <= (others => '0');
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ELSIF (H'EVENT AND H='1') THEN
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nCS_Synchro <= nCS;
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RnW_Synchro <= RnW;
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CnD_Synchro <= CnD;
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D07_Synchro <= D07;
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END IF;
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END PROCESS InputProc_Synchro;
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NextStateProc : PROCESS(nCS_Synchro, CnD_Synchro, RnW_Synchro, EtatCourant)
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BEGIN
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EtatSuivant <= EtatCourant;
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CASE EtatCourant IS
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WHEN Attente =>
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IF (nCS_Synchro='0' AND CnD_Synchro='0' AND RnW_Synchro='1') THEN
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EtatSuivant <= LectureData;
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ELSIF (nCS_Synchro='0' AND CnD_Synchro='1' AND RnW_Synchro='1') THEN
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EtatSuivant <= LectureEtat;
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ELSIF (nCS_Synchro='0' AND CnD_Synchro='0' AND RnW_Synchro='0') THEN
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EtatSuivant <= EcritureFiltre;
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ELSE
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EtatSuivant <= Attente;
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END IF;
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WHEN LectureData =>
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IF (nCS_Synchro='1') THEN
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EtatSuivant <= Attente;
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ELSE
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EtatSuivant <= LectureData;
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END IF;
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WHEN LectureEtat =>
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IF (nCS_Synchro='1') THEN
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EtatSuivant <= Attente;
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ELSE
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EtatSuivant <= LectureEtat;
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END IF;
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WHEN EcritureFiltre =>
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IF (nCS_Synchro='1') THEN
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EtatSuivant <= Attente;
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ELSE
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EtatSuivant <= EcritureFiltre;
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END IF;
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END CASE;
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END PROCESS NextStateProc;
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OutputProc_Comb : PROCESS(nCS_Synchro, CnD_Synchro, RnW_Synchro, EtatCourant, OctetLu, EtatLu)
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BEGIN
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D07 <= (others => 'Z');
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OctetLu_RD <= '0';
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EtatLu_RST <= '0';
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DecNbOctet <= '0';
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CASE EtatCourant IS
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WHEN Attente =>
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IF (nCS_Synchro='0' AND CnD_Synchro='0' AND RnW_Synchro='1') THEN
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OctetLu_RD <= '1';
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END IF;
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WHEN LectureData =>
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D07 <= OctetLu;
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IF (nCS_Synchro='1') THEN
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DecNbOctet <= '1';
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END IF;
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WHEN LectureEtat =>
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D07 <= EtatLu;
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IF (nCS_Synchro='1') THEN
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EtatLu_RST <= '1';
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END IF;
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WHEN EcritureFiltre =>
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END CASE;
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END PROCESS OutputProc_Comb;
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OutputProc_Synchro : PROCESS(H, nRST)
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BEGIN
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IF (nRST='0') THEN
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SelAdr <= (others => '0');
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ELSIF (H'EVENT AND H='1') THEN
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CASE EtatCourant IS
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WHEN EcritureFiltre =>
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IF (nCS_Synchro='1') THEN
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SelAdr <= D07_Synchro;
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END IF;
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WHEN OTHERS =>
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END CASE;
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END IF;
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END PROCESS OutputProc_Synchro;
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M_Received <= EtatLu(4);
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END ARCHITECTURE arch;
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