142 lines
2.6 KiB
VHDL
142 lines
2.6 KiB
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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-- USE ieee.std_logic_arith.all;
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USE ieee.numeric_std.all;
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ENTITY receptionTrame_op IS
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GENERIC(
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N: integer := 1200
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);
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PORT(
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H: IN std_logic;
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nCLR: IN std_logic;
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Lin: IN std_logic;
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octetRecu_EN : IN std_logic;
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n_SELECT: IN std_logic;
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n_LOAD: IN std_logic;
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n_EN: IN std_logic;
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nbBit_SELECT: IN std_logic;
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nbBit_LOAD: IN std_logic;
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nbBit_EN: IN std_logic;
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identifier_EN: IN std_logic;
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nbData_LOAD: IN std_logic;
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nbData_EN: IN std_logic;
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LinSynchro: OUT std_logic;
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n_0: OUT std_logic;
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nbBit_0: OUT std_logic;
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nbData_0: OUT std_logic;
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identifier: OUT std_logic_vector(5 downto 0);
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octetRecu: OUT std_logic_vector(7 downto 0)
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);
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END receptionTrame_op;
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ARCHITECTURE arch OF receptionTrame_op IS
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SIGNAL LinSynchro_int : std_logic;
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SIGNAL octetRecu_int : std_logic_vector(7 downto 0);
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SIGNAL nbDataField_INIT_int : integer := 0;
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SIGNAL nbDataField_INIT : unsigned(2 downto 0);
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COMPONENT D_FF
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PORT(
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H: IN std_logic;
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D: IN std_logic;
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nRst: IN std_logic;
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Q: OUT std_logic
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);
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END COMPONENT;
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COMPONENT shift_register
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GENERIC (
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WIDTH: integer
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);
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PORT(
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H: IN std_logic;
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H_EN: IN std_logic;
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nRst : IN std_logic;
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D: IN std_logic;
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Q: OUT std_logic_vector
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);
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END COMPONENT;
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COMPONENT counter
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GENERIC(
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WIDTH: integer;
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MAX_VAL: integer
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);
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PORT(
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H: IN std_logic;
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H_EN: IN std_logic;
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nRst: IN std_logic;
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INIT: IN unsigned(WIDTH-1 downto 0);
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LOAD: IN std_logic;
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upnDown: IN std_logic;
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val: OUT unsigned(WIDTH-1 downto 0);
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max: OUT std_logic
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);
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END COMPONENT;
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BEGIN
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LinSynchro <= LinSynchro_int;
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octetRecu <= octetRecu_int;
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-- Lin sync D-FF, with asynchronous reset
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Lin_in_sync : D_FF
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PORT MAP(
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H => H,
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D => Lin,
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nRst => nCLR,
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Q => LinSynchro_int
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);
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-- Lin serial->parallel shift reg
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Lin_para : shift_register
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GENERIC MAP(
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WIDTH => 8
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)
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PORT MAP(
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H => H,
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H_EN => octetRecu_EN,
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nRst => nCLR,
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D => LinSynchro_int,
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Q => octetRecu_int
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);
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-- Decoder
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WITH octetRecu_int(5 downto 4) SELECT
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nbDataField_INIT_int <=
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1 when "00",
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1 when "01",
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3 when "10",
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7 when "11",
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0 when others;
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nbDataField_INIT <= to_unsigned(nbDataField_INIT_int, 3);
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-- nbDataField counter
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nbDataField_cmp : counter
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GENERIC MAP(
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WIDTH => 3,
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MAX_VAL => 0
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)
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PORT MAP(
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H => H,
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H_EN => nbData_EN,
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nRst => nCLR,
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INIT => nbDataField_INIT,
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LOAD => nbData_LOAD,
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upnDown => '0',
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val => OPEN,
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max => nbData_0
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);
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END ARCHITECTURE arch; |