77 lines
1.4 KiB
VHDL
77 lines
1.4 KiB
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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ENTITY receptionTrame_tb IS
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GENERIC(
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CLOCK_PERIOD : time := 10 ns
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);
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end receptionTrame_tb;
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ARCHITECTURE arch OF receptionTrame_tb IS
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SIGNAL H : std_logic;
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COMPONENT receptionTrame_op
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GENERIC (
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N: integer
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);
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PORT (
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H: IN std_logic;
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nCLR: IN std_logic;
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Lin: IN std_logic;
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octetRecu_EN : IN std_logic;
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n_SELECT: IN std_logic;
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n_LOAD: IN std_logic;
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n_EN: IN std_logic;
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nbBit_SELECT: IN std_logic;
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nbBit_LOAD: IN std_logic;
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nbBit_EN: IN std_logic;
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identifier_EN: IN std_logic;
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nbData_LOAD: IN std_logic;
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nbData_EN: IN std_logic;
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LinSynchro: OUT std_logic;
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n_0: OUT std_logic;
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nbBit_0: OUT std_logic;
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nbData_0: OUT std_logic;
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identifier: OUT std_logic_vector(5 downto 0);
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octetRecu: OUT std_logic_vector(7 downto 0)
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);
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END COMPONENT;
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BEGIN
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CLK_gen : PROCESS
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BEGIN
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H <= '0';
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WAIT FOR CLOCK_PERIOD/2;
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H <= '1';
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WAIT FOR CLOCK_PERIOD/2;
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END PROCESS CLK_gen;
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U0 : receptionTrame_op
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GENERIC MAP(
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N => 1200
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)
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PORT MAP(
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H => H,
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nCLR => '1',
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Lin => '1',
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octetRecu_EN => '1',
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n_SELECT => '0',
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n_LOAD => '0',
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n_EN => '0',
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nbBit_SELECT => '0',
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nbBit_LOAD => '1',
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nbBit_EN => '1',
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identifier_EN => '0',
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nbData_LOAD => '1',
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nbData_EN => '1'
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);
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END ARCHITECTURE arch; |