47 lines
899 B
VHDL
47 lines
899 B
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use IEEE.NUMERIC_STD.all;
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ENTITY counter IS
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GENERIC(
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WIDTH: integer;
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MAX_VAL: integer
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);
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PORT(
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H: IN std_logic;
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H_EN: IN std_logic;
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nRst: IN std_logic;
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INIT: IN unsigned(WIDTH-1 downto 0);
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LOAD: IN std_logic;
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upnDown: IN std_logic;
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val: OUT unsigned(WIDTH-1 downto 0);
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max: OUT std_logic
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);
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END counter;
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ARCHITECTURE arch OF counter IS
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SIGNAL cmp: unsigned(WIDTH-1 downto 0);
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BEGIN
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val <= cmp;
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max <= '1' when cmp = MAX_VAL else '0';
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main : PROCESS(H, nRst)
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BEGIN
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if(nRst = '0') then
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cmp <= to_unsigned(0, WIDTH);
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elsif(rising_edge(H) and H_EN = '1') then
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if(LOAD = '1') then
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cmp <= INIT;
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elsif(cmp /= MAX_VAL) then
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if(upnDown = '1') then
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cmp <= cmp + 1;
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else
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cmp <= cmp - 1;
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end if;
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end if;
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end if;
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END PROCESS main;
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END ARCHITECTURE arch; |