leo/snake-vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

simulation

Browse Source
This commit is contained in:
leo 2022-01-19 12:41:21 +01:00
parent 61bf636a3f
commit 6c992bc197
2 changed files with 14 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
sources_snake/GeneSync.vhd
View File

@ -22,6 +22,7 @@ signal pulseX : std_logic;
signal pulseY: std_logic; signal pulseY: std_logic;
signal IMGX : std_logic; signal IMGX : std_logic;
signal IMGY : std_logic; signal IMGY : std_logic;
signal frameCount : integer := 0;
begin begin
Y<=Yaux(8 downto 0); Y<=Yaux(8 downto 0);
@ -42,7 +43,8 @@ begin
comptY<=comptY+1; comptY<=comptY+1;
else else
comptY<="0000000000"; comptY<="0000000000";
std.env.stop; --end the simulation frameCount <= frameCount + 1;
--std.env.stop; --end the simulation
end if; end if;
end if; end if;
end if; end if;

18
sources_snake/testBench.vhd
View File

@ -11,7 +11,6 @@ architecture Behavioral of testbench is
component VGA_top is component VGA_top is
Port ( H125MHz : in STD_LOGIC; Port ( H125MHz : in STD_LOGIC;
resetGeneral : in std_logic; resetGeneral : in std_logic;
resetPomme : in std_logic;
led : out std_logic_vector (3 downto 0); led : out std_logic_vector (3 downto 0);
vga_hs : out STD_LOGIC; vga_hs : out STD_LOGIC;
vga_vs : out STD_LOGIC; vga_vs : out STD_LOGIC;
@ -32,11 +31,11 @@ architecture Behavioral of testbench is
signal R : STD_LOGIC_VECTOR (4 downto 0); signal R : STD_LOGIC_VECTOR (4 downto 0);
signal G : STD_LOGIC_VECTOR (5 downto 0); signal G : STD_LOGIC_VECTOR (5 downto 0);
signal B : STD_LOGIC_VECTOR (4 downto 0); signal B : STD_LOGIC_VECTOR (4 downto 0);
signal bl,br,bu,bd : STD_LOGIC := '0';
begin begin
U0 : VGA_top U0 : VGA_top
port map(H125MHz => clk, port map(H125MHz => clk,
resetGeneral => '1', resetGeneral => '1',
resetPomme => '1',
led => open, led => open,
vga_hs => HS, vga_hs => HS,
vga_vs => VS, vga_vs => VS,
@ -44,10 +43,10 @@ begin
vga_g => G, vga_g => G,
vga_b => B, vga_b => B,
button_up => '0', button_up => bu,
button_down => '0', button_down => bd,
button_left => '0', button_left => bl,
button_right => '0' button_right => br
); );
clk <= not clk after clk_period/2; clk <= not clk after clk_period/2;
@ -55,6 +54,7 @@ begin
process (clk) process (clk)
file file_pointer: text open write_mode is "write.txt"; file file_pointer: text open write_mode is "write.txt";
variable line_el: line; variable line_el: line;
begin begin
if rising_edge(clk) then if rising_edge(clk) then
@ -77,7 +77,11 @@ begin
write(line_el, B & '0'); -- write the line. write(line_el, B & '0'); -- write the line.
writeline(file_pointer, line_el); -- write the contents into the file. writeline(file_pointer, line_el); -- write the contents into the file.
case << signal .U0.SYNC.frameCount : integer >> is
when 50 => br <= '1';
when others => br <= '0';
end case;
end if; end if;
end process; end process;
end Behavioral; end Behavioral;