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trouvé, c'etait la deserialisation qui etait pas dans le bon sens

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leo 2021-12-19 17:36:37 +01:00
parent d7170714c1
commit 94e7110845
4 changed files with 71 additions and 135 deletions
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107
sources_snake/Gene_Snake.vhd
View File

@ -63,96 +63,49 @@ signal running : std_logic;
begin begin
---- Process d'initialisation
--process(mat,snake,reset,current_index)
--variable current_dir : direction;
--begin
-- if(reset='0')
-- then
-- update <= '0';
-- current_index <= to_unsigned(0,11);
-- for x in 0 to 39 loop
-- for y in 0 to 29 loop
-- mat(x,y) <= to_unsigned(snake'length-1,11);
-- end loop;
-- end loop;
-- mat(0,0) <= to_unsigned(0,11);
-- mat(1,0) <= to_unsigned(1,11);
-- snake(0).X <= to_unsigned(8,10);
-- snake(0).Y <= to_unsigned(8,9);
-- snake(0).dir <= droite;
-- snake(0).isDefined <= '1';
-- snake(1).X <= to_unsigned(24,10);
-- snake(1).Y <= to_unsigned(8,9);
-- snake(1).dir <= droite;
-- snake(1).isDefined <= '1';
-- for i in 2 to snake'length-1 loop
-- snake(i).X <= to_unsigned(0,10);
-- snake(i).Y <= to_unsigned(0,9);
-- snake(i).dir <= gauche;
-- snake(i).isDefined <= '0';
-- end loop;
-- elsif(clk_rapide'event and clk_rapide = '1')
-- then
-- snake(to_integer(current_index)) <= updatedSnake;
-- current_index <= updatedIndex;
-- end if;
-- if (to_integer(current_index) = snake'length) then
-- update <= '0';
-- current_index <= to_unsigned(0,11);
-- end if;
-- if(clk_lente'event and clk_lente = '1')
-- then
-- update <= '1';
-- end if;
--end process;
-- Process de calcul d'affichage -- Process de calcul d'affichage
process(X,Y,clk,reset,running,dx,dy,updateOrder,currentSnake,snakeHere) process(X,Y,clk,reset,running,dx,dy,updateOrder,currentSnake,snakeHere)
begin begin
if(updateOrder'event and updateOrder = '1') then --if(updateOrder'event and updateOrder = '1') then
running <= '1'; -- running <= '1';
snakeHere <= '0'; -- snakeHere <= '0';
dx <= to_signed(-1,3); -- dx <= to_signed(-1,3);
dy <= to_signed(-1,3); -- dy <= to_signed(-1,3);
end if; --end if;
if(reset = '0') then --if(reset = '0') then
dx <= to_signed(-1,3); -- dx <= to_signed(-1,3);
dy <= to_signed(-1,3); -- dy <= to_signed(-1,3);
running <= '0'; -- running <= '0';
snakeHere <= '0'; -- snakeHere <= '0';
elsif(clk'event and clk = '1') then --elsif(clk'event and clk = '1') then
if(running = '1') then -- if(running = '1') then
dx <= dx + 1; -- dx <= dx + 1;
if(dx = 2) then
dx <= to_signed(-1,3);
dy <= dy + 1;
end if;
end if;
end if;
-- if(dx = 2) then
-- dx <= to_signed(-1,3);
-- dy <= dy + 1;
-- end if;
-- end if;
--end if;
if(clk'event and clk = '1') then
if(currentSnake.isDefined = '1') then if(currentSnake.isDefined = '1') then
--if(X>=currentSnake.X-8 and X<=currentSnake.X+8 and Y>=currentSnake.Y-8 and Y<=currentSnake.Y+8) then --if(X>=currentSnake.X-8 and X<=currentSnake.X+8 and Y>=currentSnake.Y-8 and Y<=currentSnake.Y+8) then
snakeHere <= '1'; snakeHere <= '1';
--end if; --end if;
else
snakeHere <= '0';
end if;
end if; end if;
if(dy = 2) then --if(dy = 2) then
dy <= to_signed(-1,3); -- dy <= to_signed(-1,3);
running <= '0'; -- running <= '0';
end if; --end if;
end process; end process;
matAddress <= resize(shift_right(to_unsigned(to_integer(Y)+to_integer(dy),9),4)*40+shift_right(to_unsigned(to_integer(X)+to_integer(dx),10),4),SNAKE_ADDRESS_SIZE); --on resize parce qu'il as décidé que le resultat faisait 18bits au lieu des 11 attendus --matAddress <= resize(shift_right(to_unsigned(to_integer(Y)+to_integer(dy),9),4)*40+shift_right(to_unsigned(to_integer(X)+to_integer(dx),10),4),SNAKE_ADDRESS_SIZE); --on resize parce qu'il as décidé que le resultat faisait 18bits au lieu des 11 attendus
matAddress <= resize(shift_right(Y,4)*40+shift_right(X,4),SNAKE_ADDRESS_SIZE);
currentAddress <= listRef; currentAddress <= listRef;

10
sources_snake/VGA_top.vhd
View File

@ -121,12 +121,12 @@ generic (length : integer;
dataSize : integer dataSize : integer
); );
Port ( address1 : in unsigned(addressSize-1 downto 0); Port ( address1 : in unsigned(addressSize-1 downto 0);
data1 : inout std_logic_vector(dataSize-1 downto 0); data1 : out std_logic_vector(dataSize-1 downto 0);
writeEnable1 : in STD_LOGIC; writeEnable1 : in STD_LOGIC;
clk1 : in STD_LOGIC; clk1 : in STD_LOGIC;
address2 : in unsigned(addressSize-1 downto 0); address2 : in unsigned(addressSize-1 downto 0);
data2 : inout std_logic_vector(dataSize-1 downto 0); data2 : in std_logic_vector(dataSize-1 downto 0);
writeEnable2 : in STD_LOGIC; writeEnable2 : in STD_LOGIC;
clk2 : in STD_LOGIC); clk2 : in STD_LOGIC);
end component snakeRam; end component snakeRam;
@ -247,7 +247,7 @@ U6 : snakeRAM --La RAM pour le snake
address1 => displayRAMAddress, address1 => displayRAMAddress,
data1 => displayRAMdata, data1 => displayRAMdata,
writeEnable1 => '0', writeEnable1 => '0',
clk1 => H125Mhz, clk1 => pxl_clk,
address2 => updateRAMAddress, address2 => updateRAMAddress,
data2 => updateRAMData, data2 => updateRAMData,
@ -265,7 +265,7 @@ U7 : snakeRAM --La RAM pour la matrice de correspondance
address1 => matdispRAMAddress, address1 => matdispRAMAddress,
data1 => matdispRAMdata, data1 => matdispRAMdata,
writeEnable1 => '0', writeEnable1 => '0',
clk1 => H125Mhz, clk1 => pxl_clk,
address2 => matupdRAMAddress, address2 => matupdRAMAddress,
data2 => std_logic_vector(matupdRAMData), data2 => std_logic_vector(matupdRAMData),
@ -273,5 +273,5 @@ U7 : snakeRAM --La RAM pour la matrice de correspondance
clk2 => H125MHz clk2 => H125MHz
); );
led(0) <= '1'; led <= std_logic_vector(displayRAMData(3 downto 0));
end Behavioral; end Behavioral;

14
sources_snake/types.vhd
View File

@ -30,15 +30,15 @@ package body types is
begin begin
--si on trouve une facon plus simple de deserialiser je suis preneur --si on trouve une facon plus simple de deserialiser je suis preneur
offset := 0; offset := 0;
sortie.X := unsigned(input(pos.X'length-1 downto 0)); sortie.isDefined := input(0);
offset := offset+pos.X'length; offset := offset+1;
sortie.Y := unsigned(input(offset+pos.Y'length-1 downto offset));
offset := offset+pos.Y'length;
sortie.dirX := signed(input(offset+pos.dirX'length-1 downto offset));
offset := offset+pos.dirX'length;
sortie.dirY := signed(input(offset+pos.dirY'length-1 downto offset)); sortie.dirY := signed(input(offset+pos.dirY'length-1 downto offset));
offset := offset+pos.dirY'length; offset := offset+pos.dirY'length;
sortie.isDefined := input(offset); sortie.dirX := signed(input(offset+pos.dirX'length-1 downto offset));
offset := offset+pos.dirX'length;
sortie.Y := unsigned(input(offset+pos.Y'length-1 downto offset));
offset := offset+pos.Y'length;
sortie.X := unsigned(input(offset+pos.X'length-1 downto offset));
return sortie; return sortie;
end to_pos; end to_pos;
end package body; end package body;

23
sources_snake/updateSnake.vhd
View File

@ -53,28 +53,24 @@ end updateSnake;
architecture Behavioral of updateSnake is architecture Behavioral of updateSnake is
signal index : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0); signal index : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
signal currentSnake : pos; signal currentSnake : pos;
signal clearRam : std_logic;
begin begin
process(clk,reset,clearRam,index) process(clk,reset,index)
begin begin
if(clk'event and clk = '1') then
if(reset = '0') then if(reset = '0') then
index <= to_unsigned(0,SNAKE_ADDRESS_SIZE); index <= to_unsigned(0,SNAKE_ADDRESS_SIZE);
clearRam <= '1';
writeEnable <= '1'; writeEnable <= '1';
matWriteEnable <= '1'; matWriteEnable <= '1';
elsif(clk'event and clk = '1') then else
if(clearRam = '1') then
index <= index + 1; index <= index + 1;
if(index = MAX_SNAKE-1) then if(index = MAX_SNAKE-1) then
index <= to_unsigned(0,SNAKE_ADDRESS_SIZE); index <= to_unsigned(0,SNAKE_ADDRESS_SIZE);
clearRam <= '0';
writeEnable <= '0'; writeEnable <= '0';
matWriteEnable <= '0'; matWriteEnable <= '0';
end if; end if;
end if; end if;
end if; end if;
if(clearRam = '1') then
if(index = 0) then if(index = 0) then
currentSnake.X <= to_unsigned(8,10); currentSnake.X <= to_unsigned(8,10);
currentSnake.Y <= to_unsigned(8,9); currentSnake.Y <= to_unsigned(8,9);
@ -103,19 +99,6 @@ begin
matAddress <= to_unsigned(10,SNAKE_ADDRESS_SIZE); matAddress <= to_unsigned(10,SNAKE_ADDRESS_SIZE);
matData <= to_unsigned(10,SNAKE_ADDRESS_SIZE); matData <= to_unsigned(10,SNAKE_ADDRESS_SIZE);
end if; end if;
else
index <= to_unsigned(0,SNAKE_ADDRESS_SIZE);
writeEnable <= '0';
matWriteEnable <= '0';
matAddress <= to_unsigned(0,SNAKE_ADDRESS_SIZE);
matData <= to_unsigned(0,SNAKE_ADDRESS_SIZE);
currentSnake.X <= to_unsigned(0,10);
currentSnake.Y <= to_unsigned(0,9);
currentSnake.dirX <= to_signed(0,2);
currentSnake.dirY <= to_signed(0,2);
currentSnake.isDefined <= '0';
end if;
end process; end process;
data <= to_stdlogicvector(currentSnake); data <= to_stdlogicvector(currentSnake);