79 lines
2.0 KiB
VHDL
79 lines
2.0 KiB
VHDL
----------------------------------------------------------------------------------
|
|
-- Company:
|
|
-- Engineer:
|
|
--
|
|
-- Create Date: 12/16/2021 09:57:33 PM
|
|
-- Design Name:
|
|
-- Module Name: snakeRam - Behavioral
|
|
-- Project Name:
|
|
-- Target Devices:
|
|
-- Tool Versions:
|
|
-- Description:
|
|
--
|
|
-- Dependencies:
|
|
--
|
|
-- Revision:
|
|
-- Revision 0.01 - File Created
|
|
-- Additional Comments:
|
|
--
|
|
----------------------------------------------------------------------------------
|
|
|
|
|
|
library IEEE;
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
|
|
|
-- Uncomment the following library declaration if using
|
|
-- arithmetic functions with Signed or Unsigned values
|
|
use IEEE.NUMERIC_STD.ALL;
|
|
|
|
library ourTypes;
|
|
use ourTypes.types.all;
|
|
|
|
-- Uncomment the following library declaration if instantiating
|
|
-- any Xilinx leaf cells in this code.
|
|
--library UNISIM;
|
|
--use UNISIM.VComponents.all;
|
|
|
|
entity snakeRam is
|
|
generic (
|
|
length : integer;
|
|
addressSize : integer;
|
|
dataSize : integer
|
|
);
|
|
Port ( addresses : in addresses;
|
|
clk1 : in std_logic;
|
|
output : out std_logic_vector_array(0 to 8)(dataSize-1 downto 0);
|
|
|
|
address2 : in unsigned(addressSize-1 downto 0);
|
|
dataIn2 : in std_logic_vector(dataSize-1 downto 0);
|
|
dataOut2 : out std_logic_vector(dataSize-1 downto 0);
|
|
writeEnable2 : in STD_LOGIC;
|
|
clk2 : in STD_LOGIC);
|
|
end snakeRam;
|
|
|
|
architecture Behavioral of snakeRam is
|
|
type listData is array(0 to length-1) of std_logic_vector(dataSize-1 downto 0);
|
|
signal mem : listData := (others => (others => '0'));
|
|
begin
|
|
|
|
process(clk1)
|
|
begin
|
|
if(clk1'event and clk1 = '1') then
|
|
for i in addresses'LOW to addresses'HIGH loop
|
|
output(i) <= mem(to_integer(addresses(i)));
|
|
end loop;
|
|
end if;
|
|
end process;
|
|
|
|
process(clk2)
|
|
begin
|
|
if(clk2'event and clk2 = '1') then
|
|
if(writeEnable2 = '1') then
|
|
mem(to_integer(address2)) <= dataIn2;
|
|
else
|
|
dataOut2 <= mem(to_integer(address2));
|
|
end if;
|
|
end if;
|
|
end process;
|
|
end Behavioral;
|