snake partiel
This commit is contained in:
Yann SALMON
parent
3d6a5eaa3e
commit
cb4c3f0951
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NumberHits:1
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Timestamp: Tue Nov 16 09:42:22 UTC 2021
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NumberHits:2
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Timestamp: Tue Jan 04 09:12:04 UTC 2022
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@ -2,70 +2,87 @@ version:1
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||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d706c656f757470757470726f647563746469616c6f675f67656e65726174655f6f75747075745f70726f64756374735f696d6d6564696174656c79:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:737065636966796c6962726172796469616c6f675f6c6962726172795f6e616d65:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f6469726563746f72696573:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f6f725f6372656174655f736f757263655f66696c65:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6372656174655f66696c65:36:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f646f63756d656e746174696f6e:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f686965726172636879:38:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726366696c6570726f7070616e656c735f74797065:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726366696c6574797065636f6d626f626f785f736f757263655f66696c655f74797065:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f646f63756d656e746174696f6e:36:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f686965726172636879:3130:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f7365745f6c696272617279:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7374616c6572756e6469616c6f675f6e6f:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f70726f6a65637473:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636173746174656d6f6e69746f725f63616e63656c:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7461736b62616e6e65725f636c6f7365:3136:00:00
|
||||
eof:1716158420
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636173746174656d6f6e69746f725f63616e63656c:37:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7461736b62616e6e65725f636c6f7365:3139:00:00
|
||||
eof:2086603918
|
||||
|
||||
@ -1,24 +1,28 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:36:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6175746f636f6e6e656374746172676574:3136:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636f726576696577:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:637573746f6d697a65636f7265:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:656469747061737465:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:3131:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6175746f636f6e6e656374746172676574:3138:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636f726576696577:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:637265617465626c6f636b64657369676e:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:637573746f6d697a65636f7265:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:39:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:656469747061737465:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:65646974756e646f:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6c61756e636870726f6772616d66706761:3436:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e68617264776172656d616e61676572:3638:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e726563656e74746172676574:3231:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:70726f6772616d646576696365:3436:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:666c6970746f766965777461736b72746c616e616c79736973:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6c61756e636870726f6772616d66706761:3531:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e68617264776172656d616e61676572:3734:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e726563656e74746172676574:3234:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:70726f6772616d646576696365:3530:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265637573746f6d697a65636f7265:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e62697467656e:3435:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e696d706c656d656e746174696f6e:3539:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e62697467656e:3534:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e696d706c656d656e746174696f6e:3638:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e736368656d61746963:37:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e73796e746865736973:3932:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e73796e746865736973:313134:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7361766566696c6570726f787968616e646c6572:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f7776696577:3235:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:736574736f75726365656e61626c6564:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f7776696577:3335:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b696d706c656d656e746174696f6e:38:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b72746c616e616c79736973:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b72746c616e616c79736973:37:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b73796e746865736973:32:00:00
|
||||
eof:2668022594
|
||||
eof:2810968177
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
version:1
|
||||
57656254616c6b5472616e736d697373696f6e417474656d70746564:43
|
||||
6d6f64655f636f756e7465727c4755494d6f6465:5
|
||||
57656254616c6b5472616e736d697373696f6e417474656d70746564:49
|
||||
6d6f64655f636f756e7465727c4755494d6f6465:6
|
||||
eof:
|
||||
|
||||
@ -33,7 +33,7 @@ version:1
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30313a333673:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313331302e3531324d42:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3934382e3432364d42:00:00
|
||||
eof:1833541424
|
||||
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a343673:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:3937362e3134354d42:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3631332e3539304d42:00:00
|
||||
eof:1302994828
|
||||
|
||||
@ -3,10 +3,10 @@
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pa" timeStamp="Tue Dec 7 12:45:32 2021">
|
||||
<application name="pa" timeStamp="Tue Jan 4 12:17:36 2022">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="477737b7f1b34f59aedda03674ab2041" type="ProjectID"/>
|
||||
<property name="ProjectIteration" value="103" type="ProjectIteration"/>
|
||||
<property name="ProjectIteration" value="116" type="ProjectIteration"/>
|
||||
</section>
|
||||
<section name="PlanAhead Usage" visible="true">
|
||||
<item name="Project Data">
|
||||
@ -17,104 +17,120 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
|
||||
</item>
|
||||
<item name="Java Command Handlers">
|
||||
<property name="AddSources" value="6" type="JavaHandler"/>
|
||||
<property name="AutoConnectTarget" value="16" type="JavaHandler"/>
|
||||
<property name="CoreView" value="3" type="JavaHandler"/>
|
||||
<property name="CustomizeCore" value="4" type="JavaHandler"/>
|
||||
<property name="EditDelete" value="4" type="JavaHandler"/>
|
||||
<property name="EditPaste" value="2" type="JavaHandler"/>
|
||||
<property name="AddSources" value="11" type="JavaHandler"/>
|
||||
<property name="AutoConnectTarget" value="18" type="JavaHandler"/>
|
||||
<property name="CoreView" value="4" type="JavaHandler"/>
|
||||
<property name="CreateBlockDesign" value="3" type="JavaHandler"/>
|
||||
<property name="CustomizeCore" value="5" type="JavaHandler"/>
|
||||
<property name="EditDelete" value="9" type="JavaHandler"/>
|
||||
<property name="EditPaste" value="3" type="JavaHandler"/>
|
||||
<property name="EditUndo" value="1" type="JavaHandler"/>
|
||||
<property name="LaunchProgramFpga" value="46" type="JavaHandler"/>
|
||||
<property name="NewProject" value="1" type="JavaHandler"/>
|
||||
<property name="OpenHardwareManager" value="68" type="JavaHandler"/>
|
||||
<property name="OpenRecentTarget" value="21" type="JavaHandler"/>
|
||||
<property name="ProgramDevice" value="46" type="JavaHandler"/>
|
||||
<property name="FlipToViewTaskRTLAnalysis" value="1" type="JavaHandler"/>
|
||||
<property name="LaunchProgramFpga" value="51" type="JavaHandler"/>
|
||||
<property name="NewProject" value="2" type="JavaHandler"/>
|
||||
<property name="OpenHardwareManager" value="74" type="JavaHandler"/>
|
||||
<property name="OpenProject" value="1" type="JavaHandler"/>
|
||||
<property name="OpenRecentTarget" value="24" type="JavaHandler"/>
|
||||
<property name="ProgramDevice" value="50" type="JavaHandler"/>
|
||||
<property name="RecustomizeCore" value="3" type="JavaHandler"/>
|
||||
<property name="RunBitgen" value="45" type="JavaHandler"/>
|
||||
<property name="RunImplementation" value="59" type="JavaHandler"/>
|
||||
<property name="RunBitgen" value="54" type="JavaHandler"/>
|
||||
<property name="RunImplementation" value="68" type="JavaHandler"/>
|
||||
<property name="RunSchematic" value="7" type="JavaHandler"/>
|
||||
<property name="RunSynthesis" value="92" type="JavaHandler"/>
|
||||
<property name="RunSynthesis" value="114" type="JavaHandler"/>
|
||||
<property name="SaveFileProxyHandler" value="3" type="JavaHandler"/>
|
||||
<property name="ShowView" value="25" type="JavaHandler"/>
|
||||
<property name="SetSourceEnabled" value="1" type="JavaHandler"/>
|
||||
<property name="ShowView" value="35" type="JavaHandler"/>
|
||||
<property name="ViewTaskImplementation" value="8" type="JavaHandler"/>
|
||||
<property name="ViewTaskRTLAnalysis" value="3" type="JavaHandler"/>
|
||||
<property name="ViewTaskRTLAnalysis" value="7" type="JavaHandler"/>
|
||||
<property name="ViewTaskSynthesis" value="2" type="JavaHandler"/>
|
||||
</item>
|
||||
<item name="Gui Handlers">
|
||||
<property name="AbstractCombinedPanel_ADD_ELEMENT" value="9" type="GuiHandlerData"/>
|
||||
<property name="AbstractCombinedPanel_REMOVE_SELECTED_ELEMENTS" value="2" type="GuiHandlerData"/>
|
||||
<property name="AbstractFileView_CLOSE" value="1" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_CANCEL" value="45" type="GuiHandlerData"/>
|
||||
<property name="AbstractFileView_RELOAD" value="2" type="GuiHandlerData"/>
|
||||
<property name="AddSrcWizard_SPECIFY_OR_CREATE_CONSTRAINT_FILES" value="1" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_CANCEL" value="59" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_CLOSE" value="1" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_NO" value="1" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_OK" value="397" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_YES" value="2" type="GuiHandlerData"/>
|
||||
<property name="ConstraintsChooserPanel_ADD_FILES" value="1" type="GuiHandlerData"/>
|
||||
<property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="18" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_NO" value="3" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_OK" value="474" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_YES" value="4" type="GuiHandlerData"/>
|
||||
<property name="CmdMsgDialog_OK" value="2" type="GuiHandlerData"/>
|
||||
<property name="ConfirmSaveTextEditsDialog_NO" value="1" type="GuiHandlerData"/>
|
||||
<property name="ConstraintsChooserPanel_ADD_FILES" value="2" type="GuiHandlerData"/>
|
||||
<property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="24" type="GuiHandlerData"/>
|
||||
<property name="CreateNewDiagramDialog_DESIGN_NAME" value="1" type="GuiHandlerData"/>
|
||||
<property name="CreateSrcFileDialog_FILE_NAME" value="5" type="GuiHandlerData"/>
|
||||
<property name="DefineModulesDialog_DEFINE_MODULES_AND_SPECIFY_IO_PORTS" value="95" type="GuiHandlerData"/>
|
||||
<property name="FPGAChooser_FPGA_TABLE" value="1" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="157" type="GuiHandlerData"/>
|
||||
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="207" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_CREATE_NEW_PROJECT" value="1" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="209" type="GuiHandlerData"/>
|
||||
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="261" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_CREATE_NEW_PROJECT" value="2" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_OPEN_PROJECT" value="1" type="GuiHandlerData"/>
|
||||
<property name="HCodeEditor_BLANK_OPERATIONS" value="17" type="GuiHandlerData"/>
|
||||
<property name="HCodeEditor_CLOSE" value="1" type="GuiHandlerData"/>
|
||||
<property name="HCodeEditor_CLOSE" value="3" type="GuiHandlerData"/>
|
||||
<property name="HCodeEditor_COMMANDS_TO_FOLD_TEXT" value="2" type="GuiHandlerData"/>
|
||||
<property name="HCodeEditor_DIFF_WITH" value="8" type="GuiHandlerData"/>
|
||||
<property name="HCodeEditor_SEARCH_TEXT_COMBO_BOX" value="15" type="GuiHandlerData"/>
|
||||
<property name="HCodeEditor_SEARCH_TEXT_COMBO_BOX" value="20" type="GuiHandlerData"/>
|
||||
<property name="HInputHandler_INDENT_SELECTION" value="1" type="GuiHandlerData"/>
|
||||
<property name="HInputHandler_TOGGLE_LINE_COMMENTS" value="37" type="GuiHandlerData"/>
|
||||
<property name="HInputHandler_TOGGLE_LINE_COMMENTS" value="40" type="GuiHandlerData"/>
|
||||
<property name="HInputHandler_UNINDENT_SELECTION" value="2" type="GuiHandlerData"/>
|
||||
<property name="HPopupTitle_CLOSE" value="1" type="GuiHandlerData"/>
|
||||
<property name="LogMonitor_MONITOR" value="3" type="GuiHandlerData"/>
|
||||
<property name="MsgTreePanel_MANAGE_SUPPRESSION" value="1" type="GuiHandlerData"/>
|
||||
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="79" type="GuiHandlerData"/>
|
||||
<property name="MsgView_CLEAR_MESSAGES_RESULTING_FROM_USER_EXECUTED" value="1" type="GuiHandlerData"/>
|
||||
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="137" type="GuiHandlerData"/>
|
||||
<property name="MsgView_CLEAR_MESSAGES_RESULTING_FROM_USER_EXECUTED" value="4" type="GuiHandlerData"/>
|
||||
<property name="MsgView_CRITICAL_WARNINGS" value="2" type="GuiHandlerData"/>
|
||||
<property name="MsgView_ERROR_MESSAGES" value="4" type="GuiHandlerData"/>
|
||||
<property name="MsgView_INFORMATION_MESSAGES" value="3" type="GuiHandlerData"/>
|
||||
<property name="MsgView_WARNING_MESSAGES" value="9" type="GuiHandlerData"/>
|
||||
<property name="NumJobsChooser_NUMBER_OF_JOBS" value="2" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_AUTO_CONNECT_TARGET" value="16" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_AUTO_UPDATE_HIER" value="11" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_GOTO_IMPLEMENTED_DESIGN" value="1" type="GuiHandlerData"/>
|
||||
<property name="MsgView_WARNING_MESSAGES" value="11" type="GuiHandlerData"/>
|
||||
<property name="NetlistTreeView_NETLIST_TREE" value="4" type="GuiHandlerData"/>
|
||||
<property name="NumJobsChooser_NUMBER_OF_JOBS" value="3" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_AUTO_CONNECT_TARGET" value="18" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_AUTO_UPDATE_HIER" value="15" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_GOTO_IMPLEMENTED_DESIGN" value="2" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_GOTO_NETLIST_DESIGN" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_LOG_WINDOW" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_MESSAGE_WINDOW" value="2" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_OPEN_HARDWARE_MANAGER" value="2" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_RECUSTOMIZE_CORE" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_RUN_BITGEN" value="42" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_RUN_BITGEN" value="45" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_RUN_IMPLEMENTATION" value="8" type="GuiHandlerData"/>
|
||||
<property name="PAViews_CODE" value="5" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_SRC_DISABLE" value="1" type="GuiHandlerData"/>
|
||||
<property name="PAViews_CODE" value="7" type="GuiHandlerData"/>
|
||||
<property name="PAViews_DEVICE" value="3" type="GuiHandlerData"/>
|
||||
<property name="PAViews_IP_CATALOG" value="1" type="GuiHandlerData"/>
|
||||
<property name="PAViews_PROJECT_SUMMARY" value="21" type="GuiHandlerData"/>
|
||||
<property name="PAViews_SCHEMATIC" value="9" type="GuiHandlerData"/>
|
||||
<property name="ProgramDebugTab_REFRESH_DEVICE" value="1" type="GuiHandlerData"/>
|
||||
<property name="ProgramFpgaDialog_PROGRAM" value="46" type="GuiHandlerData"/>
|
||||
<property name="ProgressDialog_BACKGROUND" value="4" type="GuiHandlerData"/>
|
||||
<property name="PAViews_IP_CATALOG" value="2" type="GuiHandlerData"/>
|
||||
<property name="PAViews_PROJECT_SUMMARY" value="26" type="GuiHandlerData"/>
|
||||
<property name="PAViews_SCHEMATIC" value="10" type="GuiHandlerData"/>
|
||||
<property name="ProgramDebugTab_PROGRAM_DEVICE" value="1" type="GuiHandlerData"/>
|
||||
<property name="ProgramDebugTab_REFRESH_DEVICE" value="2" type="GuiHandlerData"/>
|
||||
<property name="ProgramFpgaDialog_PROGRAM" value="51" type="GuiHandlerData"/>
|
||||
<property name="ProgressDialog_BACKGROUND" value="5" type="GuiHandlerData"/>
|
||||
<property name="ProgressDialog_CANCEL" value="5" type="GuiHandlerData"/>
|
||||
<property name="ProjectNameChooser_PROJECT_NAME" value="1" type="GuiHandlerData"/>
|
||||
<property name="ProjectTab_RELOAD" value="6" type="GuiHandlerData"/>
|
||||
<property name="RDICommands_DELETE" value="4" type="GuiHandlerData"/>
|
||||
<property name="ProjectTab_RELOAD" value="9" type="GuiHandlerData"/>
|
||||
<property name="RDICommands_COPY" value="1" type="GuiHandlerData"/>
|
||||
<property name="RDICommands_DELETE" value="8" type="GuiHandlerData"/>
|
||||
<property name="RemoveSourcesDialog_ALSO_DELETE" value="2" type="GuiHandlerData"/>
|
||||
<property name="RunGadget_SHOW_WARNING_AND_ERROR_MESSAGES_IN_MESSAGES" value="2" type="GuiHandlerData"/>
|
||||
<property name="SaveProjectUtils_DONT_SAVE" value="8" type="GuiHandlerData"/>
|
||||
<property name="SaveProjectUtils_SAVE" value="5" type="GuiHandlerData"/>
|
||||
<property name="SaveProjectUtils_SAVE" value="6" type="GuiHandlerData"/>
|
||||
<property name="SchematicView_PREVIOUS" value="10" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="3" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_ADD_HDL_AND_NETLIST_FILES_TO_YOUR_PROJECT" value="1" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="4" type="GuiHandlerData"/>
|
||||
<property name="SpecifyLibraryDialog_LIBRARY_NAME" value="1" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_ADD_DIRECTORIES" value="2" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_ADD_HDL_AND_NETLIST_FILES_TO_YOUR_PROJECT" value="3" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_ADD_OR_CREATE_SOURCE_FILE" value="1" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_CREATE_FILE" value="6" type="GuiHandlerData"/>
|
||||
<property name="SrcMenu_IP_DOCUMENTATION" value="5" type="GuiHandlerData"/>
|
||||
<property name="SrcMenu_IP_HIERARCHY" value="8" type="GuiHandlerData"/>
|
||||
<property name="SrcFilePropPanels_TYPE" value="4" type="GuiHandlerData"/>
|
||||
<property name="SrcFileTypeComboBox_SOURCE_FILE_TYPE" value="4" type="GuiHandlerData"/>
|
||||
<property name="SrcMenu_IP_DOCUMENTATION" value="6" type="GuiHandlerData"/>
|
||||
<property name="SrcMenu_IP_HIERARCHY" value="10" type="GuiHandlerData"/>
|
||||
<property name="SrcMenu_SET_LIBRARY" value="1" type="GuiHandlerData"/>
|
||||
<property name="StaleRunDialog_NO" value="1" type="GuiHandlerData"/>
|
||||
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="4" type="GuiHandlerData"/>
|
||||
<property name="SyntheticaStateMonitor_CANCEL" value="5" type="GuiHandlerData"/>
|
||||
<property name="TaskBanner_CLOSE" value="16" type="GuiHandlerData"/>
|
||||
</item>
|
||||
<item name="Other">
|
||||
<property name="GuiMode" value="14" type="GuiMode"/>
|
||||
<property name="BatchMode" value="0" type="BatchMode"/>
|
||||
<property name="TclMode" value="12" type="TclMode"/>
|
||||
<property name="SyntheticaStateMonitor_CANCEL" value="7" type="GuiHandlerData"/>
|
||||
<property name="TaskBanner_CLOSE" value="19" type="GuiHandlerData"/>
|
||||
</item>
|
||||
</section>
|
||||
</application>
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command=".planAhead." Owner="E209098F" Host="irb121-02-w" Pid="4856">
|
||||
<Process Command=".planAhead." Owner="e209098F" Host="irb121-12-w" Pid="13232">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command=".planAhead." Owner="E209098F" Host="irb121-02-w" Pid="4856">
|
||||
<Process Command=".planAhead." Owner="e209098F" Host="irb121-12-w" Pid="13232">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command=".planAhead." Owner="E209098F" Host="irb121-02-w" Pid="4856">
|
||||
<Process Command=".planAhead." Owner="e209098F" Host="irb121-12-w" Pid="13232">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command=".planAhead." Owner="E209098F" Host="irb121-02-w" Pid="4856">
|
||||
<Process Command=".planAhead." Owner="e209098F" Host="irb121-12-w" Pid="13232">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
|
||||
@ -1,10 +1,5 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado.bat" Owner="E209098F" Host="irb121-02-w" Pid="2036">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado.bat" Owner="E209098F" Host="irb121-02-w" Pid="14544">
|
||||
<Process Command="vivado.bat" Owner="e209098F" Host="irb121-12-w" Pid="13892">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command=".planAhead." Owner="E209098F" Host="irb121-02-w" Pid="5252">
|
||||
<Process Command=".planAhead." Owner="e209098F" Host="irb121-12-w" Pid="13232">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
|
||||
Binary file not shown.
@ -60,18 +60,104 @@ proc step_failed { step } {
|
||||
close $ch
|
||||
}
|
||||
|
||||
set_msg_config -id {Common 17-41} -limit 10000000
|
||||
set_msg_config -id {Synth 8-256} -limit 10000
|
||||
set_msg_config -id {Synth 8-638} -limit 10000
|
||||
|
||||
start_step init_design
|
||||
set ACTIVE_STEP init_design
|
||||
set rc [catch {
|
||||
create_msg_db init_design.pb
|
||||
set_param xicom.use_bs_reader 1
|
||||
create_project -in_memory -part xc7z010clg400-1
|
||||
set_property design_mode GateLvl [current_fileset]
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
set_property webtalk.parent_dir C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.cache/wt [current_project]
|
||||
set_property parent.project_path C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.xpr [current_project]
|
||||
set_property ip_output_repo C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
set_property XPM_LIBRARIES XPM_CDC [current_project]
|
||||
add_files -quiet C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/synth_1/VGA_top.dcp
|
||||
read_ip -quiet c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0.xci
|
||||
read_xdc C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/ZYBO_Master.xdc
|
||||
link_design -top VGA_top -part xc7z010clg400-1
|
||||
close_msg_db -file init_design.pb
|
||||
} RESULT]
|
||||
if {$rc} {
|
||||
step_failed init_design
|
||||
return -code error $RESULT
|
||||
} else {
|
||||
end_step init_design
|
||||
unset ACTIVE_STEP
|
||||
}
|
||||
|
||||
start_step opt_design
|
||||
set ACTIVE_STEP opt_design
|
||||
set rc [catch {
|
||||
create_msg_db opt_design.pb
|
||||
opt_design
|
||||
write_checkpoint -force VGA_top_opt.dcp
|
||||
create_report "impl_1_opt_report_drc_0" "report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx"
|
||||
close_msg_db -file opt_design.pb
|
||||
} RESULT]
|
||||
if {$rc} {
|
||||
step_failed opt_design
|
||||
return -code error $RESULT
|
||||
} else {
|
||||
end_step opt_design
|
||||
unset ACTIVE_STEP
|
||||
}
|
||||
|
||||
start_step place_design
|
||||
set ACTIVE_STEP place_design
|
||||
set rc [catch {
|
||||
create_msg_db place_design.pb
|
||||
if { [llength [get_debug_cores -quiet] ] > 0 } {
|
||||
implement_debug_core
|
||||
}
|
||||
place_design
|
||||
write_checkpoint -force VGA_top_placed.dcp
|
||||
create_report "impl_1_place_report_io_0" "report_io -file VGA_top_io_placed.rpt"
|
||||
create_report "impl_1_place_report_utilization_0" "report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb"
|
||||
create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file VGA_top_control_sets_placed.rpt"
|
||||
close_msg_db -file place_design.pb
|
||||
} RESULT]
|
||||
if {$rc} {
|
||||
step_failed place_design
|
||||
return -code error $RESULT
|
||||
} else {
|
||||
end_step place_design
|
||||
unset ACTIVE_STEP
|
||||
}
|
||||
|
||||
start_step route_design
|
||||
set ACTIVE_STEP route_design
|
||||
set rc [catch {
|
||||
create_msg_db route_design.pb
|
||||
route_design
|
||||
write_checkpoint -force VGA_top_routed.dcp
|
||||
create_report "impl_1_route_report_drc_0" "report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx"
|
||||
create_report "impl_1_route_report_methodology_0" "report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx"
|
||||
create_report "impl_1_route_report_power_0" "report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx"
|
||||
create_report "impl_1_route_report_route_status_0" "report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb"
|
||||
create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation "
|
||||
create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt"
|
||||
create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file VGA_top_clock_utilization_routed.rpt"
|
||||
create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx"
|
||||
close_msg_db -file route_design.pb
|
||||
} RESULT]
|
||||
if {$rc} {
|
||||
write_checkpoint -force VGA_top_routed_error.dcp
|
||||
step_failed route_design
|
||||
return -code error $RESULT
|
||||
} else {
|
||||
end_step route_design
|
||||
unset ACTIVE_STEP
|
||||
}
|
||||
|
||||
start_step write_bitstream
|
||||
set ACTIVE_STEP write_bitstream
|
||||
set rc [catch {
|
||||
create_msg_db write_bitstream.pb
|
||||
set_param synth.incrementalSynthesisCache C:/Users/E209098F/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-12508-irb121-02-w/incrSyn
|
||||
set_param xicom.use_bs_reader 1
|
||||
open_checkpoint VGA_top_routed.dcp
|
||||
set_property webtalk.parent_dir C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.cache/wt [current_project]
|
||||
set_property XPM_LIBRARIES XPM_CDC [current_project]
|
||||
catch { write_mem_info -force VGA_top.mmi }
|
||||
write_bitstream -force VGA_top.bit
|
||||
|
||||
@ -2,40 +2,43 @@
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Tue Dec 7 12:42:58 2021
|
||||
# Process ID: 4856
|
||||
# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1
|
||||
# Start of session at: Tue Jan 4 12:18:37 2022
|
||||
# Process ID: 13232
|
||||
# Current directory: C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1
|
||||
# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace
|
||||
# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi
|
||||
# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou
|
||||
# Log file: C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1/VGA_top.vdi
|
||||
# Journal file: C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source VGA_top.tcl -notrace
|
||||
Command: link_design -top VGA_top -part xc7z010clg400-1
|
||||
Design is defaulting to srcset: sources_1
|
||||
Design is defaulting to constrset: constrs_1
|
||||
INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.dcp' for cell 'U0'
|
||||
INFO: [Netlist 29-17] Analyzing 35 Unisim elements for replacement
|
||||
INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0.dcp' for cell 'U0'
|
||||
INFO: [Netlist 29-17] Analyzing 314 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-479] Netlist was created with Vivado 2018.3
|
||||
INFO: [Device 21-403] Loading part xc7z010clg400-1
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
|
||||
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
|
||||
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
|
||||
INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
|
||||
get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1248.586 ; gain = 558.375
|
||||
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
|
||||
Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
|
||||
Finished Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
|
||||
WARNING: [Opt 31-35] Removing redundant IBUF, U0/inst/clkin1_ibufg, from the path connected to top-level port: H125MHz
|
||||
Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
|
||||
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'U0/clk_in1' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
|
||||
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0_board.xdc] for cell 'U0/inst'
|
||||
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0_board.xdc] for cell 'U0/inst'
|
||||
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0.xdc] for cell 'U0/inst'
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0.xdc:57]
|
||||
INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0.xdc:57]
|
||||
get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1251.785 ; gain = 552.953
|
||||
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0.xdc] for cell 'U0/inst'
|
||||
Parsing XDC File [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/ZYBO_Master.xdc]
|
||||
Finished Parsing XDC File [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/ZYBO_Master.xdc]
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1248.586 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1251.785 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
10 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
link_design completed successfully
|
||||
link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:16 . Memory (MB): peak = 1248.586 ; gain = 885.598
|
||||
link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:25 . Memory (MB): peak = 1251.785 ; gain = 888.395
|
||||
Command: opt_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
@ -46,57 +49,58 @@ INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Project 1-461] DRC finished with 0 Errors
|
||||
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.499 . Memory (MB): peak = 1248.586 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.501 . Memory (MB): peak = 1251.785 ; gain = 0.000
|
||||
|
||||
Starting Cache Timing Information Task
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [Timing 38-2] Deriving generated clocks
|
||||
Ending Cache Timing Information Task | Checksum: 20ae1d4cd
|
||||
Ending Cache Timing Information Task | Checksum: 19f3e8d5f
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1265.152 ; gain = 16.566
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.092 . Memory (MB): peak = 1265.977 ; gain = 14.191
|
||||
|
||||
Starting Logic Optimization Task
|
||||
|
||||
Phase 1 Retarget
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Opt 31-49] Retargeted 0 cell(s).
|
||||
Phase 1 Retarget | Checksum: ddde5939
|
||||
Phase 1 Retarget | Checksum: c8a6b5ae
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Retarget created 4 cells and removed 4 cells
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.096 . Memory (MB): peak = 1346.285 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
|
||||
INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
||||
|
||||
Phase 2 Constant propagation
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Phase 2 Constant propagation | Checksum: ddde5939
|
||||
Phase 2 Constant propagation | Checksum: 1409f9166
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.123 . Memory (MB): peak = 1346.285 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
|
||||
|
||||
Phase 3 Sweep
|
||||
Phase 3 Sweep | Checksum: fec5e707
|
||||
Phase 3 Sweep | Checksum: 1b7440179
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.178 . Memory (MB): peak = 1346.285 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
|
||||
INFO: [Opt 31-1021] In phase Sweep, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
||||
|
||||
Phase 4 BUFG optimization
|
||||
INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG
|
||||
INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets
|
||||
Phase 4 BUFG optimization | Checksum: 137e6b9d1
|
||||
INFO: [Opt 31-194] Inserted BUFG H125MHz_IBUF_BUFG_inst to drive 182 load(s) on clock net H125MHz_IBUF_BUFG
|
||||
INFO: [Opt 31-193] Inserted 2 BUFG(s) on clock nets
|
||||
Phase 4 BUFG optimization | Checksum: cecab300
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.259 . Memory (MB): peak = 1346.285 ; gain = 0.000
|
||||
INFO: [Opt 31-662] Phase BUFG optimization created 1 cells of which 1 are BUFGs and removed 0 cells.
|
||||
|
||||
Phase 5 Shift Register Optimization
|
||||
Phase 5 Shift Register Optimization | Checksum: 12c29fba6
|
||||
Phase 5 Shift Register Optimization | Checksum: 193828ea0
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.412 . Memory (MB): peak = 1346.285 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
|
||||
|
||||
Phase 6 Post Processing Netlist
|
||||
Phase 6 Post Processing Netlist | Checksum: 10c49128f
|
||||
Phase 6 Post Processing Netlist | Checksum: 16ceef5f4
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.421 . Memory (MB): peak = 1346.285 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
|
||||
Opt_design Change Summary
|
||||
=========================
|
||||
@ -105,10 +109,10 @@ Opt_design Change Summary
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Retarget | 4 | 4 | 1 |
|
||||
| Retarget | 0 | 0 | 1 |
|
||||
| Constant propagation | 0 | 0 | 0 |
|
||||
| Sweep | 0 | 0 | 0 |
|
||||
| BUFG optimization | 0 | 0 | 0 |
|
||||
| Sweep | 0 | 0 | 1 |
|
||||
| BUFG optimization | 1 | 0 | 0 |
|
||||
| Shift Register Optimization | 0 | 0 | 0 |
|
||||
| Post Processing Netlist | 0 | 0 | 0 |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
@ -117,44 +121,70 @@ Opt_design Change Summary
|
||||
|
||||
Starting Connectivity Check Task
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Ending Logic Optimization Task | Checksum: e54fefee
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1346.285 ; gain = 0.000
|
||||
Ending Logic Optimization Task | Checksum: 20356351c
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.057 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.429 . Memory (MB): peak = 1346.285 ; gain = 0.000
|
||||
|
||||
Starting Power Optimization Task
|
||||
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
|
||||
Ending Power Optimization Task | Checksum: e54fefee
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-4.133 | TNS=-46.099 |
|
||||
Running Vector-less Activity Propagation...
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Finished Running Vector-less Activity Propagation
|
||||
INFO: [Pwropt 34-9] Applying IDT optimizations ...
|
||||
INFO: [Pwropt 34-10] Applying ODC optimizations ...
|
||||
|
||||
|
||||
Starting PowerOpt Patch Enables Task
|
||||
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 27 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
|
||||
INFO: [Pwropt 34-201] Structural ODC has moved 16 WE to EN ports
|
||||
Number of BRAM Ports augmented: 0 newly gated: 25 Total Ports: 54
|
||||
Number of Flops added for Enable Generation: 2
|
||||
|
||||
Ending PowerOpt Patch Enables Task | Checksum: 215f1437d
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.085 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
Ending Power Optimization Task | Checksum: 215f1437d
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1500.016 ; gain = 153.730
|
||||
|
||||
Starting Final Cleanup Task
|
||||
Ending Final Cleanup Task | Checksum: e54fefee
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Starting Logic Optimization Task
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG
|
||||
INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets
|
||||
Ending Logic Optimization Task | Checksum: 2182f781c
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.228 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
Ending Final Cleanup Task | Checksum: 2182f781c
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.967 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Starting Netlist Obfuscation Task
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Ending Netlist Obfuscation Task | Checksum: e54fefee
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
Ending Netlist Obfuscation Task | Checksum: 2182f781c
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
40 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
opt_design completed successfully
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
|
||||
Command: report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt.
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt.
|
||||
report_drc completed successfully
|
||||
Command: place_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
@ -173,48 +203,56 @@ INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of
|
||||
Phase 1 Placer Initialization
|
||||
|
||||
Phase 1.1 Placer Initialization Netlist Sorting
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 4ed236ad
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 131936915
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1a1c16c9c
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: d8624408
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.262 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.459 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Phase 1.3 Build Placer Netlist Model
|
||||
Phase 1.3 Build Placer Netlist Model | Checksum: 2939760d0
|
||||
Phase 1.3 Build Placer Netlist Model | Checksum: 1315496dd
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.351 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.837 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Phase 1.4 Constrain Clocks/Macros
|
||||
Phase 1.4 Constrain Clocks/Macros | Checksum: 2939760d0
|
||||
Phase 1.4 Constrain Clocks/Macros | Checksum: 1315496dd
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.353 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Phase 1 Placer Initialization | Checksum: 2939760d0
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.840 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
Phase 1 Placer Initialization | Checksum: 1315496dd
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.353 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.843 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Phase 2 Global Placement
|
||||
|
||||
Phase 2.1 Floorplanning
|
||||
Phase 2.1 Floorplanning | Checksum: 28231f14d
|
||||
Phase 2.1 Floorplanning | Checksum: 1a8bfe1e0
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.397 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.991 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Phase 2.2 Physical Synthesis In Placer
|
||||
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
|
||||
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
|
||||
INFO: [Physopt 32-117] Net SNAKE/listRefs[8][0] could not be optimized because driver SNAKE/mem_reg_3_i_4 could not be replicated
|
||||
INFO: [Physopt 32-117] Net SNAKE/listRefs[6][2] could not be optimized because driver SNAKE/mem_reg_1_i_4 could not be replicated
|
||||
INFO: [Physopt 32-68] No nets found for critical-cell optimization.
|
||||
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
|
||||
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
INFO: [Physopt 32-949] No candidate nets found for HD net replication
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Summary of Physical Synthesis Optimizations
|
||||
============================================
|
||||
@ -224,60 +262,71 @@ Summary of Physical Synthesis Optimizations
|
||||
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| Critical Cell | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 |
|
||||
| Total | 0 | 0 | 0 | 0 | 6 | 00:00:00 |
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Phase 2.2 Physical Synthesis In Placer | Checksum: 22348ffd6
|
||||
Phase 2.2 Physical Synthesis In Placer | Checksum: aaf1c87e
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Phase 2 Global Placement | Checksum: 2038a7242
|
||||
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
Phase 2 Global Placement | Checksum: 17a0bd3eb
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Phase 3 Detail Placement
|
||||
|
||||
Phase 3.1 Commit Multi Column Macros
|
||||
Phase 3.1 Commit Multi Column Macros | Checksum: 2038a7242
|
||||
Phase 3.1 Commit Multi Column Macros | Checksum: 17a0bd3eb
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 2c58c3354
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 18c86a722
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Phase 3.3 Area Swap Optimization
|
||||
Phase 3.3 Area Swap Optimization | Checksum: 279aeb7b4
|
||||
Phase 3.3 Area Swap Optimization | Checksum: 19f5ea993
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Phase 3.4 Pipeline Register Optimization
|
||||
Phase 3.4 Pipeline Register Optimization | Checksum: 279aeb7b4
|
||||
Phase 3.4 Pipeline Register Optimization | Checksum: 1bfb8a901
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Phase 3.5 Small Shape Detail Placement
|
||||
Phase 3.5 Small Shape Detail Placement | Checksum: 1e0aaeea1
|
||||
Phase 3.5 Fast Optimization
|
||||
Phase 3.5 Fast Optimization | Checksum: 108c906c7
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Phase 3.6 Re-assign LUT pins
|
||||
Phase 3.6 Re-assign LUT pins | Checksum: 2d338840d
|
||||
Phase 3.6 Small Shape Detail Placement
|
||||
Phase 3.6 Small Shape Detail Placement | Checksum: 1f5ba145a
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Phase 3.7 Pipeline Register Optimization
|
||||
Phase 3.7 Pipeline Register Optimization | Checksum: 2d338840d
|
||||
Phase 3.7 Re-assign LUT pins
|
||||
Phase 3.7 Re-assign LUT pins | Checksum: 1ca5326f1
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Phase 3 Detail Placement | Checksum: 2d338840d
|
||||
Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Phase 3.8 Pipeline Register Optimization
|
||||
Phase 3.8 Pipeline Register Optimization | Checksum: 1aa2d2687
|
||||
|
||||
Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Phase 3.9 Fast Optimization
|
||||
Phase 3.9 Fast Optimization | Checksum: a4f5789a
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
Phase 3 Detail Placement | Checksum: a4f5789a
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Phase 4 Post Placement Optimization and Clean-Up
|
||||
|
||||
@ -285,59 +334,60 @@ Phase 4.1 Post Commit Optimization
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
|
||||
Phase 4.1.1 Post Placement Optimization
|
||||
Post Placement Optimization Initialization | Checksum: 15c68dcd4
|
||||
Post Placement Optimization Initialization | Checksum: 100368e26
|
||||
|
||||
Phase 4.1.1.1 BUFG Insertion
|
||||
INFO: [Place 46-46] BUFG insertion identified 0 candidate nets, 0 success, 0 bufg driver replicated, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason
|
||||
Phase 4.1.1.1 BUFG Insertion | Checksum: 15c68dcd4
|
||||
Phase 4.1.1.1 BUFG Insertion | Checksum: 100368e26
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
INFO: [Place 30-746] Post Placement Timing Summary WNS=35.245. For the most accurate timing information please run report_timing.
|
||||
Phase 4.1.1 Post Placement Optimization | Checksum: 142e419cd
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
INFO: [Place 30-746] Post Placement Timing Summary WNS=-3.374. For the most accurate timing information please run report_timing.
|
||||
Phase 4.1.1 Post Placement Optimization | Checksum: be8bba9e
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Phase 4.1 Post Commit Optimization | Checksum: 142e419cd
|
||||
Time (s): cpu = 00:00:18 ; elapsed = 00:00:16 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
Phase 4.1 Post Commit Optimization | Checksum: be8bba9e
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:18 ; elapsed = 00:00:17 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Phase 4.2 Post Placement Cleanup
|
||||
Phase 4.2 Post Placement Cleanup | Checksum: 142e419cd
|
||||
Phase 4.2 Post Placement Cleanup | Checksum: be8bba9e
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:18 ; elapsed = 00:00:17 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Phase 4.3 Placer Reporting
|
||||
Phase 4.3 Placer Reporting | Checksum: 142e419cd
|
||||
Phase 4.3 Placer Reporting | Checksum: be8bba9e
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:18 ; elapsed = 00:00:17 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Phase 4.4 Final Placement Cleanup
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Phase 4.4 Final Placement Cleanup | Checksum: 20695260e
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
Phase 4.4 Final Placement Cleanup | Checksum: 540ff3bc
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 20695260e
|
||||
Time (s): cpu = 00:00:18 ; elapsed = 00:00:17 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 540ff3bc
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Ending Placer Task | Checksum: 1f2b3c1b8
|
||||
Time (s): cpu = 00:00:18 ; elapsed = 00:00:17 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
Ending Placer Task | Checksum: 531de2ac
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:18 ; elapsed = 00:00:17 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
57 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
75 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
place_design completed successfully
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:17 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.050 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.200 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_io -file VGA_top_io_placed.rpt
|
||||
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb
|
||||
INFO: [runtcl-4] Executing : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt
|
||||
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
Command: route_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
@ -349,98 +399,150 @@ INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more in
|
||||
|
||||
Starting Routing Task
|
||||
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
|
||||
Checksum: PlaceDB: f9e7c0c6 ConstDB: 0 ShapeSum: f8cc00f2 RouteDB: 0
|
||||
Checksum: PlaceDB: 3ad47cdf ConstDB: 0 ShapeSum: 184965cd RouteDB: 0
|
||||
|
||||
Phase 1 Build RT Design
|
||||
Phase 1 Build RT Design | Checksum: 9a64d846
|
||||
Phase 1 Build RT Design | Checksum: 13e412dc8
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1417.348 ; gain = 66.250
|
||||
Post Restoration Checksum: NetGraph: 7c5b36de NumContArr: 1e09a168 Constraints: 0 Timing: 0
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
Post Restoration Checksum: NetGraph: 58741a68 NumContArr: e5cd1360 Constraints: 0 Timing: 0
|
||||
|
||||
Phase 2 Router Initialization
|
||||
|
||||
Phase 2.1 Create Timer
|
||||
Phase 2.1 Create Timer | Checksum: 9a64d846
|
||||
Phase 2.1 Create Timer | Checksum: 13e412dc8
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1449.676 ; gain = 98.578
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Phase 2.2 Fix Topology Constraints
|
||||
Phase 2.2 Fix Topology Constraints | Checksum: 9a64d846
|
||||
Phase 2.2 Fix Topology Constraints | Checksum: 13e412dc8
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1455.699 ; gain = 104.602
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Phase 2.3 Pre Route Cleanup
|
||||
Phase 2.3 Pre Route Cleanup | Checksum: 9a64d846
|
||||
Phase 2.3 Pre Route Cleanup | Checksum: 13e412dc8
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1455.699 ; gain = 104.602
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
Number of Nodes with overlaps = 0
|
||||
|
||||
Phase 2.4 Update Timing
|
||||
Phase 2.4 Update Timing | Checksum: 82bae049
|
||||
Phase 2.4 Update Timing | Checksum: 1195a0f5b
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.391 | TNS=0.000 | WHS=-0.239 | THS=-2.915 |
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-3.513 | TNS=-50.092| WHS=-1.636 | THS=-51.724|
|
||||
|
||||
Phase 2 Router Initialization | Checksum: cf693307
|
||||
Phase 2 Router Initialization | Checksum: 12ae7c807
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Phase 3 Initial Routing
|
||||
Phase 3 Initial Routing | Checksum: 16fee48da
|
||||
Phase 3 Initial Routing | Checksum: 1b62d99da
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
||||
Time (s): cpu = 00:00:24 ; elapsed = 00:00:17 . Memory (MB): peak = 1546.250 ; gain = 46.234
|
||||
|
||||
Phase 4 Rip-up And Reroute
|
||||
|
||||
Phase 4.1 Global Iteration 0
|
||||
Number of Nodes with overlaps = 36
|
||||
Number of Nodes with overlaps = 954
|
||||
Number of Nodes with overlaps = 235
|
||||
Number of Nodes with overlaps = 66
|
||||
Number of Nodes with overlaps = 42
|
||||
Number of Nodes with overlaps = 19
|
||||
Number of Nodes with overlaps = 16
|
||||
Number of Nodes with overlaps = 15
|
||||
Number of Nodes with overlaps = 7
|
||||
Number of Nodes with overlaps = 1
|
||||
Number of Nodes with overlaps = 0
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=33.088 | TNS=0.000 | WHS=N/A | THS=N/A |
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-5.639 | TNS=-90.744| WHS=N/A | THS=N/A |
|
||||
|
||||
Phase 4.1 Global Iteration 0 | Checksum: 1c93f85f6
|
||||
Phase 4.1 Global Iteration 0 | Checksum: 1a754acba
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
||||
Phase 4 Rip-up And Reroute | Checksum: 1c93f85f6
|
||||
Time (s): cpu = 00:01:24 ; elapsed = 00:01:06 . Memory (MB): peak = 1596.598 ; gain = 96.582
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
||||
Phase 4.2 Global Iteration 1
|
||||
Number of Nodes with overlaps = 146
|
||||
Number of Nodes with overlaps = 24
|
||||
Number of Nodes with overlaps = 9
|
||||
Number of Nodes with overlaps = 8
|
||||
Number of Nodes with overlaps = 8
|
||||
Number of Nodes with overlaps = 5
|
||||
Number of Nodes with overlaps = 7
|
||||
Number of Nodes with overlaps = 5
|
||||
Number of Nodes with overlaps = 5
|
||||
Number of Nodes with overlaps = 2
|
||||
Number of Nodes with overlaps = 2
|
||||
Number of Nodes with overlaps = 1
|
||||
Number of Nodes with overlaps = 7
|
||||
Number of Nodes with overlaps = 1
|
||||
Number of Nodes with overlaps = 6
|
||||
Number of Nodes with overlaps = 0
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-5.630 | TNS=-88.178| WHS=N/A | THS=N/A |
|
||||
|
||||
Phase 4.2 Global Iteration 1 | Checksum: 13f25b21c
|
||||
|
||||
Time (s): cpu = 00:02:20 ; elapsed = 00:01:46 . Memory (MB): peak = 1630.195 ; gain = 130.180
|
||||
Phase 4 Rip-up And Reroute | Checksum: 13f25b21c
|
||||
|
||||
Time (s): cpu = 00:02:20 ; elapsed = 00:01:46 . Memory (MB): peak = 1630.195 ; gain = 130.180
|
||||
|
||||
Phase 5 Delay and Skew Optimization
|
||||
|
||||
Phase 5.1 Delay CleanUp
|
||||
Phase 5.1 Delay CleanUp | Checksum: 1c93f85f6
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
||||
Phase 5.1.1 Update Timing
|
||||
Phase 5.1.1 Update Timing | Checksum: 21c9bd585
|
||||
|
||||
Time (s): cpu = 00:02:20 ; elapsed = 00:01:46 . Memory (MB): peak = 1630.195 ; gain = 130.180
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-5.617 | TNS=-86.848| WHS=N/A | THS=N/A |
|
||||
|
||||
Number of Nodes with overlaps = 0
|
||||
Phase 5.1 Delay CleanUp | Checksum: e7e5e811
|
||||
|
||||
Time (s): cpu = 00:02:20 ; elapsed = 00:01:46 . Memory (MB): peak = 1630.195 ; gain = 130.180
|
||||
|
||||
Phase 5.2 Clock Skew Optimization
|
||||
Phase 5.2 Clock Skew Optimization | Checksum: 1c93f85f6
|
||||
Phase 5.2 Clock Skew Optimization | Checksum: e7e5e811
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
||||
Phase 5 Delay and Skew Optimization | Checksum: 1c93f85f6
|
||||
Time (s): cpu = 00:02:20 ; elapsed = 00:01:46 . Memory (MB): peak = 1630.195 ; gain = 130.180
|
||||
Phase 5 Delay and Skew Optimization | Checksum: e7e5e811
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
||||
Time (s): cpu = 00:02:20 ; elapsed = 00:01:46 . Memory (MB): peak = 1630.195 ; gain = 130.180
|
||||
|
||||
Phase 6 Post Hold Fix
|
||||
|
||||
Phase 6.1 Hold Fix Iter
|
||||
|
||||
Phase 6.1.1 Update Timing
|
||||
Phase 6.1.1 Update Timing | Checksum: 144941f51
|
||||
Phase 6.1.1 Update Timing | Checksum: ef9abc12
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=33.241 | TNS=0.000 | WHS=0.083 | THS=0.000 |
|
||||
Time (s): cpu = 00:02:21 ; elapsed = 00:01:47 . Memory (MB): peak = 1630.195 ; gain = 130.180
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-5.617 | TNS=-86.439| WHS=-0.443 | THS=-0.849 |
|
||||
|
||||
Phase 6.1 Hold Fix Iter | Checksum: 144941f51
|
||||
Phase 6.1 Hold Fix Iter | Checksum: 151f6c881
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
||||
Phase 6 Post Hold Fix | Checksum: 144941f51
|
||||
Time (s): cpu = 00:02:22 ; elapsed = 00:01:48 . Memory (MB): peak = 1630.195 ; gain = 130.180
|
||||
WARNING: [Route 35-468] The router encountered 388 pins that are both setup-critical and hold-critical and tried to fix hold violations at the expense of setup slack. Such pins are:
|
||||
RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_302/I0
|
||||
SYNC/ROMAddress_reg[3]_i_146/DI[3]
|
||||
SYNC/ROMAddress_reg[9]_i_237/DI[3]
|
||||
SYNC/ROMAddress[9]_i_588/I0
|
||||
SYNC/ROMAddress[9]_i_595/I0
|
||||
RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_589/I1
|
||||
RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_624/I1
|
||||
SYNC/ROMAddress_reg[9]_i_237/DI[2]
|
||||
SYNC/ROMAddress_reg[9]_i_266/DI[2]
|
||||
SYNC/ROMAddress[3]_i_103/I5
|
||||
.. and 378 more pins.
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
||||
Phase 6 Post Hold Fix | Checksum: 197295544
|
||||
|
||||
Time (s): cpu = 00:02:22 ; elapsed = 00:01:48 . Memory (MB): peak = 1630.195 ; gain = 130.180
|
||||
|
||||
Phase 7 Route finalize
|
||||
|
||||
Router Utilization Summary
|
||||
Global Vertical Routing Utilization = 0.0881194 %
|
||||
Global Horizontal Routing Utilization = 0.100414 %
|
||||
Global Vertical Routing Utilization = 2.83094 %
|
||||
Global Horizontal Routing Utilization = 3.41935 %
|
||||
Routable Net Status*
|
||||
*Does not include unroutable nets such as driverless and loadless.
|
||||
Run report_route_status for detailed report.
|
||||
@ -449,58 +551,90 @@ Router Utilization Summary
|
||||
Number of Partially Routed Nets = 0
|
||||
Number of Node Overlaps = 0
|
||||
|
||||
Phase 7 Route finalize | Checksum: 19cea99c1
|
||||
Congestion Report
|
||||
North Dir 1x1 Area, Max Cong = 54.0541%, No Congested Regions.
|
||||
South Dir 1x1 Area, Max Cong = 79.2793%, No Congested Regions.
|
||||
East Dir 1x1 Area, Max Cong = 60.2941%, No Congested Regions.
|
||||
West Dir 1x1 Area, Max Cong = 75%, No Congested Regions.
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
||||
------------------------------
|
||||
Reporting congestion hotspots
|
||||
------------------------------
|
||||
Direction: North
|
||||
----------------
|
||||
Congested clusters found at Level 0
|
||||
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
|
||||
Direction: South
|
||||
----------------
|
||||
Congested clusters found at Level 0
|
||||
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
|
||||
Direction: East
|
||||
----------------
|
||||
Congested clusters found at Level 0
|
||||
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
|
||||
Direction: West
|
||||
----------------
|
||||
Congested clusters found at Level 0
|
||||
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
|
||||
|
||||
Phase 7 Route finalize | Checksum: 1f1dffd6a
|
||||
|
||||
Time (s): cpu = 00:02:22 ; elapsed = 00:01:48 . Memory (MB): peak = 1630.195 ; gain = 130.180
|
||||
|
||||
Phase 8 Verifying routed nets
|
||||
|
||||
Verification completed successfully
|
||||
Phase 8 Verifying routed nets | Checksum: 19cea99c1
|
||||
Phase 8 Verifying routed nets | Checksum: 1f1dffd6a
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1461.477 ; gain = 110.379
|
||||
Time (s): cpu = 00:02:22 ; elapsed = 00:01:48 . Memory (MB): peak = 1630.195 ; gain = 130.180
|
||||
|
||||
Phase 9 Depositing Routes
|
||||
Phase 9 Depositing Routes | Checksum: 17f26a4e0
|
||||
Phase 9 Depositing Routes | Checksum: 238ddaa41
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1461.477 ; gain = 110.379
|
||||
Time (s): cpu = 00:02:23 ; elapsed = 00:01:49 . Memory (MB): peak = 1630.195 ; gain = 130.180
|
||||
|
||||
Phase 10 Post Router Timing
|
||||
INFO: [Route 35-57] Estimated Timing Summary | WNS=33.241 | TNS=0.000 | WHS=0.083 | THS=0.000 |
|
||||
|
||||
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
|
||||
Phase 10 Post Router Timing | Checksum: 17f26a4e0
|
||||
Phase 10.1 Update Timing
|
||||
Phase 10.1 Update Timing | Checksum: 1f42f7dac
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1461.477 ; gain = 110.379
|
||||
Time (s): cpu = 00:02:23 ; elapsed = 00:01:49 . Memory (MB): peak = 1630.195 ; gain = 130.180
|
||||
INFO: [Route 35-57] Estimated Timing Summary | WNS=-5.617 | TNS=-86.439| WHS=-0.027 | THS=-0.027 |
|
||||
|
||||
WARNING: [Route 35-328] Router estimated timing not met.
|
||||
Resolution: For a complete and accurate timing signoff, report_timing_summary must be run after route_design. Alternatively, route_design can be run with the -timing_summary option to enable a complete timing signoff at the end of route_design.
|
||||
Phase 10 Post Router Timing | Checksum: 1f42f7dac
|
||||
|
||||
Time (s): cpu = 00:02:23 ; elapsed = 00:01:49 . Memory (MB): peak = 1630.195 ; gain = 130.180
|
||||
INFO: [Route 35-16] Router Completed Successfully
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1461.477 ; gain = 110.379
|
||||
Time (s): cpu = 00:02:23 ; elapsed = 00:01:49 . Memory (MB): peak = 1630.195 ; gain = 130.180
|
||||
|
||||
Routing Is Done.
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
74 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
93 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
route_design completed successfully
|
||||
route_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:22 . Memory (MB): peak = 1461.477 ; gain = 110.379
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1461.477 ; gain = 0.000
|
||||
route_design: Time (s): cpu = 00:02:25 ; elapsed = 00:01:52 . Memory (MB): peak = 1630.195 ; gain = 130.180
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1630.195 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1630.195 ; gain = 0.000
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 1461.910 ; gain = 0.434
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1461.910 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.257 . Memory (MB): peak = 1630.195 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
|
||||
Command: report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt.
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt.
|
||||
report_drc completed successfully
|
||||
INFO: [runtcl-4] Executing : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
|
||||
Command: report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [DRC 23-133] Running Methodology with 2 threads
|
||||
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt.
|
||||
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt.
|
||||
report_methodology completed successfully
|
||||
INFO: [runtcl-4] Executing : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
|
||||
Command: report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
|
||||
@ -508,67 +642,33 @@ INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Running Vector-less Activity Propagation...
|
||||
|
||||
Finished Running Vector-less Activity Propagation
|
||||
86 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
105 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
report_power completed successfully
|
||||
INFO: [runtcl-4] Executing : report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb
|
||||
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
|
||||
INFO: [runtcl-4] Executing : report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt
|
||||
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
|
||||
INFO: [runtcl-4] Executing : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt
|
||||
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
INFO: [Common 17-206] Exiting Vivado at Tue Dec 7 12:43:48 2021...
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Tue Dec 7 12:44:06 2021
|
||||
# Process ID: 5252
|
||||
# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1
|
||||
# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace
|
||||
# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi
|
||||
# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source VGA_top.tcl -notrace
|
||||
Command: open_checkpoint VGA_top_routed.dcp
|
||||
|
||||
Starting open_checkpoint Task
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 250.652 ; gain = 0.000
|
||||
INFO: [Netlist 29-17] Analyzing 35 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-479] Netlist was created with Vivado 2018.3
|
||||
INFO: [Device 21-403] Loading part xc7z010clg400-1
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Timing 38-478] Restoring timing data from binary archive.
|
||||
INFO: [Timing 38-479] Binary timing data restore complete.
|
||||
INFO: [Project 1-856] Restoring constraints from binary archive.
|
||||
INFO: [Project 1-853] Binary constraint restore complete.
|
||||
Reading XDEF placement.
|
||||
Reading placer database...
|
||||
Reading XDEF routing.
|
||||
Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.095 . Memory (MB): peak = 1208.145 ; gain = 0.000
|
||||
Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB |
|
||||
Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.095 . Memory (MB): peak = 1208.145 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1208.145 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
INFO: [Project 1-604] Checkpoint was created with Vivado v2018.3 (64-bit) build 2405991
|
||||
open_checkpoint: Time (s): cpu = 00:00:12 ; elapsed = 00:00:17 . Memory (MB): peak = 1208.145 ; gain = 957.492
|
||||
Command: write_bitstream -force VGA_top.bit
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
Running DRC as a precondition to command write_bitstream
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1704] No user IP repositories specified
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.3/data/ip'.
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
WARNING: [DRC PDRC-153] Gated clock check: Net UPD/dataOut_reg[18]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[18]_LDC_i_1/O, cell UPD/dataOut_reg[18]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
||||
WARNING: [DRC PDRC-153] Gated clock check: Net UPD/dataOut_reg[19]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[19]_LDC_i_1/O, cell UPD/dataOut_reg[19]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
||||
WARNING: [DRC PDRC-153] Gated clock check: Net UPD/dataOut_reg[1]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[1]_LDC_i_1/O, cell UPD/dataOut_reg[1]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
||||
WARNING: [DRC PDRC-153] Gated clock check: Net UPD/dataOut_reg[20]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[20]_LDC_i_1/O, cell UPD/dataOut_reg[20]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
||||
WARNING: [DRC PDRC-153] Gated clock check: Net UPD/dataOut_reg[21]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[21]_LDC_i_1/O, cell UPD/dataOut_reg[21]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
||||
WARNING: [DRC PDRC-153] Gated clock check: Net UPD/dataOut_reg[4]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[4]_LDC_i_1/O, cell UPD/dataOut_reg[4]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
||||
WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
|
||||
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings
|
||||
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 7 Warnings
|
||||
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
|
||||
INFO: [Designutils 20-2272] Running write_bitstream with 2 threads.
|
||||
Loading data files...
|
||||
@ -579,9 +679,9 @@ Creating bitmap...
|
||||
Creating bitstream...
|
||||
Writing bitstream ./VGA_top.bit...
|
||||
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
|
||||
INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
|
||||
INFO: [Project 1-118] WebTalk data collection is enabled (User setting is ON. Install Setting is ON.).
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
22 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
124 Infos, 11 Warnings, 1 Critical Warnings and 0 Errors encountered.
|
||||
write_bitstream completed successfully
|
||||
write_bitstream: Time (s): cpu = 00:00:10 ; elapsed = 00:00:28 . Memory (MB): peak = 1679.344 ; gain = 471.199
|
||||
INFO: [Common 17-206] Exiting Vivado at Tue Dec 7 12:44:53 2021...
|
||||
write_bitstream: Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1942.887 ; gain = 312.691
|
||||
INFO: [Common 17-206] Exiting Vivado at Tue Jan 4 12:21:36 2022...
|
||||
|
||||
@ -1,534 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Tue Nov 23 09:55:17 2021
|
||||
# Process ID: 11872
|
||||
# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1
|
||||
# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace
|
||||
# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi
|
||||
# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source VGA_top.tcl -notrace
|
||||
Command: link_design -top VGA_top -part xc7z010clg400-1
|
||||
Design is defaulting to srcset: sources_1
|
||||
Design is defaulting to constrset: constrs_1
|
||||
INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.dcp' for cell 'U0'
|
||||
INFO: [Netlist 29-17] Analyzing 7 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-479] Netlist was created with Vivado 2018.3
|
||||
INFO: [Device 21-403] Loading part xc7z010clg400-1
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
|
||||
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
|
||||
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
|
||||
INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
|
||||
get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1242.094 ; gain = 551.320
|
||||
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
|
||||
Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
|
||||
Finished Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1242.094 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
link_design completed successfully
|
||||
link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:24 . Memory (MB): peak = 1242.094 ; gain = 879.125
|
||||
Command: opt_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
Running DRC as a precondition to command opt_design
|
||||
|
||||
Starting DRC Task
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Project 1-461] DRC finished with 0 Errors
|
||||
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.510 . Memory (MB): peak = 1242.094 ; gain = 0.000
|
||||
|
||||
Starting Cache Timing Information Task
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [Timing 38-2] Deriving generated clocks
|
||||
Ending Cache Timing Information Task | Checksum: 167d6f2bc
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1258.906 ; gain = 16.812
|
||||
|
||||
Starting Logic Optimization Task
|
||||
|
||||
Phase 1 Retarget
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Opt 31-49] Retargeted 0 cell(s).
|
||||
Phase 1 Retarget | Checksum: 167d6f2bc
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
|
||||
INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
||||
|
||||
Phase 2 Constant propagation
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Phase 2 Constant propagation | Checksum: 167d6f2bc
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
|
||||
|
||||
Phase 3 Sweep
|
||||
Phase 3 Sweep | Checksum: bfc412b4
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
|
||||
|
||||
Phase 4 BUFG optimization
|
||||
INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG
|
||||
INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets
|
||||
Phase 4 BUFG optimization | Checksum: 1480b8b7b
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
|
||||
|
||||
Phase 5 Shift Register Optimization
|
||||
Phase 5 Shift Register Optimization | Checksum: 20e74a998
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
|
||||
|
||||
Phase 6 Post Processing Netlist
|
||||
Phase 6 Post Processing Netlist | Checksum: 1b12e64f9
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
|
||||
Opt_design Change Summary
|
||||
=========================
|
||||
|
||||
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Retarget | 0 | 0 | 1 |
|
||||
| Constant propagation | 0 | 0 | 0 |
|
||||
| Sweep | 0 | 0 | 0 |
|
||||
| BUFG optimization | 0 | 0 | 0 |
|
||||
| Shift Register Optimization | 0 | 0 | 0 |
|
||||
| Post Processing Netlist | 0 | 0 | 0 |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
Starting Connectivity Check Task
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
Ending Logic Optimization Task | Checksum: 14d3cc591
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
|
||||
Starting Power Optimization Task
|
||||
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
|
||||
Ending Power Optimization Task | Checksum: 14d3cc591
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
|
||||
Starting Final Cleanup Task
|
||||
Ending Final Cleanup Task | Checksum: 14d3cc591
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
|
||||
Starting Netlist Obfuscation Task
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
Ending Netlist Obfuscation Task | Checksum: 14d3cc591
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
opt_design completed successfully
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
|
||||
Command: report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt.
|
||||
report_drc completed successfully
|
||||
Command: place_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
Running DRC as a precondition to command place_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Starting Placer Task
|
||||
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
|
||||
|
||||
Phase 1 Placer Initialization
|
||||
|
||||
Phase 1.1 Placer Initialization Netlist Sorting
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 12c34edfb
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.
|
||||
|
||||
bouton_down_IBUF_inst (IBUF.O) is locked to IOB_X0Y1
|
||||
bouton_down_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0
|
||||
Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin.
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 172dde9eb
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.276 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
|
||||
Phase 1.3 Build Placer Netlist Model
|
||||
Phase 1.3 Build Placer Netlist Model | Checksum: 1fe9c5a85
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.329 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
|
||||
Phase 1.4 Constrain Clocks/Macros
|
||||
Phase 1.4 Constrain Clocks/Macros | Checksum: 1fe9c5a85
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.330 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
Phase 1 Placer Initialization | Checksum: 1fe9c5a85
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.330 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
|
||||
Phase 2 Global Placement
|
||||
|
||||
Phase 2.1 Floorplanning
|
||||
Phase 2.1 Floorplanning | Checksum: 24fbfc31b
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.362 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
|
||||
Phase 2.2 Physical Synthesis In Placer
|
||||
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
|
||||
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
|
||||
INFO: [Physopt 32-949] No candidate nets found for HD net replication
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
|
||||
Summary of Physical Synthesis Optimizations
|
||||
============================================
|
||||
|
||||
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 |
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Phase 2.2 Physical Synthesis In Placer | Checksum: 19571fbec
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.767 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
Phase 2 Global Placement | Checksum: 19f068e3b
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.778 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
|
||||
Phase 3 Detail Placement
|
||||
|
||||
Phase 3.1 Commit Multi Column Macros
|
||||
Phase 3.1 Commit Multi Column Macros | Checksum: 19f068e3b
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.779 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 15793daff
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.810 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
|
||||
Phase 3.3 Area Swap Optimization
|
||||
Phase 3.3 Area Swap Optimization | Checksum: 140188978
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.812 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
|
||||
Phase 3.4 Pipeline Register Optimization
|
||||
Phase 3.4 Pipeline Register Optimization | Checksum: 1b233c362
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.813 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
|
||||
Phase 3.5 Small Shape Detail Placement
|
||||
Phase 3.5 Small Shape Detail Placement | Checksum: 13118e91f
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.865 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
|
||||
Phase 3.6 Re-assign LUT pins
|
||||
Phase 3.6 Re-assign LUT pins | Checksum: 8f675022
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.871 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
|
||||
Phase 3.7 Pipeline Register Optimization
|
||||
Phase 3.7 Pipeline Register Optimization | Checksum: 1208a0a3c
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.872 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
Phase 3 Detail Placement | Checksum: 1208a0a3c
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.873 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
|
||||
Phase 4 Post Placement Optimization and Clean-Up
|
||||
|
||||
Phase 4.1 Post Commit Optimization
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
|
||||
Phase 4.1.1 Post Placement Optimization
|
||||
Post Placement Optimization Initialization | Checksum: 150311e2f
|
||||
|
||||
Phase 4.1.1.1 BUFG Insertion
|
||||
INFO: [Place 46-46] BUFG insertion identified 0 candidate nets, 0 success, 0 bufg driver replicated, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason
|
||||
Phase 4.1.1.1 BUFG Insertion | Checksum: 150311e2f
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.917 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
INFO: [Place 30-746] Post Placement Timing Summary WNS=35.783. For the most accurate timing information please run report_timing.
|
||||
Phase 4.1.1 Post Placement Optimization | Checksum: 1b17843c4
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.918 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
Phase 4.1 Post Commit Optimization | Checksum: 1b17843c4
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.918 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
|
||||
Phase 4.2 Post Placement Cleanup
|
||||
Phase 4.2 Post Placement Cleanup | Checksum: 1b17843c4
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.920 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
|
||||
Phase 4.3 Placer Reporting
|
||||
Phase 4.3 Placer Reporting | Checksum: 1b17843c4
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.921 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
|
||||
Phase 4.4 Final Placement Cleanup
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
Phase 4.4 Final Placement Cleanup | Checksum: 18c66ff7a
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.923 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 18c66ff7a
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.923 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
Ending Placer Task | Checksum: d428089a
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.924 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
57 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
place_design completed successfully
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.041 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_io -file VGA_top_io_placed.rpt
|
||||
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb
|
||||
INFO: [runtcl-4] Executing : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt
|
||||
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1342.871 ; gain = 0.000
|
||||
Command: route_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
Running DRC as a precondition to command route_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG.
|
||||
Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin.
|
||||
This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.
|
||||
|
||||
bouton_down_IBUF_inst (IBUF.O) is locked to IOB_X0Y1
|
||||
bouton_down_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
|
||||
Starting Routing Task
|
||||
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
|
||||
Checksum: PlaceDB: efe4607 ConstDB: 0 ShapeSum: c529c293 RouteDB: 0
|
||||
|
||||
Phase 1 Build RT Design
|
||||
Phase 1 Build RT Design | Checksum: ce868b76
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1412.223 ; gain = 69.352
|
||||
Post Restoration Checksum: NetGraph: a7807a20 NumContArr: 27061156 Constraints: 0 Timing: 0
|
||||
|
||||
Phase 2 Router Initialization
|
||||
|
||||
Phase 2.1 Create Timer
|
||||
Phase 2.1 Create Timer | Checksum: ce868b76
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1442.484 ; gain = 99.613
|
||||
|
||||
Phase 2.2 Fix Topology Constraints
|
||||
Phase 2.2 Fix Topology Constraints | Checksum: ce868b76
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1448.547 ; gain = 105.676
|
||||
|
||||
Phase 2.3 Pre Route Cleanup
|
||||
Phase 2.3 Pre Route Cleanup | Checksum: ce868b76
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1448.547 ; gain = 105.676
|
||||
Number of Nodes with overlaps = 0
|
||||
|
||||
Phase 2.4 Update Timing
|
||||
Phase 2.4 Update Timing | Checksum: dcb7e2f8
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1453.652 ; gain = 110.781
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.908 | TNS=0.000 | WHS=-0.278 | THS=-4.597 |
|
||||
|
||||
Phase 2 Router Initialization | Checksum: 173ad2ca3
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1453.652 ; gain = 110.781
|
||||
|
||||
Phase 3 Initial Routing
|
||||
Phase 3 Initial Routing | Checksum: 1c424a5c2
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1453.652 ; gain = 110.781
|
||||
|
||||
Phase 4 Rip-up And Reroute
|
||||
|
||||
Phase 4.1 Global Iteration 0
|
||||
Number of Nodes with overlaps = 9
|
||||
Number of Nodes with overlaps = 0
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=34.457 | TNS=0.000 | WHS=N/A | THS=N/A |
|
||||
|
||||
Phase 4.1 Global Iteration 0 | Checksum: 123c29b62
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1453.652 ; gain = 110.781
|
||||
Phase 4 Rip-up And Reroute | Checksum: 123c29b62
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1453.652 ; gain = 110.781
|
||||
|
||||
Phase 5 Delay and Skew Optimization
|
||||
|
||||
Phase 5.1 Delay CleanUp
|
||||
Phase 5.1 Delay CleanUp | Checksum: 123c29b62
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1453.652 ; gain = 110.781
|
||||
|
||||
Phase 5.2 Clock Skew Optimization
|
||||
Phase 5.2 Clock Skew Optimization | Checksum: 123c29b62
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1453.652 ; gain = 110.781
|
||||
Phase 5 Delay and Skew Optimization | Checksum: 123c29b62
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1453.652 ; gain = 110.781
|
||||
|
||||
Phase 6 Post Hold Fix
|
||||
|
||||
Phase 6.1 Hold Fix Iter
|
||||
|
||||
Phase 6.1.1 Update Timing
|
||||
Phase 6.1.1 Update Timing | Checksum: fe7535e4
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1453.652 ; gain = 110.781
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=34.610 | TNS=0.000 | WHS=0.075 | THS=0.000 |
|
||||
|
||||
Phase 6.1 Hold Fix Iter | Checksum: fe7535e4
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1453.652 ; gain = 110.781
|
||||
Phase 6 Post Hold Fix | Checksum: fe7535e4
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1453.652 ; gain = 110.781
|
||||
|
||||
Phase 7 Route finalize
|
||||
|
||||
Router Utilization Summary
|
||||
Global Vertical Routing Utilization = 0.0425113 %
|
||||
Global Horizontal Routing Utilization = 0.0321691 %
|
||||
Routable Net Status*
|
||||
*Does not include unroutable nets such as driverless and loadless.
|
||||
Run report_route_status for detailed report.
|
||||
Number of Failed Nets = 0
|
||||
Number of Unrouted Nets = 0
|
||||
Number of Partially Routed Nets = 0
|
||||
Number of Node Overlaps = 0
|
||||
|
||||
Phase 7 Route finalize | Checksum: fe7535e4
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1453.652 ; gain = 110.781
|
||||
|
||||
Phase 8 Verifying routed nets
|
||||
|
||||
Verification completed successfully
|
||||
Phase 8 Verifying routed nets | Checksum: fe7535e4
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1454.480 ; gain = 111.609
|
||||
|
||||
Phase 9 Depositing Routes
|
||||
Phase 9 Depositing Routes | Checksum: ac130b84
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1454.480 ; gain = 111.609
|
||||
|
||||
Phase 10 Post Router Timing
|
||||
INFO: [Route 35-57] Estimated Timing Summary | WNS=34.610 | TNS=0.000 | WHS=0.075 | THS=0.000 |
|
||||
|
||||
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
|
||||
Phase 10 Post Router Timing | Checksum: ac130b84
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1454.480 ; gain = 111.609
|
||||
INFO: [Route 35-16] Router Completed Successfully
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1454.480 ; gain = 111.609
|
||||
|
||||
Routing Is Done.
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
74 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
route_design completed successfully
|
||||
route_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1454.480 ; gain = 111.609
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1454.480 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.043 . Memory (MB): peak = 1454.938 ; gain = 0.457
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1454.938 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
|
||||
Command: report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt.
|
||||
report_drc completed successfully
|
||||
INFO: [runtcl-4] Executing : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
|
||||
Command: report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [DRC 23-133] Running Methodology with 2 threads
|
||||
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt.
|
||||
report_methodology completed successfully
|
||||
INFO: [runtcl-4] Executing : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
|
||||
Command: report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Running Vector-less Activity Propagation...
|
||||
|
||||
Finished Running Vector-less Activity Propagation
|
||||
86 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
report_power completed successfully
|
||||
INFO: [runtcl-4] Executing : report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb
|
||||
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
INFO: [runtcl-4] Executing : report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt
|
||||
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
|
||||
INFO: [runtcl-4] Executing : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt
|
||||
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
INFO: [Common 17-206] Exiting Vivado at Tue Nov 23 09:56:04 2021...
|
||||
@ -1,523 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Tue Nov 30 12:02:04 2021
|
||||
# Process ID: 12280
|
||||
# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1
|
||||
# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace
|
||||
# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi
|
||||
# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source VGA_top.tcl -notrace
|
||||
Command: link_design -top VGA_top -part xc7z010clg400-1
|
||||
Design is defaulting to srcset: sources_1
|
||||
Design is defaulting to constrset: constrs_1
|
||||
INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.dcp' for cell 'U0'
|
||||
INFO: [Netlist 29-17] Analyzing 3 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-479] Netlist was created with Vivado 2018.3
|
||||
INFO: [Device 21-403] Loading part xc7z010clg400-1
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
|
||||
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
|
||||
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
|
||||
INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
|
||||
get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1224.238 ; gain = 533.496
|
||||
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
|
||||
Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
|
||||
Finished Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1224.238 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
link_design completed successfully
|
||||
link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:16 . Memory (MB): peak = 1224.238 ; gain = 861.020
|
||||
Command: opt_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
Running DRC as a precondition to command opt_design
|
||||
|
||||
Starting DRC Task
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Project 1-461] DRC finished with 0 Errors
|
||||
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.499 . Memory (MB): peak = 1224.238 ; gain = 0.000
|
||||
|
||||
Starting Cache Timing Information Task
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [Timing 38-2] Deriving generated clocks
|
||||
Ending Cache Timing Information Task | Checksum: d1b7283d
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1241.336 ; gain = 17.098
|
||||
|
||||
Starting Logic Optimization Task
|
||||
|
||||
Phase 1 Retarget
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Opt 31-49] Retargeted 0 cell(s).
|
||||
Phase 1 Retarget | Checksum: d1b7283d
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
|
||||
INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
||||
|
||||
Phase 2 Constant propagation
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Phase 2 Constant propagation | Checksum: d1b7283d
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
|
||||
|
||||
Phase 3 Sweep
|
||||
Phase 3 Sweep | Checksum: 4c4916a3
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
|
||||
|
||||
Phase 4 BUFG optimization
|
||||
INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG
|
||||
INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets
|
||||
Phase 4 BUFG optimization | Checksum: ea635365
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
|
||||
|
||||
Phase 5 Shift Register Optimization
|
||||
Phase 5 Shift Register Optimization | Checksum: 189961a21
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
|
||||
|
||||
Phase 6 Post Processing Netlist
|
||||
Phase 6 Post Processing Netlist | Checksum: fdaedd04
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
|
||||
Opt_design Change Summary
|
||||
=========================
|
||||
|
||||
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Retarget | 0 | 0 | 1 |
|
||||
| Constant propagation | 0 | 0 | 0 |
|
||||
| Sweep | 0 | 0 | 0 |
|
||||
| BUFG optimization | 0 | 0 | 0 |
|
||||
| Shift Register Optimization | 0 | 0 | 0 |
|
||||
| Post Processing Netlist | 0 | 0 | 0 |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
Starting Connectivity Check Task
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
Ending Logic Optimization Task | Checksum: 1a5a98288
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
|
||||
Starting Power Optimization Task
|
||||
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
|
||||
Ending Power Optimization Task | Checksum: 1a5a98288
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
|
||||
Starting Final Cleanup Task
|
||||
Ending Final Cleanup Task | Checksum: 1a5a98288
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
|
||||
Starting Netlist Obfuscation Task
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
Ending Netlist Obfuscation Task | Checksum: 1a5a98288
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
opt_design completed successfully
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
|
||||
Command: report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt.
|
||||
report_drc completed successfully
|
||||
Command: place_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
Running DRC as a precondition to command place_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Starting Placer Task
|
||||
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
|
||||
|
||||
Phase 1 Placer Initialization
|
||||
|
||||
Phase 1.1 Placer Initialization Netlist Sorting
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: f74f5d31
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: dff97cf7
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.238 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
|
||||
Phase 1.3 Build Placer Netlist Model
|
||||
Phase 1.3 Build Placer Netlist Model | Checksum: 1427c2c70
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.291 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
|
||||
Phase 1.4 Constrain Clocks/Macros
|
||||
Phase 1.4 Constrain Clocks/Macros | Checksum: 1427c2c70
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.292 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
Phase 1 Placer Initialization | Checksum: 1427c2c70
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.293 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
|
||||
Phase 2 Global Placement
|
||||
|
||||
Phase 2.1 Floorplanning
|
||||
Phase 2.1 Floorplanning | Checksum: fef86770
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.335 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
|
||||
Phase 2.2 Physical Synthesis In Placer
|
||||
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
|
||||
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
|
||||
INFO: [Physopt 32-949] No candidate nets found for HD net replication
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
|
||||
Summary of Physical Synthesis Optimizations
|
||||
============================================
|
||||
|
||||
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 |
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Phase 2.2 Physical Synthesis In Placer | Checksum: 1ace7cfcc
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.633 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
Phase 2 Global Placement | Checksum: 141a32296
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.643 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
|
||||
Phase 3 Detail Placement
|
||||
|
||||
Phase 3.1 Commit Multi Column Macros
|
||||
Phase 3.1 Commit Multi Column Macros | Checksum: 141a32296
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.644 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 78fa4a02
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.691 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
|
||||
Phase 3.3 Area Swap Optimization
|
||||
Phase 3.3 Area Swap Optimization | Checksum: d7dfc3b7
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.694 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
|
||||
Phase 3.4 Pipeline Register Optimization
|
||||
Phase 3.4 Pipeline Register Optimization | Checksum: d7dfc3b7
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.695 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
|
||||
Phase 3.5 Small Shape Detail Placement
|
||||
Phase 3.5 Small Shape Detail Placement | Checksum: 12debda8c
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.741 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
|
||||
Phase 3.6 Re-assign LUT pins
|
||||
Phase 3.6 Re-assign LUT pins | Checksum: 14ae64a6f
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.744 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
|
||||
Phase 3.7 Pipeline Register Optimization
|
||||
Phase 3.7 Pipeline Register Optimization | Checksum: 14ae64a6f
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.744 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
Phase 3 Detail Placement | Checksum: 14ae64a6f
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.745 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
|
||||
Phase 4 Post Placement Optimization and Clean-Up
|
||||
|
||||
Phase 4.1 Post Commit Optimization
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
|
||||
Phase 4.1.1 Post Placement Optimization
|
||||
Post Placement Optimization Initialization | Checksum: 1cebea503
|
||||
|
||||
Phase 4.1.1.1 BUFG Insertion
|
||||
INFO: [Place 46-46] BUFG insertion identified 0 candidate nets, 0 success, 0 bufg driver replicated, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason
|
||||
Phase 4.1.1.1 BUFG Insertion | Checksum: 1cebea503
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.774 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
INFO: [Place 30-746] Post Placement Timing Summary WNS=36.129. For the most accurate timing information please run report_timing.
|
||||
Phase 4.1.1 Post Placement Optimization | Checksum: 20987d072
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.775 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
Phase 4.1 Post Commit Optimization | Checksum: 20987d072
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.775 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
|
||||
Phase 4.2 Post Placement Cleanup
|
||||
Phase 4.2 Post Placement Cleanup | Checksum: 20987d072
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.776 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
|
||||
Phase 4.3 Placer Reporting
|
||||
Phase 4.3 Placer Reporting | Checksum: 20987d072
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.777 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
|
||||
Phase 4.4 Final Placement Cleanup
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
Phase 4.4 Final Placement Cleanup | Checksum: 27c4f344f
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.779 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 27c4f344f
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.779 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
Ending Placer Task | Checksum: 1ab889c44
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.780 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
57 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
place_design completed successfully
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_io -file VGA_top_io_placed.rpt
|
||||
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb
|
||||
INFO: [runtcl-4] Executing : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt
|
||||
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1327.883 ; gain = 0.000
|
||||
Command: route_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
Running DRC as a precondition to command route_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
|
||||
Starting Routing Task
|
||||
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
|
||||
Checksum: PlaceDB: e36d3f86 ConstDB: 0 ShapeSum: c81b5cbe RouteDB: 0
|
||||
|
||||
Phase 1 Build RT Design
|
||||
Phase 1 Build RT Design | Checksum: 408a135c
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1399.160 ; gain = 71.277
|
||||
Post Restoration Checksum: NetGraph: 2bba0e1e NumContArr: 14d0053e Constraints: 0 Timing: 0
|
||||
|
||||
Phase 2 Router Initialization
|
||||
|
||||
Phase 2.1 Create Timer
|
||||
Phase 2.1 Create Timer | Checksum: 408a135c
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1423.402 ; gain = 95.520
|
||||
|
||||
Phase 2.2 Fix Topology Constraints
|
||||
Phase 2.2 Fix Topology Constraints | Checksum: 408a135c
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1429.410 ; gain = 101.527
|
||||
|
||||
Phase 2.3 Pre Route Cleanup
|
||||
Phase 2.3 Pre Route Cleanup | Checksum: 408a135c
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1429.410 ; gain = 101.527
|
||||
Number of Nodes with overlaps = 0
|
||||
|
||||
Phase 2.4 Update Timing
|
||||
Phase 2.4 Update Timing | Checksum: 193e9052a
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1432.094 ; gain = 104.211
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=36.042 | TNS=0.000 | WHS=-0.250 | THS=-3.548 |
|
||||
|
||||
Phase 2 Router Initialization | Checksum: 196977bdb
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1432.094 ; gain = 104.211
|
||||
|
||||
Phase 3 Initial Routing
|
||||
Phase 3 Initial Routing | Checksum: 14455b7e9
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1432.094 ; gain = 104.211
|
||||
|
||||
Phase 4 Rip-up And Reroute
|
||||
|
||||
Phase 4.1 Global Iteration 0
|
||||
Number of Nodes with overlaps = 4
|
||||
Number of Nodes with overlaps = 0
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.940 | TNS=0.000 | WHS=N/A | THS=N/A |
|
||||
|
||||
Phase 4.1 Global Iteration 0 | Checksum: e844e306
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1432.094 ; gain = 104.211
|
||||
Phase 4 Rip-up And Reroute | Checksum: e844e306
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1432.094 ; gain = 104.211
|
||||
|
||||
Phase 5 Delay and Skew Optimization
|
||||
|
||||
Phase 5.1 Delay CleanUp
|
||||
Phase 5.1 Delay CleanUp | Checksum: e844e306
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1432.094 ; gain = 104.211
|
||||
|
||||
Phase 5.2 Clock Skew Optimization
|
||||
Phase 5.2 Clock Skew Optimization | Checksum: e844e306
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1432.094 ; gain = 104.211
|
||||
Phase 5 Delay and Skew Optimization | Checksum: e844e306
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1432.094 ; gain = 104.211
|
||||
|
||||
Phase 6 Post Hold Fix
|
||||
|
||||
Phase 6.1 Hold Fix Iter
|
||||
|
||||
Phase 6.1.1 Update Timing
|
||||
Phase 6.1.1 Update Timing | Checksum: 9a801cee
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1432.094 ; gain = 104.211
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=36.093 | TNS=0.000 | WHS=0.063 | THS=0.000 |
|
||||
|
||||
Phase 6.1 Hold Fix Iter | Checksum: 9a801cee
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1432.094 ; gain = 104.211
|
||||
Phase 6 Post Hold Fix | Checksum: 9a801cee
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1432.094 ; gain = 104.211
|
||||
|
||||
Phase 7 Route finalize
|
||||
|
||||
Router Utilization Summary
|
||||
Global Vertical Routing Utilization = 0.0209741 %
|
||||
Global Horizontal Routing Utilization = 0.00827206 %
|
||||
Routable Net Status*
|
||||
*Does not include unroutable nets such as driverless and loadless.
|
||||
Run report_route_status for detailed report.
|
||||
Number of Failed Nets = 0
|
||||
Number of Unrouted Nets = 0
|
||||
Number of Partially Routed Nets = 0
|
||||
Number of Node Overlaps = 0
|
||||
|
||||
Phase 7 Route finalize | Checksum: 12bf57e3c
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1432.094 ; gain = 104.211
|
||||
|
||||
Phase 8 Verifying routed nets
|
||||
|
||||
Verification completed successfully
|
||||
Phase 8 Verifying routed nets | Checksum: 12bf57e3c
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1433.680 ; gain = 105.797
|
||||
|
||||
Phase 9 Depositing Routes
|
||||
Phase 9 Depositing Routes | Checksum: f9632067
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1433.680 ; gain = 105.797
|
||||
|
||||
Phase 10 Post Router Timing
|
||||
INFO: [Route 35-57] Estimated Timing Summary | WNS=36.093 | TNS=0.000 | WHS=0.063 | THS=0.000 |
|
||||
|
||||
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
|
||||
Phase 10 Post Router Timing | Checksum: f9632067
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1433.680 ; gain = 105.797
|
||||
INFO: [Route 35-16] Router Completed Successfully
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1433.680 ; gain = 105.797
|
||||
|
||||
Routing Is Done.
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
74 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
route_design completed successfully
|
||||
route_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:23 . Memory (MB): peak = 1433.680 ; gain = 105.797
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1433.680 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1433.680 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1433.793 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
|
||||
Command: report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt.
|
||||
report_drc completed successfully
|
||||
INFO: [runtcl-4] Executing : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
|
||||
Command: report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [DRC 23-133] Running Methodology with 2 threads
|
||||
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt.
|
||||
report_methodology completed successfully
|
||||
INFO: [runtcl-4] Executing : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
|
||||
Command: report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Running Vector-less Activity Propagation...
|
||||
|
||||
Finished Running Vector-less Activity Propagation
|
||||
86 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
report_power completed successfully
|
||||
INFO: [runtcl-4] Executing : report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb
|
||||
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
INFO: [runtcl-4] Executing : report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt
|
||||
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
|
||||
INFO: [runtcl-4] Executing : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt
|
||||
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
INFO: [Common 17-206] Exiting Vivado at Tue Nov 30 12:02:53 2021...
|
||||
@ -1,523 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Tue Dec 7 12:19:39 2021
|
||||
# Process ID: 12864
|
||||
# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1
|
||||
# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace
|
||||
# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi
|
||||
# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source VGA_top.tcl -notrace
|
||||
Command: link_design -top VGA_top -part xc7z010clg400-1
|
||||
Design is defaulting to srcset: sources_1
|
||||
Design is defaulting to constrset: constrs_1
|
||||
INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.dcp' for cell 'U0'
|
||||
INFO: [Netlist 29-17] Analyzing 3 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-479] Netlist was created with Vivado 2018.3
|
||||
INFO: [Device 21-403] Loading part xc7z010clg400-1
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
|
||||
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
|
||||
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
|
||||
INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
|
||||
get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1224.508 ; gain = 533.289
|
||||
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
|
||||
Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
|
||||
Finished Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1224.508 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
link_design completed successfully
|
||||
link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:16 . Memory (MB): peak = 1224.508 ; gain = 861.285
|
||||
Command: opt_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
Running DRC as a precondition to command opt_design
|
||||
|
||||
Starting DRC Task
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Project 1-461] DRC finished with 0 Errors
|
||||
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.506 . Memory (MB): peak = 1224.508 ; gain = 0.000
|
||||
|
||||
Starting Cache Timing Information Task
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [Timing 38-2] Deriving generated clocks
|
||||
Ending Cache Timing Information Task | Checksum: 1089519a1
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1241.430 ; gain = 16.922
|
||||
|
||||
Starting Logic Optimization Task
|
||||
|
||||
Phase 1 Retarget
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Opt 31-49] Retargeted 0 cell(s).
|
||||
Phase 1 Retarget | Checksum: 1089519a1
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
|
||||
INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
||||
|
||||
Phase 2 Constant propagation
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Phase 2 Constant propagation | Checksum: 1089519a1
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
|
||||
|
||||
Phase 3 Sweep
|
||||
Phase 3 Sweep | Checksum: 50d21832
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
|
||||
|
||||
Phase 4 BUFG optimization
|
||||
INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG
|
||||
INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets
|
||||
Phase 4 BUFG optimization | Checksum: 95a74d60
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
|
||||
|
||||
Phase 5 Shift Register Optimization
|
||||
Phase 5 Shift Register Optimization | Checksum: 19dd21140
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
|
||||
|
||||
Phase 6 Post Processing Netlist
|
||||
Phase 6 Post Processing Netlist | Checksum: 1575eedad
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
|
||||
Opt_design Change Summary
|
||||
=========================
|
||||
|
||||
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Retarget | 0 | 0 | 1 |
|
||||
| Constant propagation | 0 | 0 | 0 |
|
||||
| Sweep | 0 | 0 | 0 |
|
||||
| BUFG optimization | 0 | 0 | 0 |
|
||||
| Shift Register Optimization | 0 | 0 | 0 |
|
||||
| Post Processing Netlist | 0 | 0 | 0 |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
Starting Connectivity Check Task
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
Ending Logic Optimization Task | Checksum: 1955eb16f
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
|
||||
Starting Power Optimization Task
|
||||
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
|
||||
Ending Power Optimization Task | Checksum: 1955eb16f
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
|
||||
Starting Final Cleanup Task
|
||||
Ending Final Cleanup Task | Checksum: 1955eb16f
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
|
||||
Starting Netlist Obfuscation Task
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
Ending Netlist Obfuscation Task | Checksum: 1955eb16f
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
opt_design completed successfully
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
|
||||
Command: report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt.
|
||||
report_drc completed successfully
|
||||
Command: place_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
Running DRC as a precondition to command place_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Starting Placer Task
|
||||
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
|
||||
|
||||
Phase 1 Placer Initialization
|
||||
|
||||
Phase 1.1 Placer Initialization Netlist Sorting
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a1a0325f
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: eef95bbb
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.244 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
|
||||
Phase 1.3 Build Placer Netlist Model
|
||||
Phase 1.3 Build Placer Netlist Model | Checksum: 1d3a049f7
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.298 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
|
||||
Phase 1.4 Constrain Clocks/Macros
|
||||
Phase 1.4 Constrain Clocks/Macros | Checksum: 1d3a049f7
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.299 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
Phase 1 Placer Initialization | Checksum: 1d3a049f7
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.299 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
|
||||
Phase 2 Global Placement
|
||||
|
||||
Phase 2.1 Floorplanning
|
||||
Phase 2.1 Floorplanning | Checksum: 1722d3694
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.337 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
|
||||
Phase 2.2 Physical Synthesis In Placer
|
||||
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
|
||||
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
|
||||
INFO: [Physopt 32-949] No candidate nets found for HD net replication
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
|
||||
Summary of Physical Synthesis Optimizations
|
||||
============================================
|
||||
|
||||
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 |
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Phase 2.2 Physical Synthesis In Placer | Checksum: 10663e9fd
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.812 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
Phase 2 Global Placement | Checksum: 1aa3f7fa5
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.822 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
|
||||
Phase 3 Detail Placement
|
||||
|
||||
Phase 3.1 Commit Multi Column Macros
|
||||
Phase 3.1 Commit Multi Column Macros | Checksum: 1aa3f7fa5
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.823 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1fa94e875
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.890 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
|
||||
Phase 3.3 Area Swap Optimization
|
||||
Phase 3.3 Area Swap Optimization | Checksum: 1bc3b5afc
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.892 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
|
||||
Phase 3.4 Pipeline Register Optimization
|
||||
Phase 3.4 Pipeline Register Optimization | Checksum: 1bc3b5afc
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.893 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
|
||||
Phase 3.5 Small Shape Detail Placement
|
||||
Phase 3.5 Small Shape Detail Placement | Checksum: 133e8332f
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.941 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
|
||||
Phase 3.6 Re-assign LUT pins
|
||||
Phase 3.6 Re-assign LUT pins | Checksum: d843b10d
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.945 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
|
||||
Phase 3.7 Pipeline Register Optimization
|
||||
Phase 3.7 Pipeline Register Optimization | Checksum: d843b10d
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.945 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
Phase 3 Detail Placement | Checksum: d843b10d
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.946 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
|
||||
Phase 4 Post Placement Optimization and Clean-Up
|
||||
|
||||
Phase 4.1 Post Commit Optimization
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
|
||||
Phase 4.1.1 Post Placement Optimization
|
||||
Post Placement Optimization Initialization | Checksum: 19cf8a569
|
||||
|
||||
Phase 4.1.1.1 BUFG Insertion
|
||||
INFO: [Place 46-46] BUFG insertion identified 0 candidate nets, 0 success, 0 bufg driver replicated, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason
|
||||
Phase 4.1.1.1 BUFG Insertion | Checksum: 19cf8a569
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.978 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
INFO: [Place 30-746] Post Placement Timing Summary WNS=35.155. For the most accurate timing information please run report_timing.
|
||||
Phase 4.1.1 Post Placement Optimization | Checksum: 1e5cba416
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.979 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
Phase 4.1 Post Commit Optimization | Checksum: 1e5cba416
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.979 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
|
||||
Phase 4.2 Post Placement Cleanup
|
||||
Phase 4.2 Post Placement Cleanup | Checksum: 1e5cba416
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.980 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
|
||||
Phase 4.3 Placer Reporting
|
||||
Phase 4.3 Placer Reporting | Checksum: 1e5cba416
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.981 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
|
||||
Phase 4.4 Final Placement Cleanup
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
Phase 4.4 Final Placement Cleanup | Checksum: 1f250909b
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.983 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1f250909b
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.983 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
Ending Placer Task | Checksum: 10d62737c
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.985 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
57 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
place_design completed successfully
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_io -file VGA_top_io_placed.rpt
|
||||
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb
|
||||
INFO: [runtcl-4] Executing : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt
|
||||
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1322.203 ; gain = 0.000
|
||||
Command: route_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
Running DRC as a precondition to command route_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
|
||||
Starting Routing Task
|
||||
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
|
||||
Checksum: PlaceDB: a04ecaff ConstDB: 0 ShapeSum: 6d13a87d RouteDB: 0
|
||||
|
||||
Phase 1 Build RT Design
|
||||
Phase 1 Build RT Design | Checksum: dd396fb6
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1402.008 ; gain = 79.566
|
||||
Post Restoration Checksum: NetGraph: 7c3cbf24 NumContArr: 60fcb092 Constraints: 0 Timing: 0
|
||||
|
||||
Phase 2 Router Initialization
|
||||
|
||||
Phase 2.1 Create Timer
|
||||
Phase 2.1 Create Timer | Checksum: dd396fb6
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1426.234 ; gain = 103.793
|
||||
|
||||
Phase 2.2 Fix Topology Constraints
|
||||
Phase 2.2 Fix Topology Constraints | Checksum: dd396fb6
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1432.270 ; gain = 109.828
|
||||
|
||||
Phase 2.3 Pre Route Cleanup
|
||||
Phase 2.3 Pre Route Cleanup | Checksum: dd396fb6
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1432.270 ; gain = 109.828
|
||||
Number of Nodes with overlaps = 0
|
||||
|
||||
Phase 2.4 Update Timing
|
||||
Phase 2.4 Update Timing | Checksum: 112cc3ffa
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1435.043 ; gain = 112.602
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.100 | TNS=0.000 | WHS=-0.267 | THS=-3.705 |
|
||||
|
||||
Phase 2 Router Initialization | Checksum: 170dc172d
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1435.043 ; gain = 112.602
|
||||
|
||||
Phase 3 Initial Routing
|
||||
Phase 3 Initial Routing | Checksum: 22395080e
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1435.043 ; gain = 112.602
|
||||
|
||||
Phase 4 Rip-up And Reroute
|
||||
|
||||
Phase 4.1 Global Iteration 0
|
||||
Number of Nodes with overlaps = 2
|
||||
Number of Nodes with overlaps = 0
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=34.628 | TNS=0.000 | WHS=N/A | THS=N/A |
|
||||
|
||||
Phase 4.1 Global Iteration 0 | Checksum: 84c8e4d7
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1435.043 ; gain = 112.602
|
||||
Phase 4 Rip-up And Reroute | Checksum: 84c8e4d7
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1435.043 ; gain = 112.602
|
||||
|
||||
Phase 5 Delay and Skew Optimization
|
||||
|
||||
Phase 5.1 Delay CleanUp
|
||||
Phase 5.1 Delay CleanUp | Checksum: 84c8e4d7
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1435.043 ; gain = 112.602
|
||||
|
||||
Phase 5.2 Clock Skew Optimization
|
||||
Phase 5.2 Clock Skew Optimization | Checksum: 84c8e4d7
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1435.043 ; gain = 112.602
|
||||
Phase 5 Delay and Skew Optimization | Checksum: 84c8e4d7
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1435.043 ; gain = 112.602
|
||||
|
||||
Phase 6 Post Hold Fix
|
||||
|
||||
Phase 6.1 Hold Fix Iter
|
||||
|
||||
Phase 6.1.1 Update Timing
|
||||
Phase 6.1.1 Update Timing | Checksum: 7ed72ff4
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1435.043 ; gain = 112.602
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=34.781 | TNS=0.000 | WHS=0.050 | THS=0.000 |
|
||||
|
||||
Phase 6.1 Hold Fix Iter | Checksum: 7ed72ff4
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1435.043 ; gain = 112.602
|
||||
Phase 6 Post Hold Fix | Checksum: 7ed72ff4
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1435.043 ; gain = 112.602
|
||||
|
||||
Phase 7 Route finalize
|
||||
|
||||
Router Utilization Summary
|
||||
Global Vertical Routing Utilization = 0.0236486 %
|
||||
Global Horizontal Routing Utilization = 0.0124081 %
|
||||
Routable Net Status*
|
||||
*Does not include unroutable nets such as driverless and loadless.
|
||||
Run report_route_status for detailed report.
|
||||
Number of Failed Nets = 0
|
||||
Number of Unrouted Nets = 0
|
||||
Number of Partially Routed Nets = 0
|
||||
Number of Node Overlaps = 0
|
||||
|
||||
Phase 7 Route finalize | Checksum: a2cd4f9e
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1435.043 ; gain = 112.602
|
||||
|
||||
Phase 8 Verifying routed nets
|
||||
|
||||
Verification completed successfully
|
||||
Phase 8 Verifying routed nets | Checksum: a2cd4f9e
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1436.496 ; gain = 114.055
|
||||
|
||||
Phase 9 Depositing Routes
|
||||
Phase 9 Depositing Routes | Checksum: 7931b51c
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1436.496 ; gain = 114.055
|
||||
|
||||
Phase 10 Post Router Timing
|
||||
INFO: [Route 35-57] Estimated Timing Summary | WNS=34.781 | TNS=0.000 | WHS=0.050 | THS=0.000 |
|
||||
|
||||
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
|
||||
Phase 10 Post Router Timing | Checksum: 7931b51c
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1436.496 ; gain = 114.055
|
||||
INFO: [Route 35-16] Router Completed Successfully
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1436.496 ; gain = 114.055
|
||||
|
||||
Routing Is Done.
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
74 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
route_design completed successfully
|
||||
route_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:23 . Memory (MB): peak = 1436.496 ; gain = 114.293
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1436.496 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1436.496 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1436.496 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
|
||||
Command: report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt.
|
||||
report_drc completed successfully
|
||||
INFO: [runtcl-4] Executing : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
|
||||
Command: report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [DRC 23-133] Running Methodology with 2 threads
|
||||
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt.
|
||||
report_methodology completed successfully
|
||||
INFO: [runtcl-4] Executing : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
|
||||
Command: report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Running Vector-less Activity Propagation...
|
||||
|
||||
Finished Running Vector-less Activity Propagation
|
||||
86 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
report_power completed successfully
|
||||
INFO: [runtcl-4] Executing : report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb
|
||||
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
INFO: [runtcl-4] Executing : report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt
|
||||
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
|
||||
INFO: [runtcl-4] Executing : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt
|
||||
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
INFO: [Common 17-206] Exiting Vivado at Tue Dec 7 12:20:28 2021...
|
||||
@ -1,523 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Tue Nov 30 12:20:41 2021
|
||||
# Process ID: 12968
|
||||
# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1
|
||||
# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace
|
||||
# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi
|
||||
# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source VGA_top.tcl -notrace
|
||||
Command: link_design -top VGA_top -part xc7z010clg400-1
|
||||
Design is defaulting to srcset: sources_1
|
||||
Design is defaulting to constrset: constrs_1
|
||||
INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.dcp' for cell 'U0'
|
||||
INFO: [Netlist 29-17] Analyzing 3 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-479] Netlist was created with Vivado 2018.3
|
||||
INFO: [Device 21-403] Loading part xc7z010clg400-1
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
|
||||
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
|
||||
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
|
||||
INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
|
||||
get_clocks: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1226.977 ; gain = 533.066
|
||||
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
|
||||
Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
|
||||
Finished Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1226.977 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
link_design completed successfully
|
||||
link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:16 . Memory (MB): peak = 1226.977 ; gain = 862.352
|
||||
Command: opt_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
Running DRC as a precondition to command opt_design
|
||||
|
||||
Starting DRC Task
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Project 1-461] DRC finished with 0 Errors
|
||||
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.501 . Memory (MB): peak = 1226.977 ; gain = 0.000
|
||||
|
||||
Starting Cache Timing Information Task
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [Timing 38-2] Deriving generated clocks
|
||||
Ending Cache Timing Information Task | Checksum: dc2ced6f
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1243.789 ; gain = 16.812
|
||||
|
||||
Starting Logic Optimization Task
|
||||
|
||||
Phase 1 Retarget
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Opt 31-49] Retargeted 0 cell(s).
|
||||
Phase 1 Retarget | Checksum: dc2ced6f
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
|
||||
INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
||||
|
||||
Phase 2 Constant propagation
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Phase 2 Constant propagation | Checksum: dc2ced6f
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
|
||||
|
||||
Phase 3 Sweep
|
||||
Phase 3 Sweep | Checksum: 19e1c8f17
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
|
||||
|
||||
Phase 4 BUFG optimization
|
||||
INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG
|
||||
INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets
|
||||
Phase 4 BUFG optimization | Checksum: c943f809
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
|
||||
|
||||
Phase 5 Shift Register Optimization
|
||||
Phase 5 Shift Register Optimization | Checksum: ba2b01e3
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
|
||||
|
||||
Phase 6 Post Processing Netlist
|
||||
Phase 6 Post Processing Netlist | Checksum: b57bee7a
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
|
||||
Opt_design Change Summary
|
||||
=========================
|
||||
|
||||
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Retarget | 0 | 0 | 1 |
|
||||
| Constant propagation | 0 | 0 | 0 |
|
||||
| Sweep | 0 | 0 | 0 |
|
||||
| BUFG optimization | 0 | 0 | 0 |
|
||||
| Shift Register Optimization | 0 | 0 | 0 |
|
||||
| Post Processing Netlist | 0 | 0 | 0 |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
Starting Connectivity Check Task
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
Ending Logic Optimization Task | Checksum: 13b7a3fb2
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
|
||||
Starting Power Optimization Task
|
||||
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
|
||||
Ending Power Optimization Task | Checksum: 13b7a3fb2
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
|
||||
Starting Final Cleanup Task
|
||||
Ending Final Cleanup Task | Checksum: 13b7a3fb2
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
|
||||
Starting Netlist Obfuscation Task
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
Ending Netlist Obfuscation Task | Checksum: 13b7a3fb2
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
opt_design completed successfully
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.033 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
|
||||
Command: report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt.
|
||||
report_drc completed successfully
|
||||
Command: place_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
Running DRC as a precondition to command place_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Starting Placer Task
|
||||
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
|
||||
|
||||
Phase 1 Placer Initialization
|
||||
|
||||
Phase 1.1 Placer Initialization Netlist Sorting
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 67b44082
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 14d1cdeaf
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.242 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
|
||||
Phase 1.3 Build Placer Netlist Model
|
||||
Phase 1.3 Build Placer Netlist Model | Checksum: 1bfc53c93
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.304 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
|
||||
Phase 1.4 Constrain Clocks/Macros
|
||||
Phase 1.4 Constrain Clocks/Macros | Checksum: 1bfc53c93
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.306 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
Phase 1 Placer Initialization | Checksum: 1bfc53c93
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.306 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
|
||||
Phase 2 Global Placement
|
||||
|
||||
Phase 2.1 Floorplanning
|
||||
Phase 2.1 Floorplanning | Checksum: 152ddf35d
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.344 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
|
||||
Phase 2.2 Physical Synthesis In Placer
|
||||
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
|
||||
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
|
||||
INFO: [Physopt 32-949] No candidate nets found for HD net replication
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
|
||||
Summary of Physical Synthesis Optimizations
|
||||
============================================
|
||||
|
||||
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 |
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Phase 2.2 Physical Synthesis In Placer | Checksum: 166883134
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.872 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
Phase 2 Global Placement | Checksum: 1ea5262ce
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.881 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
|
||||
Phase 3 Detail Placement
|
||||
|
||||
Phase 3.1 Commit Multi Column Macros
|
||||
Phase 3.1 Commit Multi Column Macros | Checksum: 1ea5262ce
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.882 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1350cd04a
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.922 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
|
||||
Phase 3.3 Area Swap Optimization
|
||||
Phase 3.3 Area Swap Optimization | Checksum: 1c8d9a95a
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.924 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
|
||||
Phase 3.4 Pipeline Register Optimization
|
||||
Phase 3.4 Pipeline Register Optimization | Checksum: 1c8d9a95a
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.925 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
|
||||
Phase 3.5 Small Shape Detail Placement
|
||||
Phase 3.5 Small Shape Detail Placement | Checksum: 236b118c7
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.980 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
|
||||
Phase 3.6 Re-assign LUT pins
|
||||
Phase 3.6 Re-assign LUT pins | Checksum: 182b978ad
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.983 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
|
||||
Phase 3.7 Pipeline Register Optimization
|
||||
Phase 3.7 Pipeline Register Optimization | Checksum: 182b978ad
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.983 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
Phase 3 Detail Placement | Checksum: 182b978ad
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.984 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
|
||||
Phase 4 Post Placement Optimization and Clean-Up
|
||||
|
||||
Phase 4.1 Post Commit Optimization
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
|
||||
Phase 4.1.1 Post Placement Optimization
|
||||
Post Placement Optimization Initialization | Checksum: c19cad15
|
||||
|
||||
Phase 4.1.1.1 BUFG Insertion
|
||||
INFO: [Place 46-46] BUFG insertion identified 0 candidate nets, 0 success, 0 bufg driver replicated, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason
|
||||
Phase 4.1.1.1 BUFG Insertion | Checksum: c19cad15
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
INFO: [Place 30-746] Post Placement Timing Summary WNS=36.030. For the most accurate timing information please run report_timing.
|
||||
Phase 4.1.1 Post Placement Optimization | Checksum: a4d8353e
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
Phase 4.1 Post Commit Optimization | Checksum: a4d8353e
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
|
||||
Phase 4.2 Post Placement Cleanup
|
||||
Phase 4.2 Post Placement Cleanup | Checksum: a4d8353e
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
|
||||
Phase 4.3 Placer Reporting
|
||||
Phase 4.3 Placer Reporting | Checksum: a4d8353e
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
|
||||
Phase 4.4 Final Placement Cleanup
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
Phase 4.4 Final Placement Cleanup | Checksum: 80d205c8
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 80d205c8
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
Ending Placer Task | Checksum: 362c66e8
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
57 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
place_design completed successfully
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1325.523 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_io -file VGA_top_io_placed.rpt
|
||||
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1325.781 ; gain = 0.000
|
||||
INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb
|
||||
INFO: [runtcl-4] Executing : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt
|
||||
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1325.781 ; gain = 0.000
|
||||
Command: route_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
Running DRC as a precondition to command route_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
|
||||
Starting Routing Task
|
||||
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
|
||||
Checksum: PlaceDB: 1579e8f6 ConstDB: 0 ShapeSum: 20b27df2 RouteDB: 0
|
||||
|
||||
Phase 1 Build RT Design
|
||||
Phase 1 Build RT Design | Checksum: b6d8bcc7
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1400.633 ; gain = 74.445
|
||||
Post Restoration Checksum: NetGraph: acd0c6a6 NumContArr: a07f621 Constraints: 0 Timing: 0
|
||||
|
||||
Phase 2 Router Initialization
|
||||
|
||||
Phase 2.1 Create Timer
|
||||
Phase 2.1 Create Timer | Checksum: b6d8bcc7
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1424.875 ; gain = 98.688
|
||||
|
||||
Phase 2.2 Fix Topology Constraints
|
||||
Phase 2.2 Fix Topology Constraints | Checksum: b6d8bcc7
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1430.887 ; gain = 104.699
|
||||
|
||||
Phase 2.3 Pre Route Cleanup
|
||||
Phase 2.3 Pre Route Cleanup | Checksum: b6d8bcc7
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1430.887 ; gain = 104.699
|
||||
Number of Nodes with overlaps = 0
|
||||
|
||||
Phase 2.4 Update Timing
|
||||
Phase 2.4 Update Timing | Checksum: 1c88f2ffd
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1433.641 ; gain = 107.453
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.958 | TNS=0.000 | WHS=-0.276 | THS=-3.718 |
|
||||
|
||||
Phase 2 Router Initialization | Checksum: 10a6ee9df
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1433.641 ; gain = 107.453
|
||||
|
||||
Phase 3 Initial Routing
|
||||
Phase 3 Initial Routing | Checksum: 17776be02
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1433.641 ; gain = 107.453
|
||||
|
||||
Phase 4 Rip-up And Reroute
|
||||
|
||||
Phase 4.1 Global Iteration 0
|
||||
Number of Nodes with overlaps = 4
|
||||
Number of Nodes with overlaps = 0
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=36.113 | TNS=0.000 | WHS=N/A | THS=N/A |
|
||||
|
||||
Phase 4.1 Global Iteration 0 | Checksum: 19eac515a
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.641 ; gain = 107.453
|
||||
Phase 4 Rip-up And Reroute | Checksum: 19eac515a
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.641 ; gain = 107.453
|
||||
|
||||
Phase 5 Delay and Skew Optimization
|
||||
|
||||
Phase 5.1 Delay CleanUp
|
||||
Phase 5.1 Delay CleanUp | Checksum: 19eac515a
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.641 ; gain = 107.453
|
||||
|
||||
Phase 5.2 Clock Skew Optimization
|
||||
Phase 5.2 Clock Skew Optimization | Checksum: 19eac515a
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.641 ; gain = 107.453
|
||||
Phase 5 Delay and Skew Optimization | Checksum: 19eac515a
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.641 ; gain = 107.453
|
||||
|
||||
Phase 6 Post Hold Fix
|
||||
|
||||
Phase 6.1 Hold Fix Iter
|
||||
|
||||
Phase 6.1.1 Update Timing
|
||||
Phase 6.1.1 Update Timing | Checksum: 219991e28
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.641 ; gain = 107.453
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=36.266 | TNS=0.000 | WHS=0.076 | THS=0.000 |
|
||||
|
||||
Phase 6.1 Hold Fix Iter | Checksum: 219991e28
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.641 ; gain = 107.453
|
||||
Phase 6 Post Hold Fix | Checksum: 219991e28
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.641 ; gain = 107.453
|
||||
|
||||
Phase 7 Route finalize
|
||||
|
||||
Router Utilization Summary
|
||||
Global Vertical Routing Utilization = 0.00900901 %
|
||||
Global Horizontal Routing Utilization = 0.00344669 %
|
||||
Routable Net Status*
|
||||
*Does not include unroutable nets such as driverless and loadless.
|
||||
Run report_route_status for detailed report.
|
||||
Number of Failed Nets = 0
|
||||
Number of Unrouted Nets = 0
|
||||
Number of Partially Routed Nets = 0
|
||||
Number of Node Overlaps = 0
|
||||
|
||||
Phase 7 Route finalize | Checksum: 1f6edf796
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.641 ; gain = 107.453
|
||||
|
||||
Phase 8 Verifying routed nets
|
||||
|
||||
Verification completed successfully
|
||||
Phase 8 Verifying routed nets | Checksum: 1f6edf796
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1435.129 ; gain = 108.941
|
||||
|
||||
Phase 9 Depositing Routes
|
||||
Phase 9 Depositing Routes | Checksum: 1ba53fff2
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1435.129 ; gain = 108.941
|
||||
|
||||
Phase 10 Post Router Timing
|
||||
INFO: [Route 35-57] Estimated Timing Summary | WNS=36.266 | TNS=0.000 | WHS=0.076 | THS=0.000 |
|
||||
|
||||
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
|
||||
Phase 10 Post Router Timing | Checksum: 1ba53fff2
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1435.129 ; gain = 108.941
|
||||
INFO: [Route 35-16] Router Completed Successfully
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1435.129 ; gain = 108.941
|
||||
|
||||
Routing Is Done.
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
74 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
route_design completed successfully
|
||||
route_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:22 . Memory (MB): peak = 1435.129 ; gain = 109.348
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1435.129 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1435.129 ; gain = 0.000
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.059 . Memory (MB): peak = 1435.129 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
|
||||
Command: report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt.
|
||||
report_drc completed successfully
|
||||
INFO: [runtcl-4] Executing : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
|
||||
Command: report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [DRC 23-133] Running Methodology with 2 threads
|
||||
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt.
|
||||
report_methodology completed successfully
|
||||
INFO: [runtcl-4] Executing : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
|
||||
Command: report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Running Vector-less Activity Propagation...
|
||||
|
||||
Finished Running Vector-less Activity Propagation
|
||||
86 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
report_power completed successfully
|
||||
INFO: [runtcl-4] Executing : report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb
|
||||
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
INFO: [runtcl-4] Executing : report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt
|
||||
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
|
||||
INFO: [runtcl-4] Executing : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt
|
||||
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
INFO: [Common 17-206] Exiting Vivado at Tue Nov 30 12:21:30 2021...
|
||||
@ -1,530 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Tue Nov 30 12:26:23 2021
|
||||
# Process ID: 13936
|
||||
# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1
|
||||
# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace
|
||||
# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi
|
||||
# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source VGA_top.tcl -notrace
|
||||
Command: link_design -top VGA_top -part xc7z010clg400-1
|
||||
Design is defaulting to srcset: sources_1
|
||||
Design is defaulting to constrset: constrs_1
|
||||
INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.dcp' for cell 'U0'
|
||||
INFO: [Netlist 29-17] Analyzing 3 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-479] Netlist was created with Vivado 2018.3
|
||||
INFO: [Device 21-403] Loading part xc7z010clg400-1
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
|
||||
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
|
||||
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
|
||||
INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
|
||||
get_clocks: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1223.945 ; gain = 534.242
|
||||
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
|
||||
Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
|
||||
Finished Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1223.945 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
link_design completed successfully
|
||||
link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:16 . Memory (MB): peak = 1223.945 ; gain = 861.488
|
||||
Command: opt_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
Running DRC as a precondition to command opt_design
|
||||
|
||||
Starting DRC Task
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Project 1-461] DRC finished with 0 Errors
|
||||
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.505 . Memory (MB): peak = 1223.945 ; gain = 0.000
|
||||
|
||||
Starting Cache Timing Information Task
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [Timing 38-2] Deriving generated clocks
|
||||
Ending Cache Timing Information Task | Checksum: 123818214
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1240.480 ; gain = 16.535
|
||||
|
||||
Starting Logic Optimization Task
|
||||
|
||||
Phase 1 Retarget
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Opt 31-49] Retargeted 0 cell(s).
|
||||
Phase 1 Retarget | Checksum: 123818214
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
|
||||
INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
||||
|
||||
Phase 2 Constant propagation
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Phase 2 Constant propagation | Checksum: 123818214
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
|
||||
|
||||
Phase 3 Sweep
|
||||
Phase 3 Sweep | Checksum: 126eab858
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
|
||||
|
||||
Phase 4 BUFG optimization
|
||||
INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG
|
||||
INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets
|
||||
Phase 4 BUFG optimization | Checksum: 12a935bc2
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
|
||||
|
||||
Phase 5 Shift Register Optimization
|
||||
Phase 5 Shift Register Optimization | Checksum: 187d22a05
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.025 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
|
||||
|
||||
Phase 6 Post Processing Netlist
|
||||
Phase 6 Post Processing Netlist | Checksum: 1eadce572
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.026 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
|
||||
Opt_design Change Summary
|
||||
=========================
|
||||
|
||||
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Retarget | 0 | 0 | 1 |
|
||||
| Constant propagation | 0 | 0 | 0 |
|
||||
| Sweep | 0 | 0 | 0 |
|
||||
| BUFG optimization | 0 | 0 | 0 |
|
||||
| Shift Register Optimization | 0 | 0 | 0 |
|
||||
| Post Processing Netlist | 0 | 0 | 0 |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
Starting Connectivity Check Task
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
Ending Logic Optimization Task | Checksum: 1626ce552
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
|
||||
Starting Power Optimization Task
|
||||
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
|
||||
Ending Power Optimization Task | Checksum: 1626ce552
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
|
||||
Starting Final Cleanup Task
|
||||
Ending Final Cleanup Task | Checksum: 1626ce552
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
|
||||
Starting Netlist Obfuscation Task
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
Ending Netlist Obfuscation Task | Checksum: 1626ce552
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
opt_design completed successfully
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
|
||||
Command: report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt.
|
||||
report_drc completed successfully
|
||||
Command: place_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
Running DRC as a precondition to command place_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Starting Placer Task
|
||||
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
|
||||
|
||||
Phase 1 Placer Initialization
|
||||
|
||||
Phase 1.1 Placer Initialization Netlist Sorting
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 11a18955b
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: b93ed54f
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.242 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
|
||||
Phase 1.3 Build Placer Netlist Model
|
||||
Phase 1.3 Build Placer Netlist Model | Checksum: 188d76266
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.297 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
|
||||
Phase 1.4 Constrain Clocks/Macros
|
||||
Phase 1.4 Constrain Clocks/Macros | Checksum: 188d76266
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.298 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
Phase 1 Placer Initialization | Checksum: 188d76266
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.299 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
|
||||
Phase 2 Global Placement
|
||||
|
||||
Phase 2.1 Floorplanning
|
||||
Phase 2.1 Floorplanning | Checksum: 18a35186d
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.334 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
|
||||
Phase 2.2 Physical Synthesis In Placer
|
||||
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
|
||||
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
|
||||
INFO: [Physopt 32-949] No candidate nets found for HD net replication
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
|
||||
Summary of Physical Synthesis Optimizations
|
||||
============================================
|
||||
|
||||
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 |
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Phase 2.2 Physical Synthesis In Placer | Checksum: 137f00f39
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.789 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
Phase 2 Global Placement | Checksum: 1432572bb
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.799 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
|
||||
Phase 3 Detail Placement
|
||||
|
||||
Phase 3.1 Commit Multi Column Macros
|
||||
Phase 3.1 Commit Multi Column Macros | Checksum: 1432572bb
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.800 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 111ffa250
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.850 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
|
||||
Phase 3.3 Area Swap Optimization
|
||||
Phase 3.3 Area Swap Optimization | Checksum: 14c2f5404
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.853 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
|
||||
Phase 3.4 Pipeline Register Optimization
|
||||
Phase 3.4 Pipeline Register Optimization | Checksum: 14c2f5404
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.853 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
|
||||
Phase 3.5 Small Shape Detail Placement
|
||||
Phase 3.5 Small Shape Detail Placement | Checksum: 8649c46f
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.901 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
|
||||
Phase 3.6 Re-assign LUT pins
|
||||
Phase 3.6 Re-assign LUT pins | Checksum: 1481f6ae7
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.904 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
|
||||
Phase 3.7 Pipeline Register Optimization
|
||||
Phase 3.7 Pipeline Register Optimization | Checksum: 1481f6ae7
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.905 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
Phase 3 Detail Placement | Checksum: 1481f6ae7
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.905 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
|
||||
Phase 4 Post Placement Optimization and Clean-Up
|
||||
|
||||
Phase 4.1 Post Commit Optimization
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
|
||||
Phase 4.1.1 Post Placement Optimization
|
||||
Post Placement Optimization Initialization | Checksum: 1e8de705c
|
||||
|
||||
Phase 4.1.1.1 BUFG Insertion
|
||||
INFO: [Place 46-46] BUFG insertion identified 0 candidate nets, 0 success, 0 bufg driver replicated, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason
|
||||
Phase 4.1.1.1 BUFG Insertion | Checksum: 1e8de705c
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.938 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
INFO: [Place 30-746] Post Placement Timing Summary WNS=35.347. For the most accurate timing information please run report_timing.
|
||||
Phase 4.1.1 Post Placement Optimization | Checksum: 20dc81c88
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.938 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
Phase 4.1 Post Commit Optimization | Checksum: 20dc81c88
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.939 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
|
||||
Phase 4.2 Post Placement Cleanup
|
||||
Phase 4.2 Post Placement Cleanup | Checksum: 20dc81c88
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.940 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
|
||||
Phase 4.3 Placer Reporting
|
||||
Phase 4.3 Placer Reporting | Checksum: 20dc81c88
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.941 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
|
||||
Phase 4.4 Final Placement Cleanup
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
Phase 4.4 Final Placement Cleanup | Checksum: 1e1df3375
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.943 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1e1df3375
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.943 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
Ending Placer Task | Checksum: 13b3db9c6
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.945 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
57 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
place_design completed successfully
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1321.344 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_io -file VGA_top_io_placed.rpt
|
||||
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1323.125 ; gain = 0.000
|
||||
INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb
|
||||
INFO: [runtcl-4] Executing : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt
|
||||
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1323.125 ; gain = 0.000
|
||||
Command: route_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
Running DRC as a precondition to command route_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
|
||||
Starting Routing Task
|
||||
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
|
||||
Checksum: PlaceDB: c37a5850 ConstDB: 0 ShapeSum: 77c36176 RouteDB: 0
|
||||
|
||||
Phase 1 Build RT Design
|
||||
Phase 1 Build RT Design | Checksum: bd1c2272
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1396.336 ; gain = 73.211
|
||||
Post Restoration Checksum: NetGraph: bbeff794 NumContArr: 12c2ade Constraints: 0 Timing: 0
|
||||
|
||||
Phase 2 Router Initialization
|
||||
|
||||
Phase 2.1 Create Timer
|
||||
Phase 2.1 Create Timer | Checksum: bd1c2272
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1420.555 ; gain = 97.430
|
||||
|
||||
Phase 2.2 Fix Topology Constraints
|
||||
Phase 2.2 Fix Topology Constraints | Checksum: bd1c2272
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1426.578 ; gain = 103.453
|
||||
|
||||
Phase 2.3 Pre Route Cleanup
|
||||
Phase 2.3 Pre Route Cleanup | Checksum: bd1c2272
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1426.578 ; gain = 103.453
|
||||
Number of Nodes with overlaps = 0
|
||||
|
||||
Phase 2.4 Update Timing
|
||||
Phase 2.4 Update Timing | Checksum: 19cf4eeba
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1429.270 ; gain = 106.145
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.290 | TNS=0.000 | WHS=-0.256 | THS=-3.320 |
|
||||
|
||||
Phase 2 Router Initialization | Checksum: 1eb51a031
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1429.270 ; gain = 106.145
|
||||
|
||||
Phase 3 Initial Routing
|
||||
Phase 3 Initial Routing | Checksum: 12fb8703e
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1429.473 ; gain = 106.348
|
||||
|
||||
Phase 4 Rip-up And Reroute
|
||||
|
||||
Phase 4.1 Global Iteration 0
|
||||
Number of Nodes with overlaps = 4
|
||||
Number of Nodes with overlaps = 0
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.101 | TNS=0.000 | WHS=N/A | THS=N/A |
|
||||
|
||||
Phase 4.1 Global Iteration 0 | Checksum: eab409dc
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1429.477 ; gain = 106.352
|
||||
Phase 4 Rip-up And Reroute | Checksum: eab409dc
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1429.477 ; gain = 106.352
|
||||
|
||||
Phase 5 Delay and Skew Optimization
|
||||
|
||||
Phase 5.1 Delay CleanUp
|
||||
|
||||
Phase 5.1.1 Update Timing
|
||||
Phase 5.1.1 Update Timing | Checksum: eab409dc
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1429.477 ; gain = 106.352
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.254 | TNS=0.000 | WHS=N/A | THS=N/A |
|
||||
|
||||
Phase 5.1 Delay CleanUp | Checksum: eab409dc
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1429.477 ; gain = 106.352
|
||||
|
||||
Phase 5.2 Clock Skew Optimization
|
||||
Phase 5.2 Clock Skew Optimization | Checksum: eab409dc
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1429.477 ; gain = 106.352
|
||||
Phase 5 Delay and Skew Optimization | Checksum: eab409dc
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1429.477 ; gain = 106.352
|
||||
|
||||
Phase 6 Post Hold Fix
|
||||
|
||||
Phase 6.1 Hold Fix Iter
|
||||
|
||||
Phase 6.1.1 Update Timing
|
||||
Phase 6.1.1 Update Timing | Checksum: 133414f2c
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1429.477 ; gain = 106.352
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.254 | TNS=0.000 | WHS=0.074 | THS=0.000 |
|
||||
|
||||
Phase 6.1 Hold Fix Iter | Checksum: fbd5f750
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1429.477 ; gain = 106.352
|
||||
Phase 6 Post Hold Fix | Checksum: fbd5f750
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1429.477 ; gain = 106.352
|
||||
|
||||
Phase 7 Route finalize
|
||||
|
||||
Router Utilization Summary
|
||||
Global Vertical Routing Utilization = 0.0239302 %
|
||||
Global Horizontal Routing Utilization = 0.00919118 %
|
||||
Routable Net Status*
|
||||
*Does not include unroutable nets such as driverless and loadless.
|
||||
Run report_route_status for detailed report.
|
||||
Number of Failed Nets = 0
|
||||
Number of Unrouted Nets = 0
|
||||
Number of Partially Routed Nets = 0
|
||||
Number of Node Overlaps = 0
|
||||
|
||||
Phase 7 Route finalize | Checksum: 1a2bd3c5a
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1429.477 ; gain = 106.352
|
||||
|
||||
Phase 8 Verifying routed nets
|
||||
|
||||
Verification completed successfully
|
||||
Phase 8 Verifying routed nets | Checksum: 1a2bd3c5a
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1431.516 ; gain = 108.391
|
||||
|
||||
Phase 9 Depositing Routes
|
||||
Phase 9 Depositing Routes | Checksum: 239975ea0
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1431.516 ; gain = 108.391
|
||||
|
||||
Phase 10 Post Router Timing
|
||||
INFO: [Route 35-57] Estimated Timing Summary | WNS=35.254 | TNS=0.000 | WHS=0.074 | THS=0.000 |
|
||||
|
||||
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
|
||||
Phase 10 Post Router Timing | Checksum: 239975ea0
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1431.516 ; gain = 108.391
|
||||
INFO: [Route 35-16] Router Completed Successfully
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1431.516 ; gain = 108.391
|
||||
|
||||
Routing Is Done.
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
75 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
route_design completed successfully
|
||||
route_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 1431.516 ; gain = 108.391
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1431.516 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1432.102 ; gain = 0.586
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1432.102 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
|
||||
Command: report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt.
|
||||
report_drc completed successfully
|
||||
INFO: [runtcl-4] Executing : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
|
||||
Command: report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [DRC 23-133] Running Methodology with 2 threads
|
||||
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt.
|
||||
report_methodology completed successfully
|
||||
INFO: [runtcl-4] Executing : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
|
||||
Command: report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Running Vector-less Activity Propagation...
|
||||
|
||||
Finished Running Vector-less Activity Propagation
|
||||
87 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
report_power completed successfully
|
||||
INFO: [runtcl-4] Executing : report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb
|
||||
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
INFO: [runtcl-4] Executing : report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt
|
||||
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
|
||||
INFO: [runtcl-4] Executing : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt
|
||||
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
INFO: [Common 17-206] Exiting Vivado at Tue Nov 30 12:27:12 2021...
|
||||
@ -1,545 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Tue Nov 23 10:29:07 2021
|
||||
# Process ID: 14844
|
||||
# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1
|
||||
# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace
|
||||
# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi
|
||||
# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source VGA_top.tcl -notrace
|
||||
Command: link_design -top VGA_top -part xc7z010clg400-1
|
||||
Design is defaulting to srcset: sources_1
|
||||
Design is defaulting to constrset: constrs_1
|
||||
INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.dcp' for cell 'U0'
|
||||
INFO: [Netlist 29-17] Analyzing 11 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-479] Netlist was created with Vivado 2018.3
|
||||
INFO: [Device 21-403] Loading part xc7z010clg400-1
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
|
||||
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
|
||||
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
|
||||
INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
|
||||
get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1244.230 ; gain = 551.977
|
||||
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
|
||||
Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
|
||||
Finished Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1244.230 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
link_design completed successfully
|
||||
link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:24 . Memory (MB): peak = 1244.230 ; gain = 880.109
|
||||
Command: opt_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
Running DRC as a precondition to command opt_design
|
||||
|
||||
Starting DRC Task
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Project 1-461] DRC finished with 0 Errors
|
||||
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.506 . Memory (MB): peak = 1244.230 ; gain = 0.000
|
||||
|
||||
Starting Cache Timing Information Task
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [Timing 38-2] Deriving generated clocks
|
||||
Ending Cache Timing Information Task | Checksum: b8ea7a4e
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1262.832 ; gain = 18.602
|
||||
|
||||
Starting Logic Optimization Task
|
||||
|
||||
Phase 1 Retarget
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Opt 31-49] Retargeted 0 cell(s).
|
||||
Phase 1 Retarget | Checksum: b8ea7a4e
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
|
||||
INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
||||
|
||||
Phase 2 Constant propagation
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Phase 2 Constant propagation | Checksum: b8ea7a4e
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
|
||||
|
||||
Phase 3 Sweep
|
||||
Phase 3 Sweep | Checksum: 69d8ab95
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
|
||||
|
||||
Phase 4 BUFG optimization
|
||||
INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG
|
||||
INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets
|
||||
Phase 4 BUFG optimization | Checksum: 13bee9dc1
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
|
||||
|
||||
Phase 5 Shift Register Optimization
|
||||
Phase 5 Shift Register Optimization | Checksum: 1a59d5459
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
|
||||
|
||||
Phase 6 Post Processing Netlist
|
||||
Phase 6 Post Processing Netlist | Checksum: 14a40c514
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
|
||||
Opt_design Change Summary
|
||||
=========================
|
||||
|
||||
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Retarget | 0 | 0 | 1 |
|
||||
| Constant propagation | 0 | 0 | 0 |
|
||||
| Sweep | 0 | 0 | 0 |
|
||||
| BUFG optimization | 0 | 0 | 0 |
|
||||
| Shift Register Optimization | 0 | 0 | 0 |
|
||||
| Post Processing Netlist | 0 | 0 | 0 |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
Starting Connectivity Check Task
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
Ending Logic Optimization Task | Checksum: 14dbbd0bc
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
|
||||
Starting Power Optimization Task
|
||||
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
|
||||
Ending Power Optimization Task | Checksum: 14dbbd0bc
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
|
||||
Starting Final Cleanup Task
|
||||
Ending Final Cleanup Task | Checksum: 14dbbd0bc
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
|
||||
Starting Netlist Obfuscation Task
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
Ending Netlist Obfuscation Task | Checksum: 14dbbd0bc
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
opt_design completed successfully
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
|
||||
Command: report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt.
|
||||
report_drc completed successfully
|
||||
Command: place_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
Running DRC as a precondition to command place_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Starting Placer Task
|
||||
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
|
||||
|
||||
Phase 1 Placer Initialization
|
||||
|
||||
Phase 1.1 Placer Initialization Netlist Sorting
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fa6d7a79
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.
|
||||
|
||||
bouton_down_IBUF_inst (IBUF.O) is locked to IOB_X0Y1
|
||||
bouton_down_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y1
|
||||
Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin.
|
||||
WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.
|
||||
|
||||
bouton_right_IBUF_inst (IBUF.O) is locked to IOB_X0Y36
|
||||
bouton_right_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0
|
||||
Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin.
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 12622357c
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.285 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
|
||||
Phase 1.3 Build Placer Netlist Model
|
||||
Phase 1.3 Build Placer Netlist Model | Checksum: 1b3b55d5e
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.343 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
|
||||
Phase 1.4 Constrain Clocks/Macros
|
||||
Phase 1.4 Constrain Clocks/Macros | Checksum: 1b3b55d5e
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.345 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
Phase 1 Placer Initialization | Checksum: 1b3b55d5e
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.345 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
|
||||
Phase 2 Global Placement
|
||||
|
||||
Phase 2.1 Floorplanning
|
||||
Phase 2.1 Floorplanning | Checksum: 1f34e0130
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.376 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
|
||||
Phase 2.2 Physical Synthesis In Placer
|
||||
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
|
||||
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
|
||||
INFO: [Physopt 32-949] No candidate nets found for HD net replication
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
|
||||
Summary of Physical Synthesis Optimizations
|
||||
============================================
|
||||
|
||||
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 |
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Phase 2.2 Physical Synthesis In Placer | Checksum: 1f822ab4a
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.886 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
Phase 2 Global Placement | Checksum: 17fde1b87
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.897 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
|
||||
Phase 3 Detail Placement
|
||||
|
||||
Phase 3.1 Commit Multi Column Macros
|
||||
Phase 3.1 Commit Multi Column Macros | Checksum: 17fde1b87
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.898 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 258919723
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.931 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
|
||||
Phase 3.3 Area Swap Optimization
|
||||
Phase 3.3 Area Swap Optimization | Checksum: 1af65d909
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.933 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
|
||||
Phase 3.4 Pipeline Register Optimization
|
||||
Phase 3.4 Pipeline Register Optimization | Checksum: 245deb5d9
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.934 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
|
||||
Phase 3.5 Small Shape Detail Placement
|
||||
Phase 3.5 Small Shape Detail Placement | Checksum: 1dab8f54b
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.998 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
|
||||
Phase 3.6 Re-assign LUT pins
|
||||
Phase 3.6 Re-assign LUT pins | Checksum: 1e1eee966
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
|
||||
Phase 3.7 Pipeline Register Optimization
|
||||
Phase 3.7 Pipeline Register Optimization | Checksum: f76e0896
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
Phase 3 Detail Placement | Checksum: f76e0896
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
|
||||
Phase 4 Post Placement Optimization and Clean-Up
|
||||
|
||||
Phase 4.1 Post Commit Optimization
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
|
||||
Phase 4.1.1 Post Placement Optimization
|
||||
Post Placement Optimization Initialization | Checksum: 13e7bd2c2
|
||||
|
||||
Phase 4.1.1.1 BUFG Insertion
|
||||
INFO: [Place 46-46] BUFG insertion identified 0 candidate nets, 0 success, 0 bufg driver replicated, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason
|
||||
Phase 4.1.1.1 BUFG Insertion | Checksum: 13e7bd2c2
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
INFO: [Place 30-746] Post Placement Timing Summary WNS=35.645. For the most accurate timing information please run report_timing.
|
||||
Phase 4.1.1 Post Placement Optimization | Checksum: 15c183492
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
Phase 4.1 Post Commit Optimization | Checksum: 15c183492
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
|
||||
Phase 4.2 Post Placement Cleanup
|
||||
Phase 4.2 Post Placement Cleanup | Checksum: 15c183492
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
|
||||
Phase 4.3 Placer Reporting
|
||||
Phase 4.3 Placer Reporting | Checksum: 15c183492
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
|
||||
Phase 4.4 Final Placement Cleanup
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
Phase 4.4 Final Placement Cleanup | Checksum: 17d5ce04d
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 17d5ce04d
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
Ending Placer Task | Checksum: d443f812
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
57 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
place_design completed successfully
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.047 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_io -file VGA_top_io_placed.rpt
|
||||
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb
|
||||
INFO: [runtcl-4] Executing : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt
|
||||
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1344.859 ; gain = 0.000
|
||||
Command: route_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
Running DRC as a precondition to command route_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG.
|
||||
Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin.
|
||||
This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.
|
||||
|
||||
bouton_down_IBUF_inst (IBUF.O) is locked to IOB_X0Y1
|
||||
bouton_down_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y1
|
||||
WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG.
|
||||
Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin.
|
||||
This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.
|
||||
|
||||
bouton_right_IBUF_inst (IBUF.O) is locked to IOB_X0Y36
|
||||
bouton_right_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 2 Warnings
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
|
||||
Starting Routing Task
|
||||
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
|
||||
Checksum: PlaceDB: 52480e80 ConstDB: 0 ShapeSum: 81fbe992 RouteDB: 0
|
||||
|
||||
Phase 1 Build RT Design
|
||||
Phase 1 Build RT Design | Checksum: fee31c87
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1413.766 ; gain = 68.906
|
||||
Post Restoration Checksum: NetGraph: e323ff66 NumContArr: 1bbf1d21 Constraints: 0 Timing: 0
|
||||
|
||||
Phase 2 Router Initialization
|
||||
|
||||
Phase 2.1 Create Timer
|
||||
Phase 2.1 Create Timer | Checksum: fee31c87
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1444.059 ; gain = 99.199
|
||||
|
||||
Phase 2.2 Fix Topology Constraints
|
||||
Phase 2.2 Fix Topology Constraints | Checksum: fee31c87
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1450.090 ; gain = 105.230
|
||||
|
||||
Phase 2.3 Pre Route Cleanup
|
||||
Phase 2.3 Pre Route Cleanup | Checksum: fee31c87
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1450.090 ; gain = 105.230
|
||||
Number of Nodes with overlaps = 0
|
||||
|
||||
Phase 2.4 Update Timing
|
||||
Phase 2.4 Update Timing | Checksum: 1441c14dd
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1454.070 ; gain = 109.211
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.769 | TNS=0.000 | WHS=-0.258 | THS=-3.023 |
|
||||
|
||||
Phase 2 Router Initialization | Checksum: 173a347ed
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1454.070 ; gain = 109.211
|
||||
|
||||
Phase 3 Initial Routing
|
||||
Phase 3 Initial Routing | Checksum: 205eb8b74
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1454.996 ; gain = 110.137
|
||||
|
||||
Phase 4 Rip-up And Reroute
|
||||
|
||||
Phase 4.1 Global Iteration 0
|
||||
Number of Nodes with overlaps = 17
|
||||
Number of Nodes with overlaps = 0
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.132 | TNS=0.000 | WHS=N/A | THS=N/A |
|
||||
|
||||
Phase 4.1 Global Iteration 0 | Checksum: 2843d0f71
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1454.996 ; gain = 110.137
|
||||
Phase 4 Rip-up And Reroute | Checksum: 2843d0f71
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1454.996 ; gain = 110.137
|
||||
|
||||
Phase 5 Delay and Skew Optimization
|
||||
|
||||
Phase 5.1 Delay CleanUp
|
||||
Phase 5.1 Delay CleanUp | Checksum: 2843d0f71
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1454.996 ; gain = 110.137
|
||||
|
||||
Phase 5.2 Clock Skew Optimization
|
||||
Phase 5.2 Clock Skew Optimization | Checksum: 2843d0f71
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1454.996 ; gain = 110.137
|
||||
Phase 5 Delay and Skew Optimization | Checksum: 2843d0f71
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1454.996 ; gain = 110.137
|
||||
|
||||
Phase 6 Post Hold Fix
|
||||
|
||||
Phase 6.1 Hold Fix Iter
|
||||
|
||||
Phase 6.1.1 Update Timing
|
||||
Phase 6.1.1 Update Timing | Checksum: 1adede088
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1454.996 ; gain = 110.137
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.132 | TNS=0.000 | WHS=0.069 | THS=0.000 |
|
||||
|
||||
Phase 6.1 Hold Fix Iter | Checksum: 1adede088
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1454.996 ; gain = 110.137
|
||||
Phase 6 Post Hold Fix | Checksum: 1adede088
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1454.996 ; gain = 110.137
|
||||
|
||||
Phase 7 Route finalize
|
||||
|
||||
Router Utilization Summary
|
||||
Global Vertical Routing Utilization = 0.0615146 %
|
||||
Global Horizontal Routing Utilization = 0.0558364 %
|
||||
Routable Net Status*
|
||||
*Does not include unroutable nets such as driverless and loadless.
|
||||
Run report_route_status for detailed report.
|
||||
Number of Failed Nets = 0
|
||||
Number of Unrouted Nets = 0
|
||||
Number of Partially Routed Nets = 0
|
||||
Number of Node Overlaps = 0
|
||||
|
||||
Phase 7 Route finalize | Checksum: 2005f65b4
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1454.996 ; gain = 110.137
|
||||
|
||||
Phase 8 Verifying routed nets
|
||||
|
||||
Verification completed successfully
|
||||
Phase 8 Verifying routed nets | Checksum: 2005f65b4
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1456.047 ; gain = 111.188
|
||||
|
||||
Phase 9 Depositing Routes
|
||||
Phase 9 Depositing Routes | Checksum: 18ba5fe80
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1456.047 ; gain = 111.188
|
||||
|
||||
Phase 10 Post Router Timing
|
||||
INFO: [Route 35-57] Estimated Timing Summary | WNS=35.132 | TNS=0.000 | WHS=0.069 | THS=0.000 |
|
||||
|
||||
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
|
||||
Phase 10 Post Router Timing | Checksum: 18ba5fe80
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1456.047 ; gain = 111.188
|
||||
INFO: [Route 35-16] Router Completed Successfully
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1456.047 ; gain = 111.188
|
||||
|
||||
Routing Is Done.
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
74 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
route_design completed successfully
|
||||
route_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1456.047 ; gain = 111.188
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1456.047 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.046 . Memory (MB): peak = 1456.453 ; gain = 0.406
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1456.453 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
|
||||
Command: report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt.
|
||||
report_drc completed successfully
|
||||
INFO: [runtcl-4] Executing : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
|
||||
Command: report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [DRC 23-133] Running Methodology with 2 threads
|
||||
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt.
|
||||
report_methodology completed successfully
|
||||
INFO: [runtcl-4] Executing : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
|
||||
Command: report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Running Vector-less Activity Propagation...
|
||||
|
||||
Finished Running Vector-less Activity Propagation
|
||||
86 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
report_power completed successfully
|
||||
INFO: [runtcl-4] Executing : report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb
|
||||
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
INFO: [runtcl-4] Executing : report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt
|
||||
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
|
||||
INFO: [runtcl-4] Executing : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt
|
||||
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
INFO: [Common 17-206] Exiting Vivado at Tue Nov 23 10:29:55 2021...
|
||||
@ -1,523 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Tue Nov 30 12:16:55 2021
|
||||
# Process ID: 15112
|
||||
# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1
|
||||
# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace
|
||||
# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi
|
||||
# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source VGA_top.tcl -notrace
|
||||
Command: link_design -top VGA_top -part xc7z010clg400-1
|
||||
Design is defaulting to srcset: sources_1
|
||||
Design is defaulting to constrset: constrs_1
|
||||
INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.dcp' for cell 'U0'
|
||||
INFO: [Netlist 29-17] Analyzing 3 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-479] Netlist was created with Vivado 2018.3
|
||||
INFO: [Device 21-403] Loading part xc7z010clg400-1
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
|
||||
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
|
||||
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
|
||||
INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
|
||||
get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1224.488 ; gain = 533.477
|
||||
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
|
||||
Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
|
||||
Finished Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1224.488 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
link_design completed successfully
|
||||
link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:16 . Memory (MB): peak = 1224.488 ; gain = 861.793
|
||||
Command: opt_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
Running DRC as a precondition to command opt_design
|
||||
|
||||
Starting DRC Task
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Project 1-461] DRC finished with 0 Errors
|
||||
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.505 . Memory (MB): peak = 1224.488 ; gain = 0.000
|
||||
|
||||
Starting Cache Timing Information Task
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [Timing 38-2] Deriving generated clocks
|
||||
Ending Cache Timing Information Task | Checksum: dc2ced6f
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1241.574 ; gain = 17.086
|
||||
|
||||
Starting Logic Optimization Task
|
||||
|
||||
Phase 1 Retarget
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Opt 31-49] Retargeted 0 cell(s).
|
||||
Phase 1 Retarget | Checksum: dc2ced6f
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
|
||||
INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
||||
|
||||
Phase 2 Constant propagation
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Phase 2 Constant propagation | Checksum: dc2ced6f
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
|
||||
|
||||
Phase 3 Sweep
|
||||
Phase 3 Sweep | Checksum: 19e1c8f17
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
|
||||
|
||||
Phase 4 BUFG optimization
|
||||
INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG
|
||||
INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets
|
||||
Phase 4 BUFG optimization | Checksum: c943f809
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
|
||||
|
||||
Phase 5 Shift Register Optimization
|
||||
Phase 5 Shift Register Optimization | Checksum: ba2b01e3
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
|
||||
|
||||
Phase 6 Post Processing Netlist
|
||||
Phase 6 Post Processing Netlist | Checksum: b57bee7a
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
|
||||
Opt_design Change Summary
|
||||
=========================
|
||||
|
||||
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Retarget | 0 | 0 | 1 |
|
||||
| Constant propagation | 0 | 0 | 0 |
|
||||
| Sweep | 0 | 0 | 0 |
|
||||
| BUFG optimization | 0 | 0 | 0 |
|
||||
| Shift Register Optimization | 0 | 0 | 0 |
|
||||
| Post Processing Netlist | 0 | 0 | 0 |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
Starting Connectivity Check Task
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
Ending Logic Optimization Task | Checksum: 13b7a3fb2
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
|
||||
Starting Power Optimization Task
|
||||
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
|
||||
Ending Power Optimization Task | Checksum: 13b7a3fb2
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
|
||||
Starting Final Cleanup Task
|
||||
Ending Final Cleanup Task | Checksum: 13b7a3fb2
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
|
||||
Starting Netlist Obfuscation Task
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
Ending Netlist Obfuscation Task | Checksum: 13b7a3fb2
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
opt_design completed successfully
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
|
||||
Command: report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt.
|
||||
report_drc completed successfully
|
||||
Command: place_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
Running DRC as a precondition to command place_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Starting Placer Task
|
||||
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
|
||||
|
||||
Phase 1 Placer Initialization
|
||||
|
||||
Phase 1.1 Placer Initialization Netlist Sorting
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 67b44082
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 14d1cdeaf
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.242 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
|
||||
Phase 1.3 Build Placer Netlist Model
|
||||
Phase 1.3 Build Placer Netlist Model | Checksum: 1bfc53c93
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.307 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
|
||||
Phase 1.4 Constrain Clocks/Macros
|
||||
Phase 1.4 Constrain Clocks/Macros | Checksum: 1bfc53c93
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.308 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
Phase 1 Placer Initialization | Checksum: 1bfc53c93
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.309 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
|
||||
Phase 2 Global Placement
|
||||
|
||||
Phase 2.1 Floorplanning
|
||||
Phase 2.1 Floorplanning | Checksum: 152ddf35d
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.349 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
|
||||
Phase 2.2 Physical Synthesis In Placer
|
||||
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
|
||||
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
|
||||
INFO: [Physopt 32-949] No candidate nets found for HD net replication
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
|
||||
Summary of Physical Synthesis Optimizations
|
||||
============================================
|
||||
|
||||
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 |
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Phase 2.2 Physical Synthesis In Placer | Checksum: 166883134
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.854 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
Phase 2 Global Placement | Checksum: 1ea5262ce
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.863 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
|
||||
Phase 3 Detail Placement
|
||||
|
||||
Phase 3.1 Commit Multi Column Macros
|
||||
Phase 3.1 Commit Multi Column Macros | Checksum: 1ea5262ce
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.864 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1350cd04a
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.906 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
|
||||
Phase 3.3 Area Swap Optimization
|
||||
Phase 3.3 Area Swap Optimization | Checksum: 1c8d9a95a
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.908 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
|
||||
Phase 3.4 Pipeline Register Optimization
|
||||
Phase 3.4 Pipeline Register Optimization | Checksum: 1c8d9a95a
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.908 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
|
||||
Phase 3.5 Small Shape Detail Placement
|
||||
Phase 3.5 Small Shape Detail Placement | Checksum: 236b118c7
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.965 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
|
||||
Phase 3.6 Re-assign LUT pins
|
||||
Phase 3.6 Re-assign LUT pins | Checksum: 182b978ad
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.968 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
|
||||
Phase 3.7 Pipeline Register Optimization
|
||||
Phase 3.7 Pipeline Register Optimization | Checksum: 182b978ad
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.968 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
Phase 3 Detail Placement | Checksum: 182b978ad
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.969 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
|
||||
Phase 4 Post Placement Optimization and Clean-Up
|
||||
|
||||
Phase 4.1 Post Commit Optimization
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
|
||||
Phase 4.1.1 Post Placement Optimization
|
||||
Post Placement Optimization Initialization | Checksum: c19cad15
|
||||
|
||||
Phase 4.1.1.1 BUFG Insertion
|
||||
INFO: [Place 46-46] BUFG insertion identified 0 candidate nets, 0 success, 0 bufg driver replicated, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason
|
||||
Phase 4.1.1.1 BUFG Insertion | Checksum: c19cad15
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.996 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
INFO: [Place 30-746] Post Placement Timing Summary WNS=36.030. For the most accurate timing information please run report_timing.
|
||||
Phase 4.1.1 Post Placement Optimization | Checksum: a4d8353e
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.997 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
Phase 4.1 Post Commit Optimization | Checksum: a4d8353e
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.997 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
|
||||
Phase 4.2 Post Placement Cleanup
|
||||
Phase 4.2 Post Placement Cleanup | Checksum: a4d8353e
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.999 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
|
||||
Phase 4.3 Placer Reporting
|
||||
Phase 4.3 Placer Reporting | Checksum: a4d8353e
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.999 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
|
||||
Phase 4.4 Final Placement Cleanup
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
Phase 4.4 Final Placement Cleanup | Checksum: 80d205c8
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 80d205c8
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
Ending Placer Task | Checksum: 362c66e8
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
57 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
place_design completed successfully
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_io -file VGA_top_io_placed.rpt
|
||||
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb
|
||||
INFO: [runtcl-4] Executing : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt
|
||||
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1325.754 ; gain = 0.000
|
||||
Command: route_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
Running DRC as a precondition to command route_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
|
||||
Starting Routing Task
|
||||
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
|
||||
Checksum: PlaceDB: 1579e8f6 ConstDB: 0 ShapeSum: 20b27df2 RouteDB: 0
|
||||
|
||||
Phase 1 Build RT Design
|
||||
Phase 1 Build RT Design | Checksum: b6d8bcc7
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1398.246 ; gain = 72.492
|
||||
Post Restoration Checksum: NetGraph: acd0c6a6 NumContArr: a07f621 Constraints: 0 Timing: 0
|
||||
|
||||
Phase 2 Router Initialization
|
||||
|
||||
Phase 2.1 Create Timer
|
||||
Phase 2.1 Create Timer | Checksum: b6d8bcc7
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1422.508 ; gain = 96.754
|
||||
|
||||
Phase 2.2 Fix Topology Constraints
|
||||
Phase 2.2 Fix Topology Constraints | Checksum: b6d8bcc7
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1428.512 ; gain = 102.758
|
||||
|
||||
Phase 2.3 Pre Route Cleanup
|
||||
Phase 2.3 Pre Route Cleanup | Checksum: b6d8bcc7
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1428.512 ; gain = 102.758
|
||||
Number of Nodes with overlaps = 0
|
||||
|
||||
Phase 2.4 Update Timing
|
||||
Phase 2.4 Update Timing | Checksum: 1c88f2ffd
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1431.293 ; gain = 105.539
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.958 | TNS=0.000 | WHS=-0.276 | THS=-3.718 |
|
||||
|
||||
Phase 2 Router Initialization | Checksum: 10a6ee9df
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1431.293 ; gain = 105.539
|
||||
|
||||
Phase 3 Initial Routing
|
||||
Phase 3 Initial Routing | Checksum: 17776be02
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1431.293 ; gain = 105.539
|
||||
|
||||
Phase 4 Rip-up And Reroute
|
||||
|
||||
Phase 4.1 Global Iteration 0
|
||||
Number of Nodes with overlaps = 4
|
||||
Number of Nodes with overlaps = 0
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=36.113 | TNS=0.000 | WHS=N/A | THS=N/A |
|
||||
|
||||
Phase 4.1 Global Iteration 0 | Checksum: 19eac515a
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1431.293 ; gain = 105.539
|
||||
Phase 4 Rip-up And Reroute | Checksum: 19eac515a
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1431.293 ; gain = 105.539
|
||||
|
||||
Phase 5 Delay and Skew Optimization
|
||||
|
||||
Phase 5.1 Delay CleanUp
|
||||
Phase 5.1 Delay CleanUp | Checksum: 19eac515a
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1431.293 ; gain = 105.539
|
||||
|
||||
Phase 5.2 Clock Skew Optimization
|
||||
Phase 5.2 Clock Skew Optimization | Checksum: 19eac515a
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1431.293 ; gain = 105.539
|
||||
Phase 5 Delay and Skew Optimization | Checksum: 19eac515a
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1431.293 ; gain = 105.539
|
||||
|
||||
Phase 6 Post Hold Fix
|
||||
|
||||
Phase 6.1 Hold Fix Iter
|
||||
|
||||
Phase 6.1.1 Update Timing
|
||||
Phase 6.1.1 Update Timing | Checksum: 219991e28
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1431.293 ; gain = 105.539
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=36.266 | TNS=0.000 | WHS=0.076 | THS=0.000 |
|
||||
|
||||
Phase 6.1 Hold Fix Iter | Checksum: 219991e28
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1431.293 ; gain = 105.539
|
||||
Phase 6 Post Hold Fix | Checksum: 219991e28
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1431.293 ; gain = 105.539
|
||||
|
||||
Phase 7 Route finalize
|
||||
|
||||
Router Utilization Summary
|
||||
Global Vertical Routing Utilization = 0.00900901 %
|
||||
Global Horizontal Routing Utilization = 0.00344669 %
|
||||
Routable Net Status*
|
||||
*Does not include unroutable nets such as driverless and loadless.
|
||||
Run report_route_status for detailed report.
|
||||
Number of Failed Nets = 0
|
||||
Number of Unrouted Nets = 0
|
||||
Number of Partially Routed Nets = 0
|
||||
Number of Node Overlaps = 0
|
||||
|
||||
Phase 7 Route finalize | Checksum: 1f6edf796
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1431.293 ; gain = 105.539
|
||||
|
||||
Phase 8 Verifying routed nets
|
||||
|
||||
Verification completed successfully
|
||||
Phase 8 Verifying routed nets | Checksum: 1f6edf796
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.059 ; gain = 107.305
|
||||
|
||||
Phase 9 Depositing Routes
|
||||
Phase 9 Depositing Routes | Checksum: 1ba53fff2
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.059 ; gain = 107.305
|
||||
|
||||
Phase 10 Post Router Timing
|
||||
INFO: [Route 35-57] Estimated Timing Summary | WNS=36.266 | TNS=0.000 | WHS=0.076 | THS=0.000 |
|
||||
|
||||
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
|
||||
Phase 10 Post Router Timing | Checksum: 1ba53fff2
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.059 ; gain = 107.305
|
||||
INFO: [Route 35-16] Router Completed Successfully
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.059 ; gain = 107.305
|
||||
|
||||
Routing Is Done.
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
74 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
route_design completed successfully
|
||||
route_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:22 . Memory (MB): peak = 1433.059 ; gain = 107.305
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1433.059 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1433.059 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1433.148 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
|
||||
Command: report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt.
|
||||
report_drc completed successfully
|
||||
INFO: [runtcl-4] Executing : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
|
||||
Command: report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [DRC 23-133] Running Methodology with 2 threads
|
||||
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt.
|
||||
report_methodology completed successfully
|
||||
INFO: [runtcl-4] Executing : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
|
||||
Command: report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Running Vector-less Activity Propagation...
|
||||
|
||||
Finished Running Vector-less Activity Propagation
|
||||
86 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
report_power completed successfully
|
||||
INFO: [runtcl-4] Executing : report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb
|
||||
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
INFO: [runtcl-4] Executing : report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt
|
||||
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
|
||||
INFO: [runtcl-4] Executing : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt
|
||||
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
INFO: [Common 17-206] Exiting Vivado at Tue Nov 30 12:17:44 2021...
|
||||
@ -1,523 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Tue Nov 30 12:43:37 2021
|
||||
# Process ID: 1568
|
||||
# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1
|
||||
# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace
|
||||
# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi
|
||||
# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source VGA_top.tcl -notrace
|
||||
Command: link_design -top VGA_top -part xc7z010clg400-1
|
||||
Design is defaulting to srcset: sources_1
|
||||
Design is defaulting to constrset: constrs_1
|
||||
INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.dcp' for cell 'U0'
|
||||
INFO: [Netlist 29-17] Analyzing 3 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-479] Netlist was created with Vivado 2018.3
|
||||
INFO: [Device 21-403] Loading part xc7z010clg400-1
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
|
||||
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
|
||||
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
|
||||
INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
|
||||
get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1225.328 ; gain = 533.879
|
||||
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
|
||||
Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
|
||||
Finished Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1225.328 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
link_design completed successfully
|
||||
link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:16 . Memory (MB): peak = 1225.328 ; gain = 861.820
|
||||
Command: opt_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
Running DRC as a precondition to command opt_design
|
||||
|
||||
Starting DRC Task
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Project 1-461] DRC finished with 0 Errors
|
||||
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.509 . Memory (MB): peak = 1225.328 ; gain = 0.000
|
||||
|
||||
Starting Cache Timing Information Task
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [Timing 38-2] Deriving generated clocks
|
||||
Ending Cache Timing Information Task | Checksum: 1cd387b97
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1242.352 ; gain = 17.023
|
||||
|
||||
Starting Logic Optimization Task
|
||||
|
||||
Phase 1 Retarget
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Opt 31-49] Retargeted 0 cell(s).
|
||||
Phase 1 Retarget | Checksum: 1cd387b97
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1322.477 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
|
||||
INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
||||
|
||||
Phase 2 Constant propagation
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Phase 2 Constant propagation | Checksum: 1cd387b97
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1322.477 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
|
||||
|
||||
Phase 3 Sweep
|
||||
Phase 3 Sweep | Checksum: 11a1ea9c4
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1322.477 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
|
||||
|
||||
Phase 4 BUFG optimization
|
||||
INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG
|
||||
INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets
|
||||
Phase 4 BUFG optimization | Checksum: 1b004ba0c
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1322.477 ; gain = 0.000
|
||||
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
|
||||
|
||||
Phase 5 Shift Register Optimization
|
||||
Phase 5 Shift Register Optimization | Checksum: 154e32ba9
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1322.477 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
|
||||
|
||||
Phase 6 Post Processing Netlist
|
||||
Phase 6 Post Processing Netlist | Checksum: 14b38df59
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 1322.477 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
|
||||
Opt_design Change Summary
|
||||
=========================
|
||||
|
||||
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Retarget | 0 | 0 | 1 |
|
||||
| Constant propagation | 0 | 0 | 0 |
|
||||
| Sweep | 0 | 0 | 0 |
|
||||
| BUFG optimization | 0 | 0 | 0 |
|
||||
| Shift Register Optimization | 0 | 0 | 0 |
|
||||
| Post Processing Netlist | 0 | 0 | 0 |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
Starting Connectivity Check Task
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1322.477 ; gain = 0.000
|
||||
Ending Logic Optimization Task | Checksum: 1327b0867
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1322.477 ; gain = 0.000
|
||||
|
||||
Starting Power Optimization Task
|
||||
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
|
||||
Ending Power Optimization Task | Checksum: 1327b0867
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1322.477 ; gain = 0.000
|
||||
|
||||
Starting Final Cleanup Task
|
||||
Ending Final Cleanup Task | Checksum: 1327b0867
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1322.477 ; gain = 0.000
|
||||
|
||||
Starting Netlist Obfuscation Task
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1322.477 ; gain = 0.000
|
||||
Ending Netlist Obfuscation Task | Checksum: 1327b0867
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1322.477 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
opt_design completed successfully
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1322.477 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1322.477 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1322.477 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
|
||||
Command: report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt.
|
||||
report_drc completed successfully
|
||||
Command: place_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
Running DRC as a precondition to command place_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Starting Placer Task
|
||||
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
|
||||
|
||||
Phase 1 Placer Initialization
|
||||
|
||||
Phase 1.1 Placer Initialization Netlist Sorting
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1322.477 ; gain = 0.000
|
||||
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 11a18955b
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1322.477 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1322.477 ; gain = 0.000
|
||||
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 14857c37a
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.244 . Memory (MB): peak = 1322.477 ; gain = 0.000
|
||||
|
||||
Phase 1.3 Build Placer Netlist Model
|
||||
Phase 1.3 Build Placer Netlist Model | Checksum: 1be26ef67
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.306 . Memory (MB): peak = 1323.027 ; gain = 0.551
|
||||
|
||||
Phase 1.4 Constrain Clocks/Macros
|
||||
Phase 1.4 Constrain Clocks/Macros | Checksum: 1be26ef67
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.307 . Memory (MB): peak = 1323.027 ; gain = 0.551
|
||||
Phase 1 Placer Initialization | Checksum: 1be26ef67
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.308 . Memory (MB): peak = 1323.027 ; gain = 0.551
|
||||
|
||||
Phase 2 Global Placement
|
||||
|
||||
Phase 2.1 Floorplanning
|
||||
Phase 2.1 Floorplanning | Checksum: 225160abb
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.356 . Memory (MB): peak = 1323.027 ; gain = 0.551
|
||||
|
||||
Phase 2.2 Physical Synthesis In Placer
|
||||
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
|
||||
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
|
||||
INFO: [Physopt 32-949] No candidate nets found for HD net replication
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1323.027 ; gain = 0.000
|
||||
|
||||
Summary of Physical Synthesis Optimizations
|
||||
============================================
|
||||
|
||||
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 |
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Phase 2.2 Physical Synthesis In Placer | Checksum: 1ba25206f
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.875 . Memory (MB): peak = 1323.027 ; gain = 0.551
|
||||
Phase 2 Global Placement | Checksum: 23614170f
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.885 . Memory (MB): peak = 1323.027 ; gain = 0.551
|
||||
|
||||
Phase 3 Detail Placement
|
||||
|
||||
Phase 3.1 Commit Multi Column Macros
|
||||
Phase 3.1 Commit Multi Column Macros | Checksum: 23614170f
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.886 . Memory (MB): peak = 1323.027 ; gain = 0.551
|
||||
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 192f50611
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.941 . Memory (MB): peak = 1323.027 ; gain = 0.551
|
||||
|
||||
Phase 3.3 Area Swap Optimization
|
||||
Phase 3.3 Area Swap Optimization | Checksum: 163924b15
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.942 . Memory (MB): peak = 1323.027 ; gain = 0.551
|
||||
|
||||
Phase 3.4 Pipeline Register Optimization
|
||||
Phase 3.4 Pipeline Register Optimization | Checksum: 163924b15
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.943 . Memory (MB): peak = 1323.027 ; gain = 0.551
|
||||
|
||||
Phase 3.5 Small Shape Detail Placement
|
||||
Phase 3.5 Small Shape Detail Placement | Checksum: 19c86ae3a
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.990 . Memory (MB): peak = 1323.027 ; gain = 0.551
|
||||
|
||||
Phase 3.6 Re-assign LUT pins
|
||||
Phase 3.6 Re-assign LUT pins | Checksum: 175abb83f
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.994 . Memory (MB): peak = 1323.027 ; gain = 0.551
|
||||
|
||||
Phase 3.7 Pipeline Register Optimization
|
||||
Phase 3.7 Pipeline Register Optimization | Checksum: 175abb83f
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.994 . Memory (MB): peak = 1323.027 ; gain = 0.551
|
||||
Phase 3 Detail Placement | Checksum: 175abb83f
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.995 . Memory (MB): peak = 1323.027 ; gain = 0.551
|
||||
|
||||
Phase 4 Post Placement Optimization and Clean-Up
|
||||
|
||||
Phase 4.1 Post Commit Optimization
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
|
||||
Phase 4.1.1 Post Placement Optimization
|
||||
Post Placement Optimization Initialization | Checksum: 284ea0e0d
|
||||
|
||||
Phase 4.1.1.1 BUFG Insertion
|
||||
INFO: [Place 46-46] BUFG insertion identified 0 candidate nets, 0 success, 0 bufg driver replicated, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason
|
||||
Phase 4.1.1.1 BUFG Insertion | Checksum: 284ea0e0d
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1323.027 ; gain = 0.551
|
||||
INFO: [Place 30-746] Post Placement Timing Summary WNS=35.407. For the most accurate timing information please run report_timing.
|
||||
Phase 4.1.1 Post Placement Optimization | Checksum: 26a7dbbcb
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1323.027 ; gain = 0.551
|
||||
Phase 4.1 Post Commit Optimization | Checksum: 26a7dbbcb
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1323.027 ; gain = 0.551
|
||||
|
||||
Phase 4.2 Post Placement Cleanup
|
||||
Phase 4.2 Post Placement Cleanup | Checksum: 26a7dbbcb
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1323.027 ; gain = 0.551
|
||||
|
||||
Phase 4.3 Placer Reporting
|
||||
Phase 4.3 Placer Reporting | Checksum: 26a7dbbcb
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1323.027 ; gain = 0.551
|
||||
|
||||
Phase 4.4 Final Placement Cleanup
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1323.027 ; gain = 0.000
|
||||
Phase 4.4 Final Placement Cleanup | Checksum: 1e396e624
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1323.027 ; gain = 0.551
|
||||
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1e396e624
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1323.027 ; gain = 0.551
|
||||
Ending Placer Task | Checksum: 10ebd1779
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1323.027 ; gain = 0.551
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
57 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
place_design completed successfully
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1323.027 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1323.746 ; gain = 0.719
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1323.746 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_io -file VGA_top_io_placed.rpt
|
||||
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1323.762 ; gain = 0.000
|
||||
INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb
|
||||
INFO: [runtcl-4] Executing : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt
|
||||
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1323.762 ; gain = 0.000
|
||||
Command: route_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
Running DRC as a precondition to command route_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
|
||||
Starting Routing Task
|
||||
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
|
||||
Checksum: PlaceDB: b0b141f5 ConstDB: 0 ShapeSum: 5e0bd584 RouteDB: 0
|
||||
|
||||
Phase 1 Build RT Design
|
||||
Phase 1 Build RT Design | Checksum: 15f37acc5
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1400.961 ; gain = 77.199
|
||||
Post Restoration Checksum: NetGraph: 6fc77d0c NumContArr: ef702fb9 Constraints: 0 Timing: 0
|
||||
|
||||
Phase 2 Router Initialization
|
||||
|
||||
Phase 2.1 Create Timer
|
||||
Phase 2.1 Create Timer | Checksum: 15f37acc5
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1425.180 ; gain = 101.418
|
||||
|
||||
Phase 2.2 Fix Topology Constraints
|
||||
Phase 2.2 Fix Topology Constraints | Checksum: 15f37acc5
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1431.219 ; gain = 107.457
|
||||
|
||||
Phase 2.3 Pre Route Cleanup
|
||||
Phase 2.3 Pre Route Cleanup | Checksum: 15f37acc5
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1431.219 ; gain = 107.457
|
||||
Number of Nodes with overlaps = 0
|
||||
|
||||
Phase 2.4 Update Timing
|
||||
Phase 2.4 Update Timing | Checksum: ca14e25f
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1433.867 ; gain = 110.105
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.355 | TNS=0.000 | WHS=-0.272 | THS=-3.945 |
|
||||
|
||||
Phase 2 Router Initialization | Checksum: ac53c1db
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1433.867 ; gain = 110.105
|
||||
|
||||
Phase 3 Initial Routing
|
||||
Phase 3 Initial Routing | Checksum: 19f2e1359
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1433.867 ; gain = 110.105
|
||||
|
||||
Phase 4 Rip-up And Reroute
|
||||
|
||||
Phase 4.1 Global Iteration 0
|
||||
Number of Nodes with overlaps = 1
|
||||
Number of Nodes with overlaps = 0
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=34.993 | TNS=0.000 | WHS=N/A | THS=N/A |
|
||||
|
||||
Phase 4.1 Global Iteration 0 | Checksum: a28f5e66
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.867 ; gain = 110.105
|
||||
Phase 4 Rip-up And Reroute | Checksum: a28f5e66
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.867 ; gain = 110.105
|
||||
|
||||
Phase 5 Delay and Skew Optimization
|
||||
|
||||
Phase 5.1 Delay CleanUp
|
||||
Phase 5.1 Delay CleanUp | Checksum: a28f5e66
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.867 ; gain = 110.105
|
||||
|
||||
Phase 5.2 Clock Skew Optimization
|
||||
Phase 5.2 Clock Skew Optimization | Checksum: a28f5e66
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.867 ; gain = 110.105
|
||||
Phase 5 Delay and Skew Optimization | Checksum: a28f5e66
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.867 ; gain = 110.105
|
||||
|
||||
Phase 6 Post Hold Fix
|
||||
|
||||
Phase 6.1 Hold Fix Iter
|
||||
|
||||
Phase 6.1.1 Update Timing
|
||||
Phase 6.1.1 Update Timing | Checksum: 121d82faf
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.867 ; gain = 110.105
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.146 | TNS=0.000 | WHS=0.055 | THS=0.000 |
|
||||
|
||||
Phase 6.1 Hold Fix Iter | Checksum: 121d82faf
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.867 ; gain = 110.105
|
||||
Phase 6 Post Hold Fix | Checksum: 121d82faf
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.867 ; gain = 110.105
|
||||
|
||||
Phase 7 Route finalize
|
||||
|
||||
Router Utilization Summary
|
||||
Global Vertical Routing Utilization = 0.0235079 %
|
||||
Global Horizontal Routing Utilization = 0.0110294 %
|
||||
Routable Net Status*
|
||||
*Does not include unroutable nets such as driverless and loadless.
|
||||
Run report_route_status for detailed report.
|
||||
Number of Failed Nets = 0
|
||||
Number of Unrouted Nets = 0
|
||||
Number of Partially Routed Nets = 0
|
||||
Number of Node Overlaps = 0
|
||||
|
||||
Phase 7 Route finalize | Checksum: 174fa15d5
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.867 ; gain = 110.105
|
||||
|
||||
Phase 8 Verifying routed nets
|
||||
|
||||
Verification completed successfully
|
||||
Phase 8 Verifying routed nets | Checksum: 174fa15d5
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1435.516 ; gain = 111.754
|
||||
|
||||
Phase 9 Depositing Routes
|
||||
Phase 9 Depositing Routes | Checksum: 175dfb98b
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1435.516 ; gain = 111.754
|
||||
|
||||
Phase 10 Post Router Timing
|
||||
INFO: [Route 35-57] Estimated Timing Summary | WNS=35.146 | TNS=0.000 | WHS=0.055 | THS=0.000 |
|
||||
|
||||
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
|
||||
Phase 10 Post Router Timing | Checksum: 175dfb98b
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1435.516 ; gain = 111.754
|
||||
INFO: [Route 35-16] Router Completed Successfully
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1435.516 ; gain = 111.754
|
||||
|
||||
Routing Is Done.
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
74 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
route_design completed successfully
|
||||
route_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:22 . Memory (MB): peak = 1435.516 ; gain = 111.754
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1435.516 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 1435.516 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1435.516 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
|
||||
Command: report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt.
|
||||
report_drc completed successfully
|
||||
INFO: [runtcl-4] Executing : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
|
||||
Command: report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [DRC 23-133] Running Methodology with 2 threads
|
||||
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt.
|
||||
report_methodology completed successfully
|
||||
INFO: [runtcl-4] Executing : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
|
||||
Command: report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Running Vector-less Activity Propagation...
|
||||
|
||||
Finished Running Vector-less Activity Propagation
|
||||
86 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
report_power completed successfully
|
||||
INFO: [runtcl-4] Executing : report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb
|
||||
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
INFO: [runtcl-4] Executing : report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt
|
||||
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
|
||||
INFO: [runtcl-4] Executing : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt
|
||||
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
INFO: [Common 17-206] Exiting Vivado at Tue Nov 30 12:44:26 2021...
|
||||
@ -1,545 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Tue Nov 23 10:08:25 2021
|
||||
# Process ID: 4688
|
||||
# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1
|
||||
# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace
|
||||
# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi
|
||||
# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source VGA_top.tcl -notrace
|
||||
Command: link_design -top VGA_top -part xc7z010clg400-1
|
||||
Design is defaulting to srcset: sources_1
|
||||
Design is defaulting to constrset: constrs_1
|
||||
INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.dcp' for cell 'U0'
|
||||
INFO: [Netlist 29-17] Analyzing 11 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-479] Netlist was created with Vivado 2018.3
|
||||
INFO: [Device 21-403] Loading part xc7z010clg400-1
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
|
||||
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
|
||||
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
|
||||
INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
|
||||
get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1242.828 ; gain = 551.719
|
||||
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
|
||||
Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
|
||||
Finished Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1242.828 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
link_design completed successfully
|
||||
link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:24 . Memory (MB): peak = 1242.828 ; gain = 879.852
|
||||
Command: opt_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
Running DRC as a precondition to command opt_design
|
||||
|
||||
Starting DRC Task
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Project 1-461] DRC finished with 0 Errors
|
||||
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.501 . Memory (MB): peak = 1242.828 ; gain = 0.000
|
||||
|
||||
Starting Cache Timing Information Task
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [Timing 38-2] Deriving generated clocks
|
||||
Ending Cache Timing Information Task | Checksum: b8ea7a4e
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 1260.746 ; gain = 17.918
|
||||
|
||||
Starting Logic Optimization Task
|
||||
|
||||
Phase 1 Retarget
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Opt 31-49] Retargeted 0 cell(s).
|
||||
Phase 1 Retarget | Checksum: b8ea7a4e
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
|
||||
INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
||||
|
||||
Phase 2 Constant propagation
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Phase 2 Constant propagation | Checksum: b8ea7a4e
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
|
||||
|
||||
Phase 3 Sweep
|
||||
Phase 3 Sweep | Checksum: 69d8ab95
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
|
||||
|
||||
Phase 4 BUFG optimization
|
||||
INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG
|
||||
INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets
|
||||
Phase 4 BUFG optimization | Checksum: 13bee9dc1
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
|
||||
|
||||
Phase 5 Shift Register Optimization
|
||||
Phase 5 Shift Register Optimization | Checksum: 1a59d5459
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
|
||||
|
||||
Phase 6 Post Processing Netlist
|
||||
Phase 6 Post Processing Netlist | Checksum: 14a40c514
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
|
||||
Opt_design Change Summary
|
||||
=========================
|
||||
|
||||
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Retarget | 0 | 0 | 1 |
|
||||
| Constant propagation | 0 | 0 | 0 |
|
||||
| Sweep | 0 | 0 | 0 |
|
||||
| BUFG optimization | 0 | 0 | 0 |
|
||||
| Shift Register Optimization | 0 | 0 | 0 |
|
||||
| Post Processing Netlist | 0 | 0 | 0 |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
Starting Connectivity Check Task
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
Ending Logic Optimization Task | Checksum: 14dbbd0bc
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.041 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
|
||||
Starting Power Optimization Task
|
||||
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
|
||||
Ending Power Optimization Task | Checksum: 14dbbd0bc
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
|
||||
Starting Final Cleanup Task
|
||||
Ending Final Cleanup Task | Checksum: 14dbbd0bc
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
|
||||
Starting Netlist Obfuscation Task
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
Ending Netlist Obfuscation Task | Checksum: 14dbbd0bc
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
opt_design completed successfully
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
|
||||
Command: report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt.
|
||||
report_drc completed successfully
|
||||
Command: place_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
Running DRC as a precondition to command place_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Starting Placer Task
|
||||
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
|
||||
|
||||
Phase 1 Placer Initialization
|
||||
|
||||
Phase 1.1 Placer Initialization Netlist Sorting
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fa6d7a79
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.
|
||||
|
||||
bouton_down_IBUF_inst (IBUF.O) is locked to IOB_X0Y1
|
||||
bouton_down_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y1
|
||||
Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin.
|
||||
WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.
|
||||
|
||||
bouton_right_IBUF_inst (IBUF.O) is locked to IOB_X0Y36
|
||||
bouton_right_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0
|
||||
Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin.
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 12622357c
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.294 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
|
||||
Phase 1.3 Build Placer Netlist Model
|
||||
Phase 1.3 Build Placer Netlist Model | Checksum: 1b3b55d5e
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.354 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
|
||||
Phase 1.4 Constrain Clocks/Macros
|
||||
Phase 1.4 Constrain Clocks/Macros | Checksum: 1b3b55d5e
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.356 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
Phase 1 Placer Initialization | Checksum: 1b3b55d5e
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.356 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
|
||||
Phase 2 Global Placement
|
||||
|
||||
Phase 2.1 Floorplanning
|
||||
Phase 2.1 Floorplanning | Checksum: 1f34e0130
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.387 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
|
||||
Phase 2.2 Physical Synthesis In Placer
|
||||
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
|
||||
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
|
||||
INFO: [Physopt 32-949] No candidate nets found for HD net replication
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
|
||||
Summary of Physical Synthesis Optimizations
|
||||
============================================
|
||||
|
||||
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 |
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Phase 2.2 Physical Synthesis In Placer | Checksum: 1f822ab4a
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.899 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
Phase 2 Global Placement | Checksum: 17fde1b87
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.910 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
|
||||
Phase 3 Detail Placement
|
||||
|
||||
Phase 3.1 Commit Multi Column Macros
|
||||
Phase 3.1 Commit Multi Column Macros | Checksum: 17fde1b87
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.911 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 258919723
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.945 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
|
||||
Phase 3.3 Area Swap Optimization
|
||||
Phase 3.3 Area Swap Optimization | Checksum: 1af65d909
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.947 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
|
||||
Phase 3.4 Pipeline Register Optimization
|
||||
Phase 3.4 Pipeline Register Optimization | Checksum: 245deb5d9
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.948 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
|
||||
Phase 3.5 Small Shape Detail Placement
|
||||
Phase 3.5 Small Shape Detail Placement | Checksum: 1dab8f54b
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
|
||||
Phase 3.6 Re-assign LUT pins
|
||||
Phase 3.6 Re-assign LUT pins | Checksum: 1e1eee966
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
|
||||
Phase 3.7 Pipeline Register Optimization
|
||||
Phase 3.7 Pipeline Register Optimization | Checksum: f76e0896
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
Phase 3 Detail Placement | Checksum: f76e0896
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
|
||||
Phase 4 Post Placement Optimization and Clean-Up
|
||||
|
||||
Phase 4.1 Post Commit Optimization
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
|
||||
Phase 4.1.1 Post Placement Optimization
|
||||
Post Placement Optimization Initialization | Checksum: 13e7bd2c2
|
||||
|
||||
Phase 4.1.1.1 BUFG Insertion
|
||||
INFO: [Place 46-46] BUFG insertion identified 0 candidate nets, 0 success, 0 bufg driver replicated, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason
|
||||
Phase 4.1.1.1 BUFG Insertion | Checksum: 13e7bd2c2
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
INFO: [Place 30-746] Post Placement Timing Summary WNS=35.645. For the most accurate timing information please run report_timing.
|
||||
Phase 4.1.1 Post Placement Optimization | Checksum: 15c183492
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
Phase 4.1 Post Commit Optimization | Checksum: 15c183492
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
|
||||
Phase 4.2 Post Placement Cleanup
|
||||
Phase 4.2 Post Placement Cleanup | Checksum: 15c183492
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
|
||||
Phase 4.3 Placer Reporting
|
||||
Phase 4.3 Placer Reporting | Checksum: 15c183492
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
|
||||
Phase 4.4 Final Placement Cleanup
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
Phase 4.4 Final Placement Cleanup | Checksum: 17d5ce04d
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 17d5ce04d
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
Ending Placer Task | Checksum: d443f812
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
57 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
place_design completed successfully
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.043 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_io -file VGA_top_io_placed.rpt
|
||||
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb
|
||||
INFO: [runtcl-4] Executing : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt
|
||||
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1347.707 ; gain = 0.000
|
||||
Command: route_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
Running DRC as a precondition to command route_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG.
|
||||
Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin.
|
||||
This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.
|
||||
|
||||
bouton_down_IBUF_inst (IBUF.O) is locked to IOB_X0Y1
|
||||
bouton_down_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y1
|
||||
WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG.
|
||||
Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin.
|
||||
This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.
|
||||
|
||||
bouton_right_IBUF_inst (IBUF.O) is locked to IOB_X0Y36
|
||||
bouton_right_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 2 Warnings
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
|
||||
Starting Routing Task
|
||||
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
|
||||
Checksum: PlaceDB: 52480e80 ConstDB: 0 ShapeSum: 81fbe992 RouteDB: 0
|
||||
|
||||
Phase 1 Build RT Design
|
||||
Phase 1 Build RT Design | Checksum: fee31c87
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1413.883 ; gain = 66.176
|
||||
Post Restoration Checksum: NetGraph: e323ff66 NumContArr: 1bbf1d21 Constraints: 0 Timing: 0
|
||||
|
||||
Phase 2 Router Initialization
|
||||
|
||||
Phase 2.1 Create Timer
|
||||
Phase 2.1 Create Timer | Checksum: fee31c87
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1444.188 ; gain = 96.480
|
||||
|
||||
Phase 2.2 Fix Topology Constraints
|
||||
Phase 2.2 Fix Topology Constraints | Checksum: fee31c87
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1450.230 ; gain = 102.523
|
||||
|
||||
Phase 2.3 Pre Route Cleanup
|
||||
Phase 2.3 Pre Route Cleanup | Checksum: fee31c87
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1450.230 ; gain = 102.523
|
||||
Number of Nodes with overlaps = 0
|
||||
|
||||
Phase 2.4 Update Timing
|
||||
Phase 2.4 Update Timing | Checksum: 1441c14dd
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1454.770 ; gain = 107.062
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.769 | TNS=0.000 | WHS=-0.258 | THS=-3.023 |
|
||||
|
||||
Phase 2 Router Initialization | Checksum: 173a347ed
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1454.770 ; gain = 107.062
|
||||
|
||||
Phase 3 Initial Routing
|
||||
Phase 3 Initial Routing | Checksum: 205eb8b74
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1455.496 ; gain = 107.789
|
||||
|
||||
Phase 4 Rip-up And Reroute
|
||||
|
||||
Phase 4.1 Global Iteration 0
|
||||
Number of Nodes with overlaps = 17
|
||||
Number of Nodes with overlaps = 0
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.132 | TNS=0.000 | WHS=N/A | THS=N/A |
|
||||
|
||||
Phase 4.1 Global Iteration 0 | Checksum: 2843d0f71
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1455.496 ; gain = 107.789
|
||||
Phase 4 Rip-up And Reroute | Checksum: 2843d0f71
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1455.496 ; gain = 107.789
|
||||
|
||||
Phase 5 Delay and Skew Optimization
|
||||
|
||||
Phase 5.1 Delay CleanUp
|
||||
Phase 5.1 Delay CleanUp | Checksum: 2843d0f71
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1455.496 ; gain = 107.789
|
||||
|
||||
Phase 5.2 Clock Skew Optimization
|
||||
Phase 5.2 Clock Skew Optimization | Checksum: 2843d0f71
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1455.496 ; gain = 107.789
|
||||
Phase 5 Delay and Skew Optimization | Checksum: 2843d0f71
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1455.496 ; gain = 107.789
|
||||
|
||||
Phase 6 Post Hold Fix
|
||||
|
||||
Phase 6.1 Hold Fix Iter
|
||||
|
||||
Phase 6.1.1 Update Timing
|
||||
Phase 6.1.1 Update Timing | Checksum: 1adede088
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1455.496 ; gain = 107.789
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.132 | TNS=0.000 | WHS=0.069 | THS=0.000 |
|
||||
|
||||
Phase 6.1 Hold Fix Iter | Checksum: 1adede088
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1455.496 ; gain = 107.789
|
||||
Phase 6 Post Hold Fix | Checksum: 1adede088
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1455.496 ; gain = 107.789
|
||||
|
||||
Phase 7 Route finalize
|
||||
|
||||
Router Utilization Summary
|
||||
Global Vertical Routing Utilization = 0.0615146 %
|
||||
Global Horizontal Routing Utilization = 0.0558364 %
|
||||
Routable Net Status*
|
||||
*Does not include unroutable nets such as driverless and loadless.
|
||||
Run report_route_status for detailed report.
|
||||
Number of Failed Nets = 0
|
||||
Number of Unrouted Nets = 0
|
||||
Number of Partially Routed Nets = 0
|
||||
Number of Node Overlaps = 0
|
||||
|
||||
Phase 7 Route finalize | Checksum: 2005f65b4
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1455.496 ; gain = 107.789
|
||||
|
||||
Phase 8 Verifying routed nets
|
||||
|
||||
Verification completed successfully
|
||||
Phase 8 Verifying routed nets | Checksum: 2005f65b4
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1456.543 ; gain = 108.836
|
||||
|
||||
Phase 9 Depositing Routes
|
||||
Phase 9 Depositing Routes | Checksum: 18ba5fe80
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1456.543 ; gain = 108.836
|
||||
|
||||
Phase 10 Post Router Timing
|
||||
INFO: [Route 35-57] Estimated Timing Summary | WNS=35.132 | TNS=0.000 | WHS=0.069 | THS=0.000 |
|
||||
|
||||
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
|
||||
Phase 10 Post Router Timing | Checksum: 18ba5fe80
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1456.543 ; gain = 108.836
|
||||
INFO: [Route 35-16] Router Completed Successfully
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1456.543 ; gain = 108.836
|
||||
|
||||
Routing Is Done.
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
74 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
route_design completed successfully
|
||||
route_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1456.543 ; gain = 108.836
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1456.543 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.047 . Memory (MB): peak = 1456.957 ; gain = 0.414
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1456.957 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
|
||||
Command: report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt.
|
||||
report_drc completed successfully
|
||||
INFO: [runtcl-4] Executing : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
|
||||
Command: report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [DRC 23-133] Running Methodology with 2 threads
|
||||
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt.
|
||||
report_methodology completed successfully
|
||||
INFO: [runtcl-4] Executing : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
|
||||
Command: report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Running Vector-less Activity Propagation...
|
||||
|
||||
Finished Running Vector-less Activity Propagation
|
||||
86 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
report_power completed successfully
|
||||
INFO: [runtcl-4] Executing : report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb
|
||||
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
INFO: [runtcl-4] Executing : report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt
|
||||
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
|
||||
INFO: [runtcl-4] Executing : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt
|
||||
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
INFO: [Common 17-206] Exiting Vivado at Tue Nov 23 10:09:12 2021...
|
||||
@ -1,523 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Tue Dec 7 12:30:30 2021
|
||||
# Process ID: 4708
|
||||
# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1
|
||||
# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace
|
||||
# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi
|
||||
# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source VGA_top.tcl -notrace
|
||||
Command: link_design -top VGA_top -part xc7z010clg400-1
|
||||
Design is defaulting to srcset: sources_1
|
||||
Design is defaulting to constrset: constrs_1
|
||||
INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.dcp' for cell 'U0'
|
||||
INFO: [Netlist 29-17] Analyzing 11 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-479] Netlist was created with Vivado 2018.3
|
||||
INFO: [Device 21-403] Loading part xc7z010clg400-1
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
|
||||
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
|
||||
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
|
||||
INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
|
||||
get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1242.105 ; gain = 551.648
|
||||
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
|
||||
Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
|
||||
Finished Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1242.105 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
link_design completed successfully
|
||||
link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:16 . Memory (MB): peak = 1242.105 ; gain = 878.844
|
||||
Command: opt_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
Running DRC as a precondition to command opt_design
|
||||
|
||||
Starting DRC Task
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Project 1-461] DRC finished with 0 Errors
|
||||
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.511 . Memory (MB): peak = 1242.105 ; gain = 0.000
|
||||
|
||||
Starting Cache Timing Information Task
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [Timing 38-2] Deriving generated clocks
|
||||
Ending Cache Timing Information Task | Checksum: d2ac4cf6
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1259.926 ; gain = 17.820
|
||||
|
||||
Starting Logic Optimization Task
|
||||
|
||||
Phase 1 Retarget
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Opt 31-49] Retargeted 0 cell(s).
|
||||
Phase 1 Retarget | Checksum: 1f756781a
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 1 cells
|
||||
INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
||||
|
||||
Phase 2 Constant propagation
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Phase 2 Constant propagation | Checksum: 1f756781a
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
|
||||
|
||||
Phase 3 Sweep
|
||||
Phase 3 Sweep | Checksum: 20f92b0fa
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
|
||||
|
||||
Phase 4 BUFG optimization
|
||||
INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG
|
||||
INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets
|
||||
Phase 4 BUFG optimization | Checksum: 19f2c89a4
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
|
||||
|
||||
Phase 5 Shift Register Optimization
|
||||
Phase 5 Shift Register Optimization | Checksum: 948878b4
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
|
||||
|
||||
Phase 6 Post Processing Netlist
|
||||
Phase 6 Post Processing Netlist | Checksum: 10d0c29d4
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
|
||||
Opt_design Change Summary
|
||||
=========================
|
||||
|
||||
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Retarget | 0 | 1 | 1 |
|
||||
| Constant propagation | 0 | 0 | 0 |
|
||||
| Sweep | 0 | 0 | 0 |
|
||||
| BUFG optimization | 0 | 0 | 0 |
|
||||
| Shift Register Optimization | 0 | 0 | 0 |
|
||||
| Post Processing Netlist | 0 | 0 | 0 |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
Starting Connectivity Check Task
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
Ending Logic Optimization Task | Checksum: 1063f0394
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
|
||||
Starting Power Optimization Task
|
||||
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
|
||||
Ending Power Optimization Task | Checksum: 1063f0394
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
|
||||
Starting Final Cleanup Task
|
||||
Ending Final Cleanup Task | Checksum: 1063f0394
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
|
||||
Starting Netlist Obfuscation Task
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
Ending Netlist Obfuscation Task | Checksum: 1063f0394
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
opt_design completed successfully
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
|
||||
Command: report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt.
|
||||
report_drc completed successfully
|
||||
Command: place_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
Running DRC as a precondition to command place_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Starting Placer Task
|
||||
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
|
||||
|
||||
Phase 1 Placer Initialization
|
||||
|
||||
Phase 1.1 Placer Initialization Netlist Sorting
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 73a34972
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1183e7dd3
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.259 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
|
||||
Phase 1.3 Build Placer Netlist Model
|
||||
Phase 1.3 Build Placer Netlist Model | Checksum: 1d9a96167
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.330 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
|
||||
Phase 1.4 Constrain Clocks/Macros
|
||||
Phase 1.4 Constrain Clocks/Macros | Checksum: 1d9a96167
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.331 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
Phase 1 Placer Initialization | Checksum: 1d9a96167
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.331 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
|
||||
Phase 2 Global Placement
|
||||
|
||||
Phase 2.1 Floorplanning
|
||||
Phase 2.1 Floorplanning | Checksum: 207239471
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.384 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
|
||||
Phase 2.2 Physical Synthesis In Placer
|
||||
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
|
||||
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
|
||||
INFO: [Physopt 32-949] No candidate nets found for HD net replication
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
|
||||
Summary of Physical Synthesis Optimizations
|
||||
============================================
|
||||
|
||||
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 |
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Phase 2.2 Physical Synthesis In Placer | Checksum: 1ec0f74d9
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
Phase 2 Global Placement | Checksum: 1db1d9ae8
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
|
||||
Phase 3 Detail Placement
|
||||
|
||||
Phase 3.1 Commit Multi Column Macros
|
||||
Phase 3.1 Commit Multi Column Macros | Checksum: 1db1d9ae8
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1b8be6344
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
|
||||
Phase 3.3 Area Swap Optimization
|
||||
Phase 3.3 Area Swap Optimization | Checksum: 24618d2d2
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
|
||||
Phase 3.4 Pipeline Register Optimization
|
||||
Phase 3.4 Pipeline Register Optimization | Checksum: 24618d2d2
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
|
||||
Phase 3.5 Small Shape Detail Placement
|
||||
Phase 3.5 Small Shape Detail Placement | Checksum: f3458c6a
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
|
||||
Phase 3.6 Re-assign LUT pins
|
||||
Phase 3.6 Re-assign LUT pins | Checksum: 1248ba3b4
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
|
||||
Phase 3.7 Pipeline Register Optimization
|
||||
Phase 3.7 Pipeline Register Optimization | Checksum: 1248ba3b4
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
Phase 3 Detail Placement | Checksum: 1248ba3b4
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
|
||||
Phase 4 Post Placement Optimization and Clean-Up
|
||||
|
||||
Phase 4.1 Post Commit Optimization
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
|
||||
Phase 4.1.1 Post Placement Optimization
|
||||
Post Placement Optimization Initialization | Checksum: 1635a43ad
|
||||
|
||||
Phase 4.1.1.1 BUFG Insertion
|
||||
INFO: [Place 46-46] BUFG insertion identified 0 candidate nets, 0 success, 0 bufg driver replicated, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason
|
||||
Phase 4.1.1.1 BUFG Insertion | Checksum: 1635a43ad
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
INFO: [Place 30-746] Post Placement Timing Summary WNS=36.020. For the most accurate timing information please run report_timing.
|
||||
Phase 4.1.1 Post Placement Optimization | Checksum: 23bd24a0c
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
Phase 4.1 Post Commit Optimization | Checksum: 23bd24a0c
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
|
||||
Phase 4.2 Post Placement Cleanup
|
||||
Phase 4.2 Post Placement Cleanup | Checksum: 23bd24a0c
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
|
||||
Phase 4.3 Placer Reporting
|
||||
Phase 4.3 Placer Reporting | Checksum: 23bd24a0c
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
|
||||
Phase 4.4 Final Placement Cleanup
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
Phase 4.4 Final Placement Cleanup | Checksum: 219552bc9
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 219552bc9
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
Ending Placer Task | Checksum: 125980005
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
57 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
place_design completed successfully
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.044 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_io -file VGA_top_io_placed.rpt
|
||||
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb
|
||||
INFO: [runtcl-4] Executing : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt
|
||||
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1343.621 ; gain = 0.000
|
||||
Command: route_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
Running DRC as a precondition to command route_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
|
||||
Starting Routing Task
|
||||
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
|
||||
Checksum: PlaceDB: af6487ab ConstDB: 0 ShapeSum: 7633785a RouteDB: 0
|
||||
|
||||
Phase 1 Build RT Design
|
||||
Phase 1 Build RT Design | Checksum: c740a96f
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1409.477 ; gain = 65.855
|
||||
Post Restoration Checksum: NetGraph: 9566862e NumContArr: 31da2341 Constraints: 0 Timing: 0
|
||||
|
||||
Phase 2 Router Initialization
|
||||
|
||||
Phase 2.1 Create Timer
|
||||
Phase 2.1 Create Timer | Checksum: c740a96f
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1439.797 ; gain = 96.176
|
||||
|
||||
Phase 2.2 Fix Topology Constraints
|
||||
Phase 2.2 Fix Topology Constraints | Checksum: c740a96f
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1445.828 ; gain = 102.207
|
||||
|
||||
Phase 2.3 Pre Route Cleanup
|
||||
Phase 2.3 Pre Route Cleanup | Checksum: c740a96f
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1445.828 ; gain = 102.207
|
||||
Number of Nodes with overlaps = 0
|
||||
|
||||
Phase 2.4 Update Timing
|
||||
Phase 2.4 Update Timing | Checksum: e75bf5ee
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1448.480 ; gain = 104.859
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.988 | TNS=0.000 | WHS=-0.304 | THS=-3.628 |
|
||||
|
||||
Phase 2 Router Initialization | Checksum: 43607781
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1448.480 ; gain = 104.859
|
||||
|
||||
Phase 3 Initial Routing
|
||||
Phase 3 Initial Routing | Checksum: 12c466190
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1448.480 ; gain = 104.859
|
||||
|
||||
Phase 4 Rip-up And Reroute
|
||||
|
||||
Phase 4.1 Global Iteration 0
|
||||
Number of Nodes with overlaps = 10
|
||||
Number of Nodes with overlaps = 0
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.445 | TNS=0.000 | WHS=N/A | THS=N/A |
|
||||
|
||||
Phase 4.1 Global Iteration 0 | Checksum: 210804e73
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1448.480 ; gain = 104.859
|
||||
Phase 4 Rip-up And Reroute | Checksum: 210804e73
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1448.480 ; gain = 104.859
|
||||
|
||||
Phase 5 Delay and Skew Optimization
|
||||
|
||||
Phase 5.1 Delay CleanUp
|
||||
Phase 5.1 Delay CleanUp | Checksum: 210804e73
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1448.480 ; gain = 104.859
|
||||
|
||||
Phase 5.2 Clock Skew Optimization
|
||||
Phase 5.2 Clock Skew Optimization | Checksum: 210804e73
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1448.480 ; gain = 104.859
|
||||
Phase 5 Delay and Skew Optimization | Checksum: 210804e73
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1448.480 ; gain = 104.859
|
||||
|
||||
Phase 6 Post Hold Fix
|
||||
|
||||
Phase 6.1 Hold Fix Iter
|
||||
|
||||
Phase 6.1.1 Update Timing
|
||||
Phase 6.1.1 Update Timing | Checksum: 14a89ec0d
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1448.480 ; gain = 104.859
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.560 | TNS=0.000 | WHS=0.076 | THS=0.000 |
|
||||
|
||||
Phase 6.1 Hold Fix Iter | Checksum: 14a89ec0d
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1448.480 ; gain = 104.859
|
||||
Phase 6 Post Hold Fix | Checksum: 14a89ec0d
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1448.480 ; gain = 104.859
|
||||
|
||||
Phase 7 Route finalize
|
||||
|
||||
Router Utilization Summary
|
||||
Global Vertical Routing Utilization = 0.0451858 %
|
||||
Global Horizontal Routing Utilization = 0.0363051 %
|
||||
Routable Net Status*
|
||||
*Does not include unroutable nets such as driverless and loadless.
|
||||
Run report_route_status for detailed report.
|
||||
Number of Failed Nets = 0
|
||||
Number of Unrouted Nets = 0
|
||||
Number of Partially Routed Nets = 0
|
||||
Number of Node Overlaps = 0
|
||||
|
||||
Phase 7 Route finalize | Checksum: 2224be1cd
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1448.480 ; gain = 104.859
|
||||
|
||||
Phase 8 Verifying routed nets
|
||||
|
||||
Verification completed successfully
|
||||
Phase 8 Verifying routed nets | Checksum: 2224be1cd
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1450.207 ; gain = 106.586
|
||||
|
||||
Phase 9 Depositing Routes
|
||||
Phase 9 Depositing Routes | Checksum: 180a9d30f
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1450.207 ; gain = 106.586
|
||||
|
||||
Phase 10 Post Router Timing
|
||||
INFO: [Route 35-57] Estimated Timing Summary | WNS=35.560 | TNS=0.000 | WHS=0.076 | THS=0.000 |
|
||||
|
||||
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
|
||||
Phase 10 Post Router Timing | Checksum: 180a9d30f
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1450.207 ; gain = 106.586
|
||||
INFO: [Route 35-16] Router Completed Successfully
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1450.207 ; gain = 106.586
|
||||
|
||||
Routing Is Done.
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
74 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
route_design completed successfully
|
||||
route_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:22 . Memory (MB): peak = 1450.207 ; gain = 106.586
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1450.207 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.045 . Memory (MB): peak = 1450.629 ; gain = 0.422
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1450.629 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
|
||||
Command: report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt.
|
||||
report_drc completed successfully
|
||||
INFO: [runtcl-4] Executing : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
|
||||
Command: report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [DRC 23-133] Running Methodology with 2 threads
|
||||
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt.
|
||||
report_methodology completed successfully
|
||||
INFO: [runtcl-4] Executing : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
|
||||
Command: report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Running Vector-less Activity Propagation...
|
||||
|
||||
Finished Running Vector-less Activity Propagation
|
||||
86 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
report_power completed successfully
|
||||
INFO: [runtcl-4] Executing : report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb
|
||||
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
INFO: [runtcl-4] Executing : report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt
|
||||
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
|
||||
INFO: [runtcl-4] Executing : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt
|
||||
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
INFO: [Common 17-206] Exiting Vivado at Tue Dec 7 12:31:19 2021...
|
||||
@ -1,523 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Tue Dec 7 12:42:58 2021
|
||||
# Process ID: 4856
|
||||
# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1
|
||||
# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace
|
||||
# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi
|
||||
# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source VGA_top.tcl -notrace
|
||||
Command: link_design -top VGA_top -part xc7z010clg400-1
|
||||
Design is defaulting to srcset: sources_1
|
||||
Design is defaulting to constrset: constrs_1
|
||||
INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.dcp' for cell 'U0'
|
||||
INFO: [Netlist 29-17] Analyzing 35 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-479] Netlist was created with Vivado 2018.3
|
||||
INFO: [Device 21-403] Loading part xc7z010clg400-1
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
|
||||
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
|
||||
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
|
||||
INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
|
||||
get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1248.586 ; gain = 558.375
|
||||
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
|
||||
Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
|
||||
Finished Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1248.586 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
link_design completed successfully
|
||||
link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:16 . Memory (MB): peak = 1248.586 ; gain = 885.598
|
||||
Command: opt_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
Running DRC as a precondition to command opt_design
|
||||
|
||||
Starting DRC Task
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Project 1-461] DRC finished with 0 Errors
|
||||
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.499 . Memory (MB): peak = 1248.586 ; gain = 0.000
|
||||
|
||||
Starting Cache Timing Information Task
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [Timing 38-2] Deriving generated clocks
|
||||
Ending Cache Timing Information Task | Checksum: 20ae1d4cd
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1265.152 ; gain = 16.566
|
||||
|
||||
Starting Logic Optimization Task
|
||||
|
||||
Phase 1 Retarget
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Opt 31-49] Retargeted 0 cell(s).
|
||||
Phase 1 Retarget | Checksum: ddde5939
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Retarget created 4 cells and removed 4 cells
|
||||
INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
||||
|
||||
Phase 2 Constant propagation
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Phase 2 Constant propagation | Checksum: ddde5939
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
|
||||
|
||||
Phase 3 Sweep
|
||||
Phase 3 Sweep | Checksum: fec5e707
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
|
||||
|
||||
Phase 4 BUFG optimization
|
||||
INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG
|
||||
INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets
|
||||
Phase 4 BUFG optimization | Checksum: 137e6b9d1
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
|
||||
|
||||
Phase 5 Shift Register Optimization
|
||||
Phase 5 Shift Register Optimization | Checksum: 12c29fba6
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
|
||||
|
||||
Phase 6 Post Processing Netlist
|
||||
Phase 6 Post Processing Netlist | Checksum: 10c49128f
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
|
||||
Opt_design Change Summary
|
||||
=========================
|
||||
|
||||
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Retarget | 4 | 4 | 1 |
|
||||
| Constant propagation | 0 | 0 | 0 |
|
||||
| Sweep | 0 | 0 | 0 |
|
||||
| BUFG optimization | 0 | 0 | 0 |
|
||||
| Shift Register Optimization | 0 | 0 | 0 |
|
||||
| Post Processing Netlist | 0 | 0 | 0 |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
Starting Connectivity Check Task
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Ending Logic Optimization Task | Checksum: e54fefee
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.057 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
|
||||
Starting Power Optimization Task
|
||||
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
|
||||
Ending Power Optimization Task | Checksum: e54fefee
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
|
||||
Starting Final Cleanup Task
|
||||
Ending Final Cleanup Task | Checksum: e54fefee
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
|
||||
Starting Netlist Obfuscation Task
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Ending Netlist Obfuscation Task | Checksum: e54fefee
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
opt_design completed successfully
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
|
||||
Command: report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt.
|
||||
report_drc completed successfully
|
||||
Command: place_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
Running DRC as a precondition to command place_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Starting Placer Task
|
||||
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
|
||||
|
||||
Phase 1 Placer Initialization
|
||||
|
||||
Phase 1.1 Placer Initialization Netlist Sorting
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 4ed236ad
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1a1c16c9c
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.262 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
|
||||
Phase 1.3 Build Placer Netlist Model
|
||||
Phase 1.3 Build Placer Netlist Model | Checksum: 2939760d0
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.351 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
|
||||
Phase 1.4 Constrain Clocks/Macros
|
||||
Phase 1.4 Constrain Clocks/Macros | Checksum: 2939760d0
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.353 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Phase 1 Placer Initialization | Checksum: 2939760d0
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.353 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
|
||||
Phase 2 Global Placement
|
||||
|
||||
Phase 2.1 Floorplanning
|
||||
Phase 2.1 Floorplanning | Checksum: 28231f14d
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.397 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
|
||||
Phase 2.2 Physical Synthesis In Placer
|
||||
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
|
||||
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
|
||||
INFO: [Physopt 32-949] No candidate nets found for HD net replication
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
|
||||
Summary of Physical Synthesis Optimizations
|
||||
============================================
|
||||
|
||||
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 |
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Phase 2.2 Physical Synthesis In Placer | Checksum: 22348ffd6
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Phase 2 Global Placement | Checksum: 2038a7242
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
|
||||
Phase 3 Detail Placement
|
||||
|
||||
Phase 3.1 Commit Multi Column Macros
|
||||
Phase 3.1 Commit Multi Column Macros | Checksum: 2038a7242
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 2c58c3354
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
|
||||
Phase 3.3 Area Swap Optimization
|
||||
Phase 3.3 Area Swap Optimization | Checksum: 279aeb7b4
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
|
||||
Phase 3.4 Pipeline Register Optimization
|
||||
Phase 3.4 Pipeline Register Optimization | Checksum: 279aeb7b4
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
|
||||
Phase 3.5 Small Shape Detail Placement
|
||||
Phase 3.5 Small Shape Detail Placement | Checksum: 1e0aaeea1
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
|
||||
Phase 3.6 Re-assign LUT pins
|
||||
Phase 3.6 Re-assign LUT pins | Checksum: 2d338840d
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
|
||||
Phase 3.7 Pipeline Register Optimization
|
||||
Phase 3.7 Pipeline Register Optimization | Checksum: 2d338840d
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Phase 3 Detail Placement | Checksum: 2d338840d
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
|
||||
Phase 4 Post Placement Optimization and Clean-Up
|
||||
|
||||
Phase 4.1 Post Commit Optimization
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
|
||||
Phase 4.1.1 Post Placement Optimization
|
||||
Post Placement Optimization Initialization | Checksum: 15c68dcd4
|
||||
|
||||
Phase 4.1.1.1 BUFG Insertion
|
||||
INFO: [Place 46-46] BUFG insertion identified 0 candidate nets, 0 success, 0 bufg driver replicated, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason
|
||||
Phase 4.1.1.1 BUFG Insertion | Checksum: 15c68dcd4
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
INFO: [Place 30-746] Post Placement Timing Summary WNS=35.245. For the most accurate timing information please run report_timing.
|
||||
Phase 4.1.1 Post Placement Optimization | Checksum: 142e419cd
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Phase 4.1 Post Commit Optimization | Checksum: 142e419cd
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
|
||||
Phase 4.2 Post Placement Cleanup
|
||||
Phase 4.2 Post Placement Cleanup | Checksum: 142e419cd
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
|
||||
Phase 4.3 Placer Reporting
|
||||
Phase 4.3 Placer Reporting | Checksum: 142e419cd
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
|
||||
Phase 4.4 Final Placement Cleanup
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Phase 4.4 Final Placement Cleanup | Checksum: 20695260e
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 20695260e
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Ending Placer Task | Checksum: 1f2b3c1b8
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
57 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
place_design completed successfully
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.050 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_io -file VGA_top_io_placed.rpt
|
||||
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb
|
||||
INFO: [runtcl-4] Executing : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt
|
||||
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Command: route_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
Running DRC as a precondition to command route_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
|
||||
Starting Routing Task
|
||||
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
|
||||
Checksum: PlaceDB: f9e7c0c6 ConstDB: 0 ShapeSum: f8cc00f2 RouteDB: 0
|
||||
|
||||
Phase 1 Build RT Design
|
||||
Phase 1 Build RT Design | Checksum: 9a64d846
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1417.348 ; gain = 66.250
|
||||
Post Restoration Checksum: NetGraph: 7c5b36de NumContArr: 1e09a168 Constraints: 0 Timing: 0
|
||||
|
||||
Phase 2 Router Initialization
|
||||
|
||||
Phase 2.1 Create Timer
|
||||
Phase 2.1 Create Timer | Checksum: 9a64d846
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1449.676 ; gain = 98.578
|
||||
|
||||
Phase 2.2 Fix Topology Constraints
|
||||
Phase 2.2 Fix Topology Constraints | Checksum: 9a64d846
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1455.699 ; gain = 104.602
|
||||
|
||||
Phase 2.3 Pre Route Cleanup
|
||||
Phase 2.3 Pre Route Cleanup | Checksum: 9a64d846
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1455.699 ; gain = 104.602
|
||||
Number of Nodes with overlaps = 0
|
||||
|
||||
Phase 2.4 Update Timing
|
||||
Phase 2.4 Update Timing | Checksum: 82bae049
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.391 | TNS=0.000 | WHS=-0.239 | THS=-2.915 |
|
||||
|
||||
Phase 2 Router Initialization | Checksum: cf693307
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
||||
|
||||
Phase 3 Initial Routing
|
||||
Phase 3 Initial Routing | Checksum: 16fee48da
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
||||
|
||||
Phase 4 Rip-up And Reroute
|
||||
|
||||
Phase 4.1 Global Iteration 0
|
||||
Number of Nodes with overlaps = 36
|
||||
Number of Nodes with overlaps = 0
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=33.088 | TNS=0.000 | WHS=N/A | THS=N/A |
|
||||
|
||||
Phase 4.1 Global Iteration 0 | Checksum: 1c93f85f6
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
||||
Phase 4 Rip-up And Reroute | Checksum: 1c93f85f6
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
||||
|
||||
Phase 5 Delay and Skew Optimization
|
||||
|
||||
Phase 5.1 Delay CleanUp
|
||||
Phase 5.1 Delay CleanUp | Checksum: 1c93f85f6
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
||||
|
||||
Phase 5.2 Clock Skew Optimization
|
||||
Phase 5.2 Clock Skew Optimization | Checksum: 1c93f85f6
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
||||
Phase 5 Delay and Skew Optimization | Checksum: 1c93f85f6
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
||||
|
||||
Phase 6 Post Hold Fix
|
||||
|
||||
Phase 6.1 Hold Fix Iter
|
||||
|
||||
Phase 6.1.1 Update Timing
|
||||
Phase 6.1.1 Update Timing | Checksum: 144941f51
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=33.241 | TNS=0.000 | WHS=0.083 | THS=0.000 |
|
||||
|
||||
Phase 6.1 Hold Fix Iter | Checksum: 144941f51
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
||||
Phase 6 Post Hold Fix | Checksum: 144941f51
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
||||
|
||||
Phase 7 Route finalize
|
||||
|
||||
Router Utilization Summary
|
||||
Global Vertical Routing Utilization = 0.0881194 %
|
||||
Global Horizontal Routing Utilization = 0.100414 %
|
||||
Routable Net Status*
|
||||
*Does not include unroutable nets such as driverless and loadless.
|
||||
Run report_route_status for detailed report.
|
||||
Number of Failed Nets = 0
|
||||
Number of Unrouted Nets = 0
|
||||
Number of Partially Routed Nets = 0
|
||||
Number of Node Overlaps = 0
|
||||
|
||||
Phase 7 Route finalize | Checksum: 19cea99c1
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
||||
|
||||
Phase 8 Verifying routed nets
|
||||
|
||||
Verification completed successfully
|
||||
Phase 8 Verifying routed nets | Checksum: 19cea99c1
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1461.477 ; gain = 110.379
|
||||
|
||||
Phase 9 Depositing Routes
|
||||
Phase 9 Depositing Routes | Checksum: 17f26a4e0
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1461.477 ; gain = 110.379
|
||||
|
||||
Phase 10 Post Router Timing
|
||||
INFO: [Route 35-57] Estimated Timing Summary | WNS=33.241 | TNS=0.000 | WHS=0.083 | THS=0.000 |
|
||||
|
||||
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
|
||||
Phase 10 Post Router Timing | Checksum: 17f26a4e0
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1461.477 ; gain = 110.379
|
||||
INFO: [Route 35-16] Router Completed Successfully
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1461.477 ; gain = 110.379
|
||||
|
||||
Routing Is Done.
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
74 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
route_design completed successfully
|
||||
route_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:22 . Memory (MB): peak = 1461.477 ; gain = 110.379
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1461.477 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 1461.910 ; gain = 0.434
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1461.910 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
|
||||
Command: report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt.
|
||||
report_drc completed successfully
|
||||
INFO: [runtcl-4] Executing : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
|
||||
Command: report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [DRC 23-133] Running Methodology with 2 threads
|
||||
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt.
|
||||
report_methodology completed successfully
|
||||
INFO: [runtcl-4] Executing : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
|
||||
Command: report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Running Vector-less Activity Propagation...
|
||||
|
||||
Finished Running Vector-less Activity Propagation
|
||||
86 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
report_power completed successfully
|
||||
INFO: [runtcl-4] Executing : report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb
|
||||
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
INFO: [runtcl-4] Executing : report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt
|
||||
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
|
||||
INFO: [runtcl-4] Executing : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt
|
||||
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
INFO: [Common 17-206] Exiting Vivado at Tue Dec 7 12:43:48 2021...
|
||||
@ -1,523 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Tue Dec 7 12:35:58 2021
|
||||
# Process ID: 6484
|
||||
# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1
|
||||
# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace
|
||||
# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi
|
||||
# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source VGA_top.tcl -notrace
|
||||
Command: link_design -top VGA_top -part xc7z010clg400-1
|
||||
Design is defaulting to srcset: sources_1
|
||||
Design is defaulting to constrset: constrs_1
|
||||
INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.dcp' for cell 'U0'
|
||||
INFO: [Netlist 29-17] Analyzing 11 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-479] Netlist was created with Vivado 2018.3
|
||||
INFO: [Device 21-403] Loading part xc7z010clg400-1
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
|
||||
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
|
||||
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
|
||||
INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
|
||||
get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1242.344 ; gain = 551.617
|
||||
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
|
||||
Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
|
||||
Finished Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1242.344 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
link_design completed successfully
|
||||
link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:16 . Memory (MB): peak = 1242.344 ; gain = 879.055
|
||||
Command: opt_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
Running DRC as a precondition to command opt_design
|
||||
|
||||
Starting DRC Task
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Project 1-461] DRC finished with 0 Errors
|
||||
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.520 . Memory (MB): peak = 1242.344 ; gain = 0.000
|
||||
|
||||
Starting Cache Timing Information Task
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [Timing 38-2] Deriving generated clocks
|
||||
Ending Cache Timing Information Task | Checksum: 110b259ca
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1259.379 ; gain = 17.035
|
||||
|
||||
Starting Logic Optimization Task
|
||||
|
||||
Phase 1 Retarget
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Opt 31-49] Retargeted 0 cell(s).
|
||||
Phase 1 Retarget | Checksum: 84bc87f3
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 1 cells
|
||||
INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
||||
|
||||
Phase 2 Constant propagation
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Phase 2 Constant propagation | Checksum: 84bc87f3
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
|
||||
|
||||
Phase 3 Sweep
|
||||
Phase 3 Sweep | Checksum: b8cdff51
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
|
||||
|
||||
Phase 4 BUFG optimization
|
||||
INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG
|
||||
INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets
|
||||
Phase 4 BUFG optimization | Checksum: 37ad6b15
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
|
||||
|
||||
Phase 5 Shift Register Optimization
|
||||
Phase 5 Shift Register Optimization | Checksum: e3a97acd
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
|
||||
|
||||
Phase 6 Post Processing Netlist
|
||||
Phase 6 Post Processing Netlist | Checksum: b120801e
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
|
||||
Opt_design Change Summary
|
||||
=========================
|
||||
|
||||
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Retarget | 0 | 1 | 1 |
|
||||
| Constant propagation | 0 | 0 | 0 |
|
||||
| Sweep | 0 | 0 | 0 |
|
||||
| BUFG optimization | 0 | 0 | 0 |
|
||||
| Shift Register Optimization | 0 | 0 | 0 |
|
||||
| Post Processing Netlist | 0 | 0 | 0 |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
Starting Connectivity Check Task
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
Ending Logic Optimization Task | Checksum: 8a9a4abc
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
|
||||
Starting Power Optimization Task
|
||||
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
|
||||
Ending Power Optimization Task | Checksum: 8a9a4abc
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
|
||||
Starting Final Cleanup Task
|
||||
Ending Final Cleanup Task | Checksum: 8a9a4abc
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
|
||||
Starting Netlist Obfuscation Task
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
Ending Netlist Obfuscation Task | Checksum: 8a9a4abc
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
opt_design completed successfully
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
|
||||
Command: report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt.
|
||||
report_drc completed successfully
|
||||
Command: place_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
Running DRC as a precondition to command place_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Starting Placer Task
|
||||
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
|
||||
|
||||
Phase 1 Placer Initialization
|
||||
|
||||
Phase 1.1 Placer Initialization Netlist Sorting
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 5ce38b0a
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1a81b9fdd
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.245 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
|
||||
Phase 1.3 Build Placer Netlist Model
|
||||
Phase 1.3 Build Placer Netlist Model | Checksum: 2311220d7
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.315 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
|
||||
Phase 1.4 Constrain Clocks/Macros
|
||||
Phase 1.4 Constrain Clocks/Macros | Checksum: 2311220d7
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.316 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
Phase 1 Placer Initialization | Checksum: 2311220d7
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.317 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
|
||||
Phase 2 Global Placement
|
||||
|
||||
Phase 2.1 Floorplanning
|
||||
Phase 2.1 Floorplanning | Checksum: 28f582a8d
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.357 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
|
||||
Phase 2.2 Physical Synthesis In Placer
|
||||
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
|
||||
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
|
||||
INFO: [Physopt 32-949] No candidate nets found for HD net replication
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
|
||||
Summary of Physical Synthesis Optimizations
|
||||
============================================
|
||||
|
||||
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 |
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Phase 2.2 Physical Synthesis In Placer | Checksum: 23519395c
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
Phase 2 Global Placement | Checksum: 2086fb3d6
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
|
||||
Phase 3 Detail Placement
|
||||
|
||||
Phase 3.1 Commit Multi Column Macros
|
||||
Phase 3.1 Commit Multi Column Macros | Checksum: 2086fb3d6
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 295740530
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
|
||||
Phase 3.3 Area Swap Optimization
|
||||
Phase 3.3 Area Swap Optimization | Checksum: 2b6e3c48d
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
|
||||
Phase 3.4 Pipeline Register Optimization
|
||||
Phase 3.4 Pipeline Register Optimization | Checksum: 2b6b80a4e
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
|
||||
Phase 3.5 Small Shape Detail Placement
|
||||
Phase 3.5 Small Shape Detail Placement | Checksum: 15bcefb3a
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
|
||||
Phase 3.6 Re-assign LUT pins
|
||||
Phase 3.6 Re-assign LUT pins | Checksum: 1fcac79aa
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
|
||||
Phase 3.7 Pipeline Register Optimization
|
||||
Phase 3.7 Pipeline Register Optimization | Checksum: 1fc203fe9
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
Phase 3 Detail Placement | Checksum: 1fc203fe9
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
|
||||
Phase 4 Post Placement Optimization and Clean-Up
|
||||
|
||||
Phase 4.1 Post Commit Optimization
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
|
||||
Phase 4.1.1 Post Placement Optimization
|
||||
Post Placement Optimization Initialization | Checksum: 227c33555
|
||||
|
||||
Phase 4.1.1.1 BUFG Insertion
|
||||
INFO: [Place 46-46] BUFG insertion identified 0 candidate nets, 0 success, 0 bufg driver replicated, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason
|
||||
Phase 4.1.1.1 BUFG Insertion | Checksum: 227c33555
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
INFO: [Place 30-746] Post Placement Timing Summary WNS=35.931. For the most accurate timing information please run report_timing.
|
||||
Phase 4.1.1 Post Placement Optimization | Checksum: 21491ebb1
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
Phase 4.1 Post Commit Optimization | Checksum: 21491ebb1
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
|
||||
Phase 4.2 Post Placement Cleanup
|
||||
Phase 4.2 Post Placement Cleanup | Checksum: 21491ebb1
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
|
||||
Phase 4.3 Placer Reporting
|
||||
Phase 4.3 Placer Reporting | Checksum: 21491ebb1
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
|
||||
Phase 4.4 Final Placement Cleanup
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
Phase 4.4 Final Placement Cleanup | Checksum: 1be90c9f9
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1be90c9f9
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
Ending Placer Task | Checksum: e54542d9
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
57 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
place_design completed successfully
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.052 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_io -file VGA_top_io_placed.rpt
|
||||
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb
|
||||
INFO: [runtcl-4] Executing : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt
|
||||
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1342.969 ; gain = 0.000
|
||||
Command: route_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
Running DRC as a precondition to command route_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
|
||||
Starting Routing Task
|
||||
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
|
||||
Checksum: PlaceDB: c930627b ConstDB: 0 ShapeSum: 1c14e05e RouteDB: 0
|
||||
|
||||
Phase 1 Build RT Design
|
||||
Phase 1 Build RT Design | Checksum: 174c0357c
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1409.715 ; gain = 66.746
|
||||
Post Restoration Checksum: NetGraph: ce3f1938 NumContArr: a6811c44 Constraints: 0 Timing: 0
|
||||
|
||||
Phase 2 Router Initialization
|
||||
|
||||
Phase 2.1 Create Timer
|
||||
Phase 2.1 Create Timer | Checksum: 174c0357c
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1440.016 ; gain = 97.047
|
||||
|
||||
Phase 2.2 Fix Topology Constraints
|
||||
Phase 2.2 Fix Topology Constraints | Checksum: 174c0357c
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1446.012 ; gain = 103.043
|
||||
|
||||
Phase 2.3 Pre Route Cleanup
|
||||
Phase 2.3 Pre Route Cleanup | Checksum: 174c0357c
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1446.012 ; gain = 103.043
|
||||
Number of Nodes with overlaps = 0
|
||||
|
||||
Phase 2.4 Update Timing
|
||||
Phase 2.4 Update Timing | Checksum: 18806e6e0
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1448.656 ; gain = 105.688
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=36.010 | TNS=0.000 | WHS=-0.256 | THS=-3.626 |
|
||||
|
||||
Phase 2 Router Initialization | Checksum: 1ffe8b068
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1448.656 ; gain = 105.688
|
||||
|
||||
Phase 3 Initial Routing
|
||||
Phase 3 Initial Routing | Checksum: 203c94bde
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1449.172 ; gain = 106.203
|
||||
|
||||
Phase 4 Rip-up And Reroute
|
||||
|
||||
Phase 4.1 Global Iteration 0
|
||||
Number of Nodes with overlaps = 14
|
||||
Number of Nodes with overlaps = 0
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.090 | TNS=0.000 | WHS=N/A | THS=N/A |
|
||||
|
||||
Phase 4.1 Global Iteration 0 | Checksum: 1a9606839
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1449.172 ; gain = 106.203
|
||||
Phase 4 Rip-up And Reroute | Checksum: 1a9606839
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1449.172 ; gain = 106.203
|
||||
|
||||
Phase 5 Delay and Skew Optimization
|
||||
|
||||
Phase 5.1 Delay CleanUp
|
||||
Phase 5.1 Delay CleanUp | Checksum: 1a9606839
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1449.172 ; gain = 106.203
|
||||
|
||||
Phase 5.2 Clock Skew Optimization
|
||||
Phase 5.2 Clock Skew Optimization | Checksum: 1a9606839
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1449.172 ; gain = 106.203
|
||||
Phase 5 Delay and Skew Optimization | Checksum: 1a9606839
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1449.172 ; gain = 106.203
|
||||
|
||||
Phase 6 Post Hold Fix
|
||||
|
||||
Phase 6.1 Hold Fix Iter
|
||||
|
||||
Phase 6.1.1 Update Timing
|
||||
Phase 6.1.1 Update Timing | Checksum: 1e2322df1
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1449.172 ; gain = 106.203
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.205 | TNS=0.000 | WHS=0.073 | THS=0.000 |
|
||||
|
||||
Phase 6.1 Hold Fix Iter | Checksum: 1e2322df1
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1449.172 ; gain = 106.203
|
||||
Phase 6 Post Hold Fix | Checksum: 1e2322df1
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1449.172 ; gain = 106.203
|
||||
|
||||
Phase 7 Route finalize
|
||||
|
||||
Router Utilization Summary
|
||||
Global Vertical Routing Utilization = 0.0460304 %
|
||||
Global Horizontal Routing Utilization = 0.0457261 %
|
||||
Routable Net Status*
|
||||
*Does not include unroutable nets such as driverless and loadless.
|
||||
Run report_route_status for detailed report.
|
||||
Number of Failed Nets = 0
|
||||
Number of Unrouted Nets = 0
|
||||
Number of Partially Routed Nets = 0
|
||||
Number of Node Overlaps = 0
|
||||
|
||||
Phase 7 Route finalize | Checksum: 181eae35c
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1449.172 ; gain = 106.203
|
||||
|
||||
Phase 8 Verifying routed nets
|
||||
|
||||
Verification completed successfully
|
||||
Phase 8 Verifying routed nets | Checksum: 181eae35c
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1451.223 ; gain = 108.254
|
||||
|
||||
Phase 9 Depositing Routes
|
||||
Phase 9 Depositing Routes | Checksum: 12f7c034c
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1451.223 ; gain = 108.254
|
||||
|
||||
Phase 10 Post Router Timing
|
||||
INFO: [Route 35-57] Estimated Timing Summary | WNS=35.205 | TNS=0.000 | WHS=0.073 | THS=0.000 |
|
||||
|
||||
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
|
||||
Phase 10 Post Router Timing | Checksum: 12f7c034c
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1451.223 ; gain = 108.254
|
||||
INFO: [Route 35-16] Router Completed Successfully
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1451.223 ; gain = 108.254
|
||||
|
||||
Routing Is Done.
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
74 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
route_design completed successfully
|
||||
route_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:22 . Memory (MB): peak = 1451.223 ; gain = 108.254
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1451.223 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.047 . Memory (MB): peak = 1451.637 ; gain = 0.414
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1451.637 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
|
||||
Command: report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt.
|
||||
report_drc completed successfully
|
||||
INFO: [runtcl-4] Executing : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
|
||||
Command: report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [DRC 23-133] Running Methodology with 2 threads
|
||||
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt.
|
||||
report_methodology completed successfully
|
||||
INFO: [runtcl-4] Executing : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
|
||||
Command: report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Running Vector-less Activity Propagation...
|
||||
|
||||
Finished Running Vector-less Activity Propagation
|
||||
86 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
report_power completed successfully
|
||||
INFO: [runtcl-4] Executing : report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb
|
||||
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
INFO: [runtcl-4] Executing : report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt
|
||||
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
|
||||
INFO: [runtcl-4] Executing : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt
|
||||
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
INFO: [Common 17-206] Exiting Vivado at Tue Dec 7 12:36:47 2021...
|
||||
@ -1,529 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Tue Nov 23 10:20:49 2021
|
||||
# Process ID: 8972
|
||||
# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1
|
||||
# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace
|
||||
# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi
|
||||
# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source VGA_top.tcl -notrace
|
||||
Command: link_design -top VGA_top -part xc7z010clg400-1
|
||||
Design is defaulting to srcset: sources_1
|
||||
Design is defaulting to constrset: constrs_1
|
||||
INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.dcp' for cell 'U0'
|
||||
INFO: [Netlist 29-17] Analyzing 3 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-479] Netlist was created with Vivado 2018.3
|
||||
INFO: [Device 21-403] Loading part xc7z010clg400-1
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
|
||||
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
|
||||
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
|
||||
INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
|
||||
get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1224.426 ; gain = 534.145
|
||||
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
|
||||
Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
|
||||
WARNING: [Vivado 12-507] No nets matched 'bouton_down_IBUF'. [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc:12]
|
||||
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc:12]
|
||||
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
||||
WARNING: [Vivado 12-507] No nets matched 'bouton_right_IBUF'. [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc:13]
|
||||
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc:13]
|
||||
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
||||
Finished Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1224.426 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
10 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered.
|
||||
link_design completed successfully
|
||||
link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:24 . Memory (MB): peak = 1224.426 ; gain = 861.312
|
||||
Command: opt_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
Running DRC as a precondition to command opt_design
|
||||
|
||||
Starting DRC Task
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Project 1-461] DRC finished with 0 Errors
|
||||
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.489 . Memory (MB): peak = 1224.426 ; gain = 0.000
|
||||
|
||||
Starting Cache Timing Information Task
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [Timing 38-2] Deriving generated clocks
|
||||
Ending Cache Timing Information Task | Checksum: 5a9f0cbf
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1240.770 ; gain = 16.344
|
||||
|
||||
Starting Logic Optimization Task
|
||||
|
||||
Phase 1 Retarget
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Opt 31-49] Retargeted 0 cell(s).
|
||||
Phase 1 Retarget | Checksum: 5a9f0cbf
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
|
||||
INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
||||
|
||||
Phase 2 Constant propagation
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Phase 2 Constant propagation | Checksum: 5a9f0cbf
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
|
||||
|
||||
Phase 3 Sweep
|
||||
Phase 3 Sweep | Checksum: 117de2bd6
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
|
||||
|
||||
Phase 4 BUFG optimization
|
||||
INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG
|
||||
INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets
|
||||
Phase 4 BUFG optimization | Checksum: 7fbfd86e
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
|
||||
|
||||
Phase 5 Shift Register Optimization
|
||||
Phase 5 Shift Register Optimization | Checksum: 17b01d26a
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
|
||||
|
||||
Phase 6 Post Processing Netlist
|
||||
Phase 6 Post Processing Netlist | Checksum: b289bdf0
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
|
||||
Opt_design Change Summary
|
||||
=========================
|
||||
|
||||
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Retarget | 0 | 0 | 1 |
|
||||
| Constant propagation | 0 | 0 | 0 |
|
||||
| Sweep | 0 | 0 | 0 |
|
||||
| BUFG optimization | 0 | 0 | 0 |
|
||||
| Shift Register Optimization | 0 | 0 | 0 |
|
||||
| Post Processing Netlist | 0 | 0 | 0 |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
Starting Connectivity Check Task
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
Ending Logic Optimization Task | Checksum: a7dcf37c
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
|
||||
Starting Power Optimization Task
|
||||
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
|
||||
Ending Power Optimization Task | Checksum: a7dcf37c
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
|
||||
Starting Final Cleanup Task
|
||||
Ending Final Cleanup Task | Checksum: a7dcf37c
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
|
||||
Starting Netlist Obfuscation Task
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
Ending Netlist Obfuscation Task | Checksum: a7dcf37c
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
30 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered.
|
||||
opt_design completed successfully
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
|
||||
Command: report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt.
|
||||
report_drc completed successfully
|
||||
Command: place_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
Running DRC as a precondition to command place_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Starting Placer Task
|
||||
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
|
||||
|
||||
Phase 1 Placer Initialization
|
||||
|
||||
Phase 1.1 Placer Initialization Netlist Sorting
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a1a0325f
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 11cf26ecf
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.233 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
|
||||
Phase 1.3 Build Placer Netlist Model
|
||||
Phase 1.3 Build Placer Netlist Model | Checksum: 18315a003
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.277 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
|
||||
Phase 1.4 Constrain Clocks/Macros
|
||||
Phase 1.4 Constrain Clocks/Macros | Checksum: 18315a003
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.278 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
Phase 1 Placer Initialization | Checksum: 18315a003
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.279 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
|
||||
Phase 2 Global Placement
|
||||
|
||||
Phase 2.1 Floorplanning
|
||||
Phase 2.1 Floorplanning | Checksum: 1a3a857f8
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.309 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
|
||||
Phase 2.2 Physical Synthesis In Placer
|
||||
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
|
||||
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
|
||||
INFO: [Physopt 32-949] No candidate nets found for HD net replication
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
|
||||
Summary of Physical Synthesis Optimizations
|
||||
============================================
|
||||
|
||||
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 |
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Phase 2.2 Physical Synthesis In Placer | Checksum: 129d92158
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.535 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
Phase 2 Global Placement | Checksum: 15aff6cea
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.545 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
|
||||
Phase 3 Detail Placement
|
||||
|
||||
Phase 3.1 Commit Multi Column Macros
|
||||
Phase 3.1 Commit Multi Column Macros | Checksum: 15aff6cea
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.546 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: e992437f
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.575 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
|
||||
Phase 3.3 Area Swap Optimization
|
||||
Phase 3.3 Area Swap Optimization | Checksum: 125aa6a8c
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.577 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
|
||||
Phase 3.4 Pipeline Register Optimization
|
||||
Phase 3.4 Pipeline Register Optimization | Checksum: 125aa6a8c
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.578 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
|
||||
Phase 3.5 Small Shape Detail Placement
|
||||
Phase 3.5 Small Shape Detail Placement | Checksum: 9d3a0023
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.617 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
|
||||
Phase 3.6 Re-assign LUT pins
|
||||
Phase 3.6 Re-assign LUT pins | Checksum: 100894d91
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.620 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
|
||||
Phase 3.7 Pipeline Register Optimization
|
||||
Phase 3.7 Pipeline Register Optimization | Checksum: 100894d91
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.621 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
Phase 3 Detail Placement | Checksum: 100894d91
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.621 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
|
||||
Phase 4 Post Placement Optimization and Clean-Up
|
||||
|
||||
Phase 4.1 Post Commit Optimization
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
|
||||
Phase 4.1.1 Post Placement Optimization
|
||||
Post Placement Optimization Initialization | Checksum: 1582d7486
|
||||
|
||||
Phase 4.1.1.1 BUFG Insertion
|
||||
INFO: [Place 46-46] BUFG insertion identified 0 candidate nets, 0 success, 0 bufg driver replicated, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason
|
||||
Phase 4.1.1.1 BUFG Insertion | Checksum: 1582d7486
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.652 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
INFO: [Place 30-746] Post Placement Timing Summary WNS=35.525. For the most accurate timing information please run report_timing.
|
||||
Phase 4.1.1 Post Placement Optimization | Checksum: 1fb172a0a
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.652 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
Phase 4.1 Post Commit Optimization | Checksum: 1fb172a0a
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.653 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
|
||||
Phase 4.2 Post Placement Cleanup
|
||||
Phase 4.2 Post Placement Cleanup | Checksum: 1fb172a0a
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.654 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
|
||||
Phase 4.3 Placer Reporting
|
||||
Phase 4.3 Placer Reporting | Checksum: 1fb172a0a
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.655 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
|
||||
Phase 4.4 Final Placement Cleanup
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
Phase 4.4 Final Placement Cleanup | Checksum: 1a5f08b61
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.657 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1a5f08b61
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.657 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
Ending Placer Task | Checksum: ea220969
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.658 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
57 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered.
|
||||
place_design completed successfully
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.379 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 1326.145 ; gain = 0.766
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1326.145 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_io -file VGA_top_io_placed.rpt
|
||||
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1329.160 ; gain = 0.000
|
||||
INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb
|
||||
INFO: [runtcl-4] Executing : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt
|
||||
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1329.160 ; gain = 0.000
|
||||
Command: route_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
Running DRC as a precondition to command route_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
|
||||
Starting Routing Task
|
||||
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
|
||||
Checksum: PlaceDB: 659db238 ConstDB: 0 ShapeSum: 84845731 RouteDB: 0
|
||||
|
||||
Phase 1 Build RT Design
|
||||
Phase 1 Build RT Design | Checksum: e41f4d51
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1401.383 ; gain = 72.223
|
||||
Post Restoration Checksum: NetGraph: 5c55eb1d NumContArr: 87c96234 Constraints: 0 Timing: 0
|
||||
|
||||
Phase 2 Router Initialization
|
||||
|
||||
Phase 2.1 Create Timer
|
||||
Phase 2.1 Create Timer | Checksum: e41f4d51
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1425.637 ; gain = 96.477
|
||||
|
||||
Phase 2.2 Fix Topology Constraints
|
||||
Phase 2.2 Fix Topology Constraints | Checksum: e41f4d51
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1431.664 ; gain = 102.504
|
||||
|
||||
Phase 2.3 Pre Route Cleanup
|
||||
Phase 2.3 Pre Route Cleanup | Checksum: e41f4d51
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1431.664 ; gain = 102.504
|
||||
Number of Nodes with overlaps = 0
|
||||
|
||||
Phase 2.4 Update Timing
|
||||
Phase 2.4 Update Timing | Checksum: 6955b62d
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1434.438 ; gain = 105.277
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.474 | TNS=0.000 | WHS=-0.254 | THS=-3.685 |
|
||||
|
||||
Phase 2 Router Initialization | Checksum: 95e944f1
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1434.438 ; gain = 105.277
|
||||
|
||||
Phase 3 Initial Routing
|
||||
Phase 3 Initial Routing | Checksum: 73b087ef
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1434.438 ; gain = 105.277
|
||||
|
||||
Phase 4 Rip-up And Reroute
|
||||
|
||||
Phase 4.1 Global Iteration 0
|
||||
Number of Nodes with overlaps = 2
|
||||
Number of Nodes with overlaps = 0
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=33.732 | TNS=0.000 | WHS=N/A | THS=N/A |
|
||||
|
||||
Phase 4.1 Global Iteration 0 | Checksum: c2f4c059
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1434.438 ; gain = 105.277
|
||||
Phase 4 Rip-up And Reroute | Checksum: c2f4c059
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1434.438 ; gain = 105.277
|
||||
|
||||
Phase 5 Delay and Skew Optimization
|
||||
|
||||
Phase 5.1 Delay CleanUp
|
||||
Phase 5.1 Delay CleanUp | Checksum: c2f4c059
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1434.438 ; gain = 105.277
|
||||
|
||||
Phase 5.2 Clock Skew Optimization
|
||||
Phase 5.2 Clock Skew Optimization | Checksum: c2f4c059
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1434.438 ; gain = 105.277
|
||||
Phase 5 Delay and Skew Optimization | Checksum: c2f4c059
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1434.438 ; gain = 105.277
|
||||
|
||||
Phase 6 Post Hold Fix
|
||||
|
||||
Phase 6.1 Hold Fix Iter
|
||||
|
||||
Phase 6.1.1 Update Timing
|
||||
Phase 6.1.1 Update Timing | Checksum: 171f06df9
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1434.438 ; gain = 105.277
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=33.848 | TNS=0.000 | WHS=0.048 | THS=0.000 |
|
||||
|
||||
Phase 6.1 Hold Fix Iter | Checksum: 16074e70e
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1434.438 ; gain = 105.277
|
||||
Phase 6 Post Hold Fix | Checksum: 16074e70e
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1434.438 ; gain = 105.277
|
||||
|
||||
Phase 7 Route finalize
|
||||
|
||||
Router Utilization Summary
|
||||
Global Vertical Routing Utilization = 0.0225225 %
|
||||
Global Horizontal Routing Utilization = 0.0140165 %
|
||||
Routable Net Status*
|
||||
*Does not include unroutable nets such as driverless and loadless.
|
||||
Run report_route_status for detailed report.
|
||||
Number of Failed Nets = 0
|
||||
Number of Unrouted Nets = 0
|
||||
Number of Partially Routed Nets = 0
|
||||
Number of Node Overlaps = 0
|
||||
|
||||
Phase 7 Route finalize | Checksum: 16074e70e
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1434.438 ; gain = 105.277
|
||||
|
||||
Phase 8 Verifying routed nets
|
||||
|
||||
Verification completed successfully
|
||||
Phase 8 Verifying routed nets | Checksum: 16074e70e
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1436.086 ; gain = 106.926
|
||||
|
||||
Phase 9 Depositing Routes
|
||||
Phase 9 Depositing Routes | Checksum: 1e005d2dc
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1436.086 ; gain = 106.926
|
||||
|
||||
Phase 10 Post Router Timing
|
||||
INFO: [Route 35-57] Estimated Timing Summary | WNS=33.848 | TNS=0.000 | WHS=0.048 | THS=0.000 |
|
||||
|
||||
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
|
||||
Phase 10 Post Router Timing | Checksum: 1e005d2dc
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1436.086 ; gain = 106.926
|
||||
INFO: [Route 35-16] Router Completed Successfully
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1436.086 ; gain = 106.926
|
||||
|
||||
Routing Is Done.
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
74 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered.
|
||||
route_design completed successfully
|
||||
route_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1436.086 ; gain = 106.926
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1436.086 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1436.758 ; gain = 0.672
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1436.758 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
|
||||
Command: report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt.
|
||||
report_drc completed successfully
|
||||
INFO: [runtcl-4] Executing : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
|
||||
Command: report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [DRC 23-133] Running Methodology with 2 threads
|
||||
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt.
|
||||
report_methodology completed successfully
|
||||
INFO: [runtcl-4] Executing : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
|
||||
Command: report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Running Vector-less Activity Propagation...
|
||||
|
||||
Finished Running Vector-less Activity Propagation
|
||||
86 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered.
|
||||
report_power completed successfully
|
||||
INFO: [runtcl-4] Executing : report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb
|
||||
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
INFO: [runtcl-4] Executing : report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt
|
||||
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
|
||||
INFO: [runtcl-4] Executing : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt
|
||||
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
INFO: [Common 17-206] Exiting Vivado at Tue Nov 23 10:21:35 2021...
|
||||
@ -1,523 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Tue Dec 7 12:26:40 2021
|
||||
# Process ID: 9384
|
||||
# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1
|
||||
# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace
|
||||
# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi
|
||||
# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source VGA_top.tcl -notrace
|
||||
Command: link_design -top VGA_top -part xc7z010clg400-1
|
||||
Design is defaulting to srcset: sources_1
|
||||
Design is defaulting to constrset: constrs_1
|
||||
INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.dcp' for cell 'U0'
|
||||
INFO: [Netlist 29-17] Analyzing 3 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-479] Netlist was created with Vivado 2018.3
|
||||
INFO: [Device 21-403] Loading part xc7z010clg400-1
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
|
||||
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
|
||||
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
|
||||
INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
|
||||
get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1223.977 ; gain = 532.945
|
||||
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
|
||||
Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
|
||||
Finished Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1223.977 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
link_design completed successfully
|
||||
link_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB): peak = 1223.977 ; gain = 860.727
|
||||
Command: opt_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
Running DRC as a precondition to command opt_design
|
||||
|
||||
Starting DRC Task
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Project 1-461] DRC finished with 0 Errors
|
||||
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.512 . Memory (MB): peak = 1223.977 ; gain = 0.000
|
||||
|
||||
Starting Cache Timing Information Task
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [Timing 38-2] Deriving generated clocks
|
||||
Ending Cache Timing Information Task | Checksum: 1e73ff6cd
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1240.598 ; gain = 16.621
|
||||
|
||||
Starting Logic Optimization Task
|
||||
|
||||
Phase 1 Retarget
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Opt 31-49] Retargeted 0 cell(s).
|
||||
Phase 1 Retarget | Checksum: 1e73ff6cd
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
|
||||
INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
||||
|
||||
Phase 2 Constant propagation
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Phase 2 Constant propagation | Checksum: 1e73ff6cd
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
|
||||
|
||||
Phase 3 Sweep
|
||||
Phase 3 Sweep | Checksum: 1b93fc096
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
|
||||
|
||||
Phase 4 BUFG optimization
|
||||
INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG
|
||||
INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets
|
||||
Phase 4 BUFG optimization | Checksum: 17548010c
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
|
||||
|
||||
Phase 5 Shift Register Optimization
|
||||
Phase 5 Shift Register Optimization | Checksum: 112979ec5
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
|
||||
|
||||
Phase 6 Post Processing Netlist
|
||||
Phase 6 Post Processing Netlist | Checksum: dc7cd0a1
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
|
||||
Opt_design Change Summary
|
||||
=========================
|
||||
|
||||
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Retarget | 0 | 0 | 1 |
|
||||
| Constant propagation | 0 | 0 | 0 |
|
||||
| Sweep | 0 | 0 | 0 |
|
||||
| BUFG optimization | 0 | 0 | 0 |
|
||||
| Shift Register Optimization | 0 | 0 | 0 |
|
||||
| Post Processing Netlist | 0 | 0 | 0 |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
Starting Connectivity Check Task
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
Ending Logic Optimization Task | Checksum: 150d68caf
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
|
||||
Starting Power Optimization Task
|
||||
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
|
||||
Ending Power Optimization Task | Checksum: 150d68caf
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
|
||||
Starting Final Cleanup Task
|
||||
Ending Final Cleanup Task | Checksum: 150d68caf
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
|
||||
Starting Netlist Obfuscation Task
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
Ending Netlist Obfuscation Task | Checksum: 150d68caf
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
opt_design completed successfully
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
|
||||
Command: report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt.
|
||||
report_drc completed successfully
|
||||
Command: place_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
Running DRC as a precondition to command place_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Starting Placer Task
|
||||
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
|
||||
|
||||
Phase 1 Placer Initialization
|
||||
|
||||
Phase 1.1 Placer Initialization Netlist Sorting
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: c1eb0453
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 140e33f71
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.241 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
|
||||
Phase 1.3 Build Placer Netlist Model
|
||||
Phase 1.3 Build Placer Netlist Model | Checksum: 1adacafea
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.290 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
|
||||
Phase 1.4 Constrain Clocks/Macros
|
||||
Phase 1.4 Constrain Clocks/Macros | Checksum: 1adacafea
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.291 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
Phase 1 Placer Initialization | Checksum: 1adacafea
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.292 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
|
||||
Phase 2 Global Placement
|
||||
|
||||
Phase 2.1 Floorplanning
|
||||
Phase 2.1 Floorplanning | Checksum: 1ee11f466
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.334 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
|
||||
Phase 2.2 Physical Synthesis In Placer
|
||||
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
|
||||
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
|
||||
INFO: [Physopt 32-949] No candidate nets found for HD net replication
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
|
||||
Summary of Physical Synthesis Optimizations
|
||||
============================================
|
||||
|
||||
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 |
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Phase 2.2 Physical Synthesis In Placer | Checksum: 14964665c
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.673 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
Phase 2 Global Placement | Checksum: 1f3bcd8e6
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.683 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
|
||||
Phase 3 Detail Placement
|
||||
|
||||
Phase 3.1 Commit Multi Column Macros
|
||||
Phase 3.1 Commit Multi Column Macros | Checksum: 1f3bcd8e6
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.684 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 101f41530
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.724 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
|
||||
Phase 3.3 Area Swap Optimization
|
||||
Phase 3.3 Area Swap Optimization | Checksum: 1aa9f5064
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.726 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
|
||||
Phase 3.4 Pipeline Register Optimization
|
||||
Phase 3.4 Pipeline Register Optimization | Checksum: 1aa9f5064
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.726 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
|
||||
Phase 3.5 Small Shape Detail Placement
|
||||
Phase 3.5 Small Shape Detail Placement | Checksum: c56fd17b
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.782 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
|
||||
Phase 3.6 Re-assign LUT pins
|
||||
Phase 3.6 Re-assign LUT pins | Checksum: 10748b914
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.786 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
|
||||
Phase 3.7 Pipeline Register Optimization
|
||||
Phase 3.7 Pipeline Register Optimization | Checksum: 10748b914
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.786 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
Phase 3 Detail Placement | Checksum: 10748b914
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.787 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
|
||||
Phase 4 Post Placement Optimization and Clean-Up
|
||||
|
||||
Phase 4.1 Post Commit Optimization
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
|
||||
Phase 4.1.1 Post Placement Optimization
|
||||
Post Placement Optimization Initialization | Checksum: 1b4de7b32
|
||||
|
||||
Phase 4.1.1.1 BUFG Insertion
|
||||
INFO: [Place 46-46] BUFG insertion identified 0 candidate nets, 0 success, 0 bufg driver replicated, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason
|
||||
Phase 4.1.1.1 BUFG Insertion | Checksum: 1b4de7b32
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.818 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
INFO: [Place 30-746] Post Placement Timing Summary WNS=35.374. For the most accurate timing information please run report_timing.
|
||||
Phase 4.1.1 Post Placement Optimization | Checksum: 1221ff634
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.819 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
Phase 4.1 Post Commit Optimization | Checksum: 1221ff634
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.819 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
|
||||
Phase 4.2 Post Placement Cleanup
|
||||
Phase 4.2 Post Placement Cleanup | Checksum: 1221ff634
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.821 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
|
||||
Phase 4.3 Placer Reporting
|
||||
Phase 4.3 Placer Reporting | Checksum: 1221ff634
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.821 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
|
||||
Phase 4.4 Final Placement Cleanup
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
Phase 4.4 Final Placement Cleanup | Checksum: 11b681dd6
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.823 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 11b681dd6
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.824 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
Ending Placer Task | Checksum: c7f5b6fe
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.825 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
57 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
place_design completed successfully
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.058 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_io -file VGA_top_io_placed.rpt
|
||||
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb
|
||||
INFO: [runtcl-4] Executing : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt
|
||||
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1324.828 ; gain = 0.000
|
||||
Command: route_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
Running DRC as a precondition to command route_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
|
||||
Starting Routing Task
|
||||
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
|
||||
Checksum: PlaceDB: 4cd546ca ConstDB: 0 ShapeSum: 7b207034 RouteDB: 0
|
||||
|
||||
Phase 1 Build RT Design
|
||||
Phase 1 Build RT Design | Checksum: 193e9b080
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1400.352 ; gain = 75.523
|
||||
Post Restoration Checksum: NetGraph: f603a583 NumContArr: 9de60afd Constraints: 0 Timing: 0
|
||||
|
||||
Phase 2 Router Initialization
|
||||
|
||||
Phase 2.1 Create Timer
|
||||
Phase 2.1 Create Timer | Checksum: 193e9b080
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1424.602 ; gain = 99.773
|
||||
|
||||
Phase 2.2 Fix Topology Constraints
|
||||
Phase 2.2 Fix Topology Constraints | Checksum: 193e9b080
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1430.637 ; gain = 105.809
|
||||
|
||||
Phase 2.3 Pre Route Cleanup
|
||||
Phase 2.3 Pre Route Cleanup | Checksum: 193e9b080
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1430.637 ; gain = 105.809
|
||||
Number of Nodes with overlaps = 0
|
||||
|
||||
Phase 2.4 Update Timing
|
||||
Phase 2.4 Update Timing | Checksum: 14d287119
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.406 ; gain = 108.578
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.306 | TNS=0.000 | WHS=-0.280 | THS=-3.042 |
|
||||
|
||||
Phase 2 Router Initialization | Checksum: 11c317e3b
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.406 ; gain = 108.578
|
||||
|
||||
Phase 3 Initial Routing
|
||||
Phase 3 Initial Routing | Checksum: 13856f33e
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.406 ; gain = 108.578
|
||||
|
||||
Phase 4 Rip-up And Reroute
|
||||
|
||||
Phase 4.1 Global Iteration 0
|
||||
Number of Nodes with overlaps = 4
|
||||
Number of Nodes with overlaps = 0
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.229 | TNS=0.000 | WHS=N/A | THS=N/A |
|
||||
|
||||
Phase 4.1 Global Iteration 0 | Checksum: 130baabbd
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.406 ; gain = 108.578
|
||||
Phase 4 Rip-up And Reroute | Checksum: 130baabbd
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.406 ; gain = 108.578
|
||||
|
||||
Phase 5 Delay and Skew Optimization
|
||||
|
||||
Phase 5.1 Delay CleanUp
|
||||
Phase 5.1 Delay CleanUp | Checksum: 130baabbd
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.406 ; gain = 108.578
|
||||
|
||||
Phase 5.2 Clock Skew Optimization
|
||||
Phase 5.2 Clock Skew Optimization | Checksum: 130baabbd
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.406 ; gain = 108.578
|
||||
Phase 5 Delay and Skew Optimization | Checksum: 130baabbd
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.406 ; gain = 108.578
|
||||
|
||||
Phase 6 Post Hold Fix
|
||||
|
||||
Phase 6.1 Hold Fix Iter
|
||||
|
||||
Phase 6.1.1 Update Timing
|
||||
Phase 6.1.1 Update Timing | Checksum: 92f99af8
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.406 ; gain = 108.578
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.382 | TNS=0.000 | WHS=0.073 | THS=0.000 |
|
||||
|
||||
Phase 6.1 Hold Fix Iter | Checksum: 92f99af8
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.406 ; gain = 108.578
|
||||
Phase 6 Post Hold Fix | Checksum: 92f99af8
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.406 ; gain = 108.578
|
||||
|
||||
Phase 7 Route finalize
|
||||
|
||||
Router Utilization Summary
|
||||
Global Vertical Routing Utilization = 0.019848 %
|
||||
Global Horizontal Routing Utilization = 0.0151654 %
|
||||
Routable Net Status*
|
||||
*Does not include unroutable nets such as driverless and loadless.
|
||||
Run report_route_status for detailed report.
|
||||
Number of Failed Nets = 0
|
||||
Number of Unrouted Nets = 0
|
||||
Number of Partially Routed Nets = 0
|
||||
Number of Node Overlaps = 0
|
||||
|
||||
Phase 7 Route finalize | Checksum: 1561952c6
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.406 ; gain = 108.578
|
||||
|
||||
Phase 8 Verifying routed nets
|
||||
|
||||
Verification completed successfully
|
||||
Phase 8 Verifying routed nets | Checksum: 1561952c6
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1434.938 ; gain = 110.109
|
||||
|
||||
Phase 9 Depositing Routes
|
||||
Phase 9 Depositing Routes | Checksum: 242e77cc4
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1434.938 ; gain = 110.109
|
||||
|
||||
Phase 10 Post Router Timing
|
||||
INFO: [Route 35-57] Estimated Timing Summary | WNS=35.382 | TNS=0.000 | WHS=0.073 | THS=0.000 |
|
||||
|
||||
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
|
||||
Phase 10 Post Router Timing | Checksum: 242e77cc4
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1434.938 ; gain = 110.109
|
||||
INFO: [Route 35-16] Router Completed Successfully
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1434.938 ; gain = 110.109
|
||||
|
||||
Routing Is Done.
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
74 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
route_design completed successfully
|
||||
route_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:23 . Memory (MB): peak = 1434.938 ; gain = 110.109
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1434.938 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 1435.922 ; gain = 0.984
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1435.922 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
|
||||
Command: report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt.
|
||||
report_drc completed successfully
|
||||
INFO: [runtcl-4] Executing : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
|
||||
Command: report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [DRC 23-133] Running Methodology with 2 threads
|
||||
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt.
|
||||
report_methodology completed successfully
|
||||
INFO: [runtcl-4] Executing : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
|
||||
Command: report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Running Vector-less Activity Propagation...
|
||||
|
||||
Finished Running Vector-less Activity Propagation
|
||||
86 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
report_power completed successfully
|
||||
INFO: [runtcl-4] Executing : report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb
|
||||
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
INFO: [runtcl-4] Executing : report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt
|
||||
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
|
||||
INFO: [runtcl-4] Executing : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt
|
||||
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
INFO: [Common 17-206] Exiting Vivado at Tue Dec 7 12:27:29 2021...
|
||||
@ -1,545 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Tue Nov 23 10:14:24 2021
|
||||
# Process ID: 9960
|
||||
# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1
|
||||
# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace
|
||||
# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi
|
||||
# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source VGA_top.tcl -notrace
|
||||
Command: link_design -top VGA_top -part xc7z010clg400-1
|
||||
Design is defaulting to srcset: sources_1
|
||||
Design is defaulting to constrset: constrs_1
|
||||
INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.dcp' for cell 'U0'
|
||||
INFO: [Netlist 29-17] Analyzing 11 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-479] Netlist was created with Vivado 2018.3
|
||||
INFO: [Device 21-403] Loading part xc7z010clg400-1
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
|
||||
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
|
||||
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
|
||||
INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
|
||||
get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1242.402 ; gain = 551.609
|
||||
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
|
||||
Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
|
||||
Finished Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1242.402 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
link_design completed successfully
|
||||
link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:24 . Memory (MB): peak = 1242.402 ; gain = 879.289
|
||||
Command: opt_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
Running DRC as a precondition to command opt_design
|
||||
|
||||
Starting DRC Task
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Project 1-461] DRC finished with 0 Errors
|
||||
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.496 . Memory (MB): peak = 1242.402 ; gain = 0.000
|
||||
|
||||
Starting Cache Timing Information Task
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [Timing 38-2] Deriving generated clocks
|
||||
Ending Cache Timing Information Task | Checksum: b8ea7a4e
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1257.285 ; gain = 14.883
|
||||
|
||||
Starting Logic Optimization Task
|
||||
|
||||
Phase 1 Retarget
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Opt 31-49] Retargeted 0 cell(s).
|
||||
Phase 1 Retarget | Checksum: b8ea7a4e
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
|
||||
INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
||||
|
||||
Phase 2 Constant propagation
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Phase 2 Constant propagation | Checksum: b8ea7a4e
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
|
||||
|
||||
Phase 3 Sweep
|
||||
Phase 3 Sweep | Checksum: 69d8ab95
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
|
||||
|
||||
Phase 4 BUFG optimization
|
||||
INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG
|
||||
INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets
|
||||
Phase 4 BUFG optimization | Checksum: 13bee9dc1
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
|
||||
|
||||
Phase 5 Shift Register Optimization
|
||||
Phase 5 Shift Register Optimization | Checksum: 1a59d5459
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
|
||||
|
||||
Phase 6 Post Processing Netlist
|
||||
Phase 6 Post Processing Netlist | Checksum: 14a40c514
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
|
||||
Opt_design Change Summary
|
||||
=========================
|
||||
|
||||
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Retarget | 0 | 0 | 1 |
|
||||
| Constant propagation | 0 | 0 | 0 |
|
||||
| Sweep | 0 | 0 | 0 |
|
||||
| BUFG optimization | 0 | 0 | 0 |
|
||||
| Shift Register Optimization | 0 | 0 | 0 |
|
||||
| Post Processing Netlist | 0 | 0 | 0 |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
Starting Connectivity Check Task
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
Ending Logic Optimization Task | Checksum: 14dbbd0bc
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
|
||||
Starting Power Optimization Task
|
||||
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
|
||||
Ending Power Optimization Task | Checksum: 14dbbd0bc
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
|
||||
Starting Final Cleanup Task
|
||||
Ending Final Cleanup Task | Checksum: 14dbbd0bc
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
|
||||
Starting Netlist Obfuscation Task
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
Ending Netlist Obfuscation Task | Checksum: 14dbbd0bc
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
opt_design completed successfully
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.044 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
|
||||
Command: report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt.
|
||||
report_drc completed successfully
|
||||
Command: place_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
Running DRC as a precondition to command place_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Starting Placer Task
|
||||
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
|
||||
|
||||
Phase 1 Placer Initialization
|
||||
|
||||
Phase 1.1 Placer Initialization Netlist Sorting
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fa6d7a79
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.
|
||||
|
||||
bouton_down_IBUF_inst (IBUF.O) is locked to IOB_X0Y1
|
||||
bouton_down_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y1
|
||||
Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin.
|
||||
WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.
|
||||
|
||||
bouton_right_IBUF_inst (IBUF.O) is locked to IOB_X0Y36
|
||||
bouton_right_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0
|
||||
Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin.
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 12622357c
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.297 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
|
||||
Phase 1.3 Build Placer Netlist Model
|
||||
Phase 1.3 Build Placer Netlist Model | Checksum: 1b3b55d5e
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.356 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
|
||||
Phase 1.4 Constrain Clocks/Macros
|
||||
Phase 1.4 Constrain Clocks/Macros | Checksum: 1b3b55d5e
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.357 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
Phase 1 Placer Initialization | Checksum: 1b3b55d5e
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.357 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
|
||||
Phase 2 Global Placement
|
||||
|
||||
Phase 2.1 Floorplanning
|
||||
Phase 2.1 Floorplanning | Checksum: 1f34e0130
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.388 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
|
||||
Phase 2.2 Physical Synthesis In Placer
|
||||
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
|
||||
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
|
||||
INFO: [Physopt 32-949] No candidate nets found for HD net replication
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
|
||||
Summary of Physical Synthesis Optimizations
|
||||
============================================
|
||||
|
||||
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 |
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Phase 2.2 Physical Synthesis In Placer | Checksum: 1f822ab4a
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.902 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
Phase 2 Global Placement | Checksum: 17fde1b87
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.913 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
|
||||
Phase 3 Detail Placement
|
||||
|
||||
Phase 3.1 Commit Multi Column Macros
|
||||
Phase 3.1 Commit Multi Column Macros | Checksum: 17fde1b87
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.914 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 258919723
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.947 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
|
||||
Phase 3.3 Area Swap Optimization
|
||||
Phase 3.3 Area Swap Optimization | Checksum: 1af65d909
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.949 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
|
||||
Phase 3.4 Pipeline Register Optimization
|
||||
Phase 3.4 Pipeline Register Optimization | Checksum: 245deb5d9
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.950 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
|
||||
Phase 3.5 Small Shape Detail Placement
|
||||
Phase 3.5 Small Shape Detail Placement | Checksum: 1dab8f54b
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
|
||||
Phase 3.6 Re-assign LUT pins
|
||||
Phase 3.6 Re-assign LUT pins | Checksum: 1e1eee966
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
|
||||
Phase 3.7 Pipeline Register Optimization
|
||||
Phase 3.7 Pipeline Register Optimization | Checksum: f76e0896
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
Phase 3 Detail Placement | Checksum: f76e0896
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
|
||||
Phase 4 Post Placement Optimization and Clean-Up
|
||||
|
||||
Phase 4.1 Post Commit Optimization
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
|
||||
Phase 4.1.1 Post Placement Optimization
|
||||
Post Placement Optimization Initialization | Checksum: 13e7bd2c2
|
||||
|
||||
Phase 4.1.1.1 BUFG Insertion
|
||||
INFO: [Place 46-46] BUFG insertion identified 0 candidate nets, 0 success, 0 bufg driver replicated, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason
|
||||
Phase 4.1.1.1 BUFG Insertion | Checksum: 13e7bd2c2
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
INFO: [Place 30-746] Post Placement Timing Summary WNS=35.645. For the most accurate timing information please run report_timing.
|
||||
Phase 4.1.1 Post Placement Optimization | Checksum: 15c183492
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
Phase 4.1 Post Commit Optimization | Checksum: 15c183492
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
|
||||
Phase 4.2 Post Placement Cleanup
|
||||
Phase 4.2 Post Placement Cleanup | Checksum: 15c183492
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
|
||||
Phase 4.3 Placer Reporting
|
||||
Phase 4.3 Placer Reporting | Checksum: 15c183492
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
|
||||
Phase 4.4 Final Placement Cleanup
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
Phase 4.4 Final Placement Cleanup | Checksum: 17d5ce04d
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 17d5ce04d
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
Ending Placer Task | Checksum: d443f812
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
57 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
place_design completed successfully
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.043 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_io -file VGA_top_io_placed.rpt
|
||||
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb
|
||||
INFO: [runtcl-4] Executing : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt
|
||||
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.895 ; gain = 0.000
|
||||
Command: route_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
Running DRC as a precondition to command route_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG.
|
||||
Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin.
|
||||
This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.
|
||||
|
||||
bouton_down_IBUF_inst (IBUF.O) is locked to IOB_X0Y1
|
||||
bouton_down_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y1
|
||||
WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG.
|
||||
Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin.
|
||||
This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.
|
||||
|
||||
bouton_right_IBUF_inst (IBUF.O) is locked to IOB_X0Y36
|
||||
bouton_right_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 2 Warnings
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
|
||||
Starting Routing Task
|
||||
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
|
||||
Checksum: PlaceDB: 52480e80 ConstDB: 0 ShapeSum: 81fbe992 RouteDB: 0
|
||||
|
||||
Phase 1 Build RT Design
|
||||
Phase 1 Build RT Design | Checksum: fee31c87
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1411.523 ; gain = 68.629
|
||||
Post Restoration Checksum: NetGraph: e323ff66 NumContArr: 1bbf1d21 Constraints: 0 Timing: 0
|
||||
|
||||
Phase 2 Router Initialization
|
||||
|
||||
Phase 2.1 Create Timer
|
||||
Phase 2.1 Create Timer | Checksum: fee31c87
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1441.797 ; gain = 98.902
|
||||
|
||||
Phase 2.2 Fix Topology Constraints
|
||||
Phase 2.2 Fix Topology Constraints | Checksum: fee31c87
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1447.852 ; gain = 104.957
|
||||
|
||||
Phase 2.3 Pre Route Cleanup
|
||||
Phase 2.3 Pre Route Cleanup | Checksum: fee31c87
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1447.852 ; gain = 104.957
|
||||
Number of Nodes with overlaps = 0
|
||||
|
||||
Phase 2.4 Update Timing
|
||||
Phase 2.4 Update Timing | Checksum: 1441c14dd
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1451.789 ; gain = 108.895
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.769 | TNS=0.000 | WHS=-0.258 | THS=-3.023 |
|
||||
|
||||
Phase 2 Router Initialization | Checksum: 173a347ed
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1451.789 ; gain = 108.895
|
||||
|
||||
Phase 3 Initial Routing
|
||||
Phase 3 Initial Routing | Checksum: 205eb8b74
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1452.559 ; gain = 109.664
|
||||
|
||||
Phase 4 Rip-up And Reroute
|
||||
|
||||
Phase 4.1 Global Iteration 0
|
||||
Number of Nodes with overlaps = 17
|
||||
Number of Nodes with overlaps = 0
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.132 | TNS=0.000 | WHS=N/A | THS=N/A |
|
||||
|
||||
Phase 4.1 Global Iteration 0 | Checksum: 2843d0f71
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1452.559 ; gain = 109.664
|
||||
Phase 4 Rip-up And Reroute | Checksum: 2843d0f71
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1452.559 ; gain = 109.664
|
||||
|
||||
Phase 5 Delay and Skew Optimization
|
||||
|
||||
Phase 5.1 Delay CleanUp
|
||||
Phase 5.1 Delay CleanUp | Checksum: 2843d0f71
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1452.559 ; gain = 109.664
|
||||
|
||||
Phase 5.2 Clock Skew Optimization
|
||||
Phase 5.2 Clock Skew Optimization | Checksum: 2843d0f71
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1452.559 ; gain = 109.664
|
||||
Phase 5 Delay and Skew Optimization | Checksum: 2843d0f71
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1452.559 ; gain = 109.664
|
||||
|
||||
Phase 6 Post Hold Fix
|
||||
|
||||
Phase 6.1 Hold Fix Iter
|
||||
|
||||
Phase 6.1.1 Update Timing
|
||||
Phase 6.1.1 Update Timing | Checksum: 1adede088
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1452.559 ; gain = 109.664
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.132 | TNS=0.000 | WHS=0.069 | THS=0.000 |
|
||||
|
||||
Phase 6.1 Hold Fix Iter | Checksum: 1adede088
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1452.559 ; gain = 109.664
|
||||
Phase 6 Post Hold Fix | Checksum: 1adede088
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1452.559 ; gain = 109.664
|
||||
|
||||
Phase 7 Route finalize
|
||||
|
||||
Router Utilization Summary
|
||||
Global Vertical Routing Utilization = 0.0615146 %
|
||||
Global Horizontal Routing Utilization = 0.0558364 %
|
||||
Routable Net Status*
|
||||
*Does not include unroutable nets such as driverless and loadless.
|
||||
Run report_route_status for detailed report.
|
||||
Number of Failed Nets = 0
|
||||
Number of Unrouted Nets = 0
|
||||
Number of Partially Routed Nets = 0
|
||||
Number of Node Overlaps = 0
|
||||
|
||||
Phase 7 Route finalize | Checksum: 2005f65b4
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1452.559 ; gain = 109.664
|
||||
|
||||
Phase 8 Verifying routed nets
|
||||
|
||||
Verification completed successfully
|
||||
Phase 8 Verifying routed nets | Checksum: 2005f65b4
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1453.578 ; gain = 110.684
|
||||
|
||||
Phase 9 Depositing Routes
|
||||
Phase 9 Depositing Routes | Checksum: 18ba5fe80
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1453.578 ; gain = 110.684
|
||||
|
||||
Phase 10 Post Router Timing
|
||||
INFO: [Route 35-57] Estimated Timing Summary | WNS=35.132 | TNS=0.000 | WHS=0.069 | THS=0.000 |
|
||||
|
||||
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
|
||||
Phase 10 Post Router Timing | Checksum: 18ba5fe80
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1453.578 ; gain = 110.684
|
||||
INFO: [Route 35-16] Router Completed Successfully
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1453.578 ; gain = 110.684
|
||||
|
||||
Routing Is Done.
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
74 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
route_design completed successfully
|
||||
route_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1453.578 ; gain = 110.684
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1453.578 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 1454.922 ; gain = 1.344
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1454.922 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
|
||||
Command: report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt.
|
||||
report_drc completed successfully
|
||||
INFO: [runtcl-4] Executing : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
|
||||
Command: report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [DRC 23-133] Running Methodology with 2 threads
|
||||
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt.
|
||||
report_methodology completed successfully
|
||||
INFO: [runtcl-4] Executing : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
|
||||
Command: report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Running Vector-less Activity Propagation...
|
||||
|
||||
Finished Running Vector-less Activity Propagation
|
||||
86 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
report_power completed successfully
|
||||
INFO: [runtcl-4] Executing : report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb
|
||||
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
INFO: [runtcl-4] Executing : report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt
|
||||
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
|
||||
INFO: [runtcl-4] Executing : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt
|
||||
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
INFO: [Common 17-206] Exiting Vivado at Tue Nov 23 10:15:11 2021...
|
||||
@ -1,8 +1,8 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
|
||||
| Date : Tue Dec 7 12:43:48 2021
|
||||
| Host : irb121-02-w running 64-bit major release (build 9200)
|
||||
| Date : Tue Jan 4 12:21:25 2022
|
||||
| Host : irb121-12-w running 64-bit major release (build 9200)
|
||||
| Command : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx
|
||||
| Design : VGA_top
|
||||
| Device : 7z010-clg400
|
||||
|
||||
Binary file not shown.
@ -1,8 +1,8 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
-------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
|
||||
| Date : Tue Dec 7 12:43:48 2021
|
||||
| Host : irb121-02-w running 64-bit major release (build 9200)
|
||||
| Date : Tue Jan 4 12:21:25 2022
|
||||
| Host : irb121-12-w running 64-bit major release (build 9200)
|
||||
| Command : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt
|
||||
| Design : VGA_top
|
||||
| Device : 7z010-clg400
|
||||
@ -16,12 +16,15 @@ Table of Contents
|
||||
1. Clock Primitive Utilization
|
||||
2. Global Clock Resources
|
||||
3. Global Clock Source Details
|
||||
4. Clock Regions: Key Resource Utilization
|
||||
5. Clock Regions : Global Clock Summary
|
||||
6. Device Cell Placement Summary for Global Clock g0
|
||||
7. Device Cell Placement Summary for Global Clock g1
|
||||
8. Clock Region Cell Placement per Global Clock: Region X1Y0
|
||||
9. Clock Region Cell Placement per Global Clock: Region X1Y1
|
||||
4. Local Clock Details
|
||||
5. Clock Regions: Key Resource Utilization
|
||||
6. Clock Regions : Global Clock Summary
|
||||
7. Device Cell Placement Summary for Global Clock g0
|
||||
8. Device Cell Placement Summary for Global Clock g1
|
||||
9. Device Cell Placement Summary for Global Clock g2
|
||||
10. Clock Region Cell Placement per Global Clock: Region X0Y0
|
||||
11. Clock Region Cell Placement per Global Clock: Region X1Y0
|
||||
12. Clock Region Cell Placement per Global Clock: Region X1Y1
|
||||
|
||||
1. Clock Primitive Utilization
|
||||
------------------------------
|
||||
@ -29,7 +32,7 @@ Table of Contents
|
||||
+----------+------+-----------+-----+--------------+--------+
|
||||
| Type | Used | Available | LOC | Clock Region | Pblock |
|
||||
+----------+------+-----------+-----+--------------+--------+
|
||||
| BUFGCTRL | 2 | 32 | 0 | 0 | 0 |
|
||||
| BUFGCTRL | 3 | 32 | 0 | 0 | 0 |
|
||||
| BUFH | 0 | 48 | 0 | 0 | 0 |
|
||||
| BUFIO | 0 | 8 | 0 | 0 | 0 |
|
||||
| BUFMR | 0 | 4 | 0 | 0 | 0 |
|
||||
@ -42,12 +45,13 @@ Table of Contents
|
||||
2. Global Clock Resources
|
||||
-------------------------
|
||||
|
||||
+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+----------+-----------------------+--------------------------------+
|
||||
| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
|
||||
+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+----------+-----------------------+--------------------------------+
|
||||
| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y16 | n/a | 2 | 21 | 0 | 40.000 | Multiple | U0/inst/clkout1_buf/O | U0/inst/clk_out1 |
|
||||
| g1 | src0 | BUFG/O | None | BUFGCTRL_X0Y17 | n/a | 1 | 1 | 0 | 40.000 | Multiple | U0/inst/clkf_buf/O | U0/inst/clkfbout_buf_clk_wiz_1 |
|
||||
+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+----------+-----------------------+--------------------------------+
|
||||
+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+--------------------+--------------------------+--------------------------------+
|
||||
| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
|
||||
+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+--------------------+--------------------------+--------------------------------+
|
||||
| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y16 | n/a | 3 | 184 | 0 | 8.000 | sys_clk_pin | H125MHz_IBUF_BUFG_inst/O | H125MHz_IBUF_BUFG |
|
||||
| g1 | src1 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 3 | 60 | 0 | 40.000 | clk_out1_clk_wiz_1 | U0/inst/clkout1_buf/O | U0/inst/clk_out1 |
|
||||
| g2 | src1 | BUFG/O | None | BUFGCTRL_X0Y1 | n/a | 1 | 1 | 0 | 40.000 | clkfbout_clk_wiz_1 | U0/inst/clkf_buf/O | U0/inst/clkfbout_buf_clk_wiz_1 |
|
||||
+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+--------------------+--------------------------+--------------------------------+
|
||||
* Clock Loads column represents the clock pin loads (pin count)
|
||||
** Non-Clock Loads column represents the non-clock pin loads (pin count)
|
||||
|
||||
@ -55,17 +59,31 @@ Table of Contents
|
||||
3. Global Clock Source Details
|
||||
------------------------------
|
||||
|
||||
+-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------+--------------------------------+----------------------------+
|
||||
| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
|
||||
+-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------+--------------------------------+----------------------------+
|
||||
| src0 | g0 | MMCME2_ADV/CLKOUT0 | None | MMCME2_ADV_X0Y1 | X1Y1 | 1 | 0 | 40.000 | Multiple | U0/inst/mmcm_adv_inst/CLKOUT0 | U0/inst/clk_out1_clk_wiz_1 |
|
||||
| src0 | g1 | MMCME2_ADV/CLKFBOUT | None | MMCME2_ADV_X0Y1 | X1Y1 | 1 | 0 | 40.000 | Multiple | U0/inst/mmcm_adv_inst/CLKFBOUT | U0/inst/clkfbout_clk_wiz_1 |
|
||||
+-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------+--------------------------------+----------------------------+
|
||||
+-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+--------------------------------+----------------------------+
|
||||
| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
|
||||
+-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+--------------------------------+----------------------------+
|
||||
| src0 | g0 | IBUF/O | IOB_X0Y78 | IOB_X0Y78 | X1Y1 | 1 | 0 | 8.000 | sys_clk_pin | H125MHz_IBUF_inst/O | H125MHz_IBUF |
|
||||
| src1 | g1 | MMCME2_ADV/CLKOUT0 | None | MMCME2_ADV_X0Y0 | X1Y0 | 1 | 0 | 40.000 | clk_out1_clk_wiz_1 | U0/inst/mmcm_adv_inst/CLKOUT0 | U0/inst/clk_out1_clk_wiz_1 |
|
||||
| src1 | g2 | MMCME2_ADV/CLKFBOUT | None | MMCME2_ADV_X0Y0 | X1Y0 | 1 | 0 | 40.000 | clkfbout_clk_wiz_1 | U0/inst/mmcm_adv_inst/CLKFBOUT | U0/inst/clkfbout_clk_wiz_1 |
|
||||
+-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+--------------------------------+----------------------------+
|
||||
* Clock Loads column represents the clock pin loads (pin count)
|
||||
** Non-Clock Loads column represents the non-clock pin loads (pin count)
|
||||
|
||||
|
||||
4. Clock Regions: Key Resource Utilization
|
||||
4. Local Clock Details
|
||||
----------------------
|
||||
|
||||
+----------+-----------------+------------+------------------+--------------+-------------+-----------------+--------------+-------+------------------+------------+
|
||||
| Local Id | Driver Type/Pin | Constraint | Site/BEL | Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
|
||||
+----------+-----------------+------------+------------------+--------------+-------------+-----------------+--------------+-------+------------------+------------||
|
||||
| 0 | FDRE/Q | None | SLICE_X8Y34/A5FF | X0Y0 | 17 | 29 | | | UPD/update_reg/Q | UPD/update - Static -
|
||||
+----------+-----------------+------------+------------------+--------------+-------------+-----------------+--------------+-------+------------------+------------||
|
||||
* Local Clocks in this context represents only clocks driven by non-global buffers
|
||||
** Clock Loads column represents the clock pin loads (pin count)
|
||||
*** Non-Clock Loads column represents the non-clock pin loads (pin count)
|
||||
|
||||
|
||||
5. Clock Regions: Key Resource Utilization
|
||||
------------------------------------------
|
||||
|
||||
+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
|
||||
@ -73,15 +91,15 @@ Table of Contents
|
||||
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
|
||||
| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
|
||||
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
|
||||
| X0Y0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1100 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
|
||||
| X1Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 3 | 1100 | 1 | 350 | 0 | 40 | 0 | 20 | 0 | 20 |
|
||||
| X0Y0 | 2 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 76 | 1100 | 63 | 400 | 1 | 20 | 6 | 10 | 0 | 20 |
|
||||
| X1Y0 | 3 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 80 | 1100 | 29 | 350 | 3 | 40 | 12 | 20 | 0 | 20 |
|
||||
| X0Y1 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1100 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
|
||||
| X1Y1 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 18 | 1100 | 3 | 350 | 0 | 40 | 0 | 20 | 0 | 20 |
|
||||
| X1Y1 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 33 | 1100 | 8 | 350 | 0 | 40 | 0 | 20 | 0 | 20 |
|
||||
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
|
||||
* Global Clock column represents track count; while other columns represents cell counts
|
||||
|
||||
|
||||
5. Clock Regions : Global Clock Summary
|
||||
6. Clock Regions : Global Clock Summary
|
||||
---------------------------------------
|
||||
|
||||
All Modules
|
||||
@ -89,40 +107,62 @@ All Modules
|
||||
| | X0 | X1 |
|
||||
+----+----+----+
|
||||
| Y1 | 0 | 2 |
|
||||
| Y0 | 0 | 1 |
|
||||
| Y0 | 2 | 3 |
|
||||
+----+----+----+
|
||||
|
||||
|
||||
6. Device Cell Placement Summary for Global Clock g0
|
||||
7. Device Cell Placement Summary for Global Clock g0
|
||||
----------------------------------------------------
|
||||
|
||||
+-----------+-----------------+-------------------+----------+-------------+----------------+-------------+----------+----------------+----------+------------------+
|
||||
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
|
||||
+-----------+-----------------+-------------------+----------+-------------+----------------+-------------+----------+----------------+----------+------------------+
|
||||
| g0 | BUFG/O | n/a | Multiple | 40.000 | {0.000 20.000} | 21 | 0 | 0 | 0 | U0/inst/clk_out1 |
|
||||
+-----------+-----------------+-------------------+----------+-------------+----------------+-------------+----------+----------------+----------+------------------+
|
||||
+-----------+-----------------+-------------------+-------------+-------------+---------------+-------------+----------+----------------+----------+-------------------+
|
||||
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
|
||||
+-----------+-----------------+-------------------+-------------+-------------+---------------+-------------+----------+----------------+----------+-------------------+
|
||||
| g0 | BUFG/O | n/a | sys_clk_pin | 8.000 | {0.000 4.000} | 156 | 0 | 1 | 0 | H125MHz_IBUF_BUFG |
|
||||
+-----------+-----------------+-------------------+-------------+-------------+---------------+-------------+----------+----------------+----------+-------------------+
|
||||
* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources
|
||||
** IO Loads column represents load cell count of IO types
|
||||
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
|
||||
**** GT Loads column represents load cell count of GT types
|
||||
|
||||
|
||||
+----+----+-----+
|
||||
| | X0 | X1 |
|
||||
+----+----+-----+
|
||||
| Y1 | 0 | 18 |
|
||||
| Y0 | 0 | 3 |
|
||||
+----+----+-----+
|
||||
+----+-----+-----+
|
||||
| | X0 | X1 |
|
||||
+----+-----+-----+
|
||||
| Y1 | 0 | 8 |
|
||||
| Y0 | 74 | 75 |
|
||||
+----+-----+-----+
|
||||
|
||||
|
||||
7. Device Cell Placement Summary for Global Clock g1
|
||||
8. Device Cell Placement Summary for Global Clock g1
|
||||
----------------------------------------------------
|
||||
|
||||
+-----------+-----------------+-------------------+----------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
|
||||
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
|
||||
+-----------+-----------------+-------------------+----------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
|
||||
| g1 | BUFG/O | n/a | Multiple | 40.000 | {0.000 20.000} | 0 | 0 | 1 | 0 | U0/inst/clkfbout_buf_clk_wiz_1 |
|
||||
+-----------+-----------------+-------------------+----------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
|
||||
+-----------+-----------------+-------------------+--------------------+-------------+----------------+-------------+----------+----------------+----------+------------------+
|
||||
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
|
||||
+-----------+-----------------+-------------------+--------------------+-------------+----------------+-------------+----------+----------------+----------+------------------+
|
||||
| g1 | BUFG/O | n/a | clk_out1_clk_wiz_1 | 40.000 | {0.000 20.000} | 60 | 0 | 0 | 0 | U0/inst/clk_out1 |
|
||||
+-----------+-----------------+-------------------+--------------------+-------------+----------------+-------------+----------+----------------+----------+------------------+
|
||||
* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources
|
||||
** IO Loads column represents load cell count of IO types
|
||||
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
|
||||
**** GT Loads column represents load cell count of GT types
|
||||
|
||||
|
||||
+----+-----+-----+
|
||||
| | X0 | X1 |
|
||||
+----+-----+-----+
|
||||
| Y1 | 0 | 25 |
|
||||
| Y0 | 10 | 25 |
|
||||
+----+-----+-----+
|
||||
|
||||
|
||||
9. Device Cell Placement Summary for Global Clock g2
|
||||
----------------------------------------------------
|
||||
|
||||
+-----------+-----------------+-------------------+--------------------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
|
||||
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
|
||||
+-----------+-----------------+-------------------+--------------------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
|
||||
| g2 | BUFG/O | n/a | clkfbout_clk_wiz_1 | 40.000 | {0.000 20.000} | 0 | 0 | 1 | 0 | U0/inst/clkfbout_buf_clk_wiz_1 |
|
||||
+-----------+-----------------+-------------------+--------------------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
|
||||
* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources
|
||||
** IO Loads column represents load cell count of IO types
|
||||
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
|
||||
@ -132,51 +172,75 @@ All Modules
|
||||
+----+----+----+
|
||||
| | X0 | X1 |
|
||||
+----+----+----+
|
||||
| Y1 | 0 | 1 |
|
||||
| Y0 | 0 | 0 |
|
||||
| Y1 | 0 | 0 |
|
||||
| Y0 | 0 | 1 |
|
||||
+----+----+----+
|
||||
|
||||
|
||||
8. Clock Region Cell Placement per Global Clock: Region X1Y0
|
||||
------------------------------------------------------------
|
||||
10. Clock Region Cell Placement per Global Clock: Region X0Y0
|
||||
-------------------------------------------------------------
|
||||
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------+
|
||||
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------+
|
||||
| g0 | n/a | BUFG/O | None | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | U0/inst/clk_out1 |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------+
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------+
|
||||
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------+
|
||||
| g0 | n/a | BUFG/O | None | 74 | 0 | 66 | 0 | 7 | 0 | 0 | 0 | 0 | 0 | H125MHz_IBUF_BUFG |
|
||||
| g1 | n/a | BUFG/O | None | 10 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | U0/inst/clk_out1 |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------+
|
||||
* Clock Loads column represents the clock pin loads (pin count)
|
||||
** Non-Clock Loads column represents the non-clock pin loads (pin count)
|
||||
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
|
||||
|
||||
|
||||
9. Clock Region Cell Placement per Global Clock: Region X1Y1
|
||||
------------------------------------------------------------
|
||||
11. Clock Region Cell Placement per Global Clock: Region X1Y0
|
||||
-------------------------------------------------------------
|
||||
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------+
|
||||
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------+
|
||||
| g0 | n/a | BUFG/O | None | 18 | 0 | 18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | U0/inst/clk_out1 |
|
||||
| g1 | n/a | BUFG/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | U0/inst/clkfbout_buf_clk_wiz_1 |
|
||||
| g0 | n/a | BUFG/O | None | 75 | 0 | 55 | 0 | 15 | 0 | 0 | 1 | 0 | 0 | H125MHz_IBUF_BUFG |
|
||||
| g1 | n/a | BUFG/O | None | 25 | 0 | 25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | U0/inst/clk_out1 |
|
||||
| g2 | n/a | BUFG/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | U0/inst/clkfbout_buf_clk_wiz_1 |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------+
|
||||
* Clock Loads column represents the clock pin loads (pin count)
|
||||
** Non-Clock Loads column represents the non-clock pin loads (pin count)
|
||||
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
|
||||
|
||||
|
||||
12. Clock Region Cell Placement per Global Clock: Region X1Y1
|
||||
-------------------------------------------------------------
|
||||
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------+
|
||||
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------+
|
||||
| g0 | n/a | BUFG/O | None | 8 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | H125MHz_IBUF_BUFG |
|
||||
| g1 | n/a | BUFG/O | None | 25 | 0 | 25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | U0/inst/clk_out1 |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------+
|
||||
* Clock Loads column represents the clock pin loads (pin count)
|
||||
** Non-Clock Loads column represents the non-clock pin loads (pin count)
|
||||
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
|
||||
|
||||
|
||||
|
||||
# Location of BUFG Primitives
|
||||
set_property LOC BUFGCTRL_X0Y17 [get_cells U0/inst/clkf_buf]
|
||||
set_property LOC BUFGCTRL_X0Y16 [get_cells U0/inst/clkout1_buf]
|
||||
set_property LOC BUFGCTRL_X0Y1 [get_cells U0/inst/clkf_buf]
|
||||
set_property LOC BUFGCTRL_X0Y0 [get_cells U0/inst/clkout1_buf]
|
||||
set_property LOC BUFGCTRL_X0Y16 [get_cells H125MHz_IBUF_BUFG_inst]
|
||||
|
||||
# Location of IO Primitives which is load of clock spine
|
||||
|
||||
# Location of clock ports
|
||||
set_property LOC IOB_X0Y78 [get_ports H125MHz]
|
||||
|
||||
# Clock net "U0/inst/clk_out1" driven by instance "U0/inst/clkout1_buf" located at site "BUFGCTRL_X0Y16"
|
||||
# Clock net "U0/inst/clk_out1" driven by instance "U0/inst/clkout1_buf" located at site "BUFGCTRL_X0Y0"
|
||||
#startgroup
|
||||
create_pblock {CLKAG_U0/inst/clk_out1}
|
||||
add_cells_to_pblock [get_pblocks {CLKAG_U0/inst/clk_out1}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="U0/inst/clk_out1"}]]]
|
||||
resize_pblock [get_pblocks {CLKAG_U0/inst/clk_out1}] -add {CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1}
|
||||
resize_pblock [get_pblocks {CLKAG_U0/inst/clk_out1}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1}
|
||||
#endgroup
|
||||
|
||||
# Clock net "H125MHz_IBUF_BUFG" driven by instance "H125MHz_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y16"
|
||||
#startgroup
|
||||
create_pblock {CLKAG_H125MHz_IBUF_BUFG}
|
||||
add_cells_to_pblock [get_pblocks {CLKAG_H125MHz_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL && NAME!=U0/inst/mmcm_adv_inst} -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="H125MHz_IBUF_BUFG"}]]]
|
||||
resize_pblock [get_pblocks {CLKAG_H125MHz_IBUF_BUFG}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1}
|
||||
#endgroup
|
||||
|
||||
@ -1,8 +1,8 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
|
||||
| Date : Tue Dec 7 12:43:23 2021
|
||||
| Host : irb121-02-w running 64-bit major release (build 9200)
|
||||
| Date : Tue Jan 4 12:19:29 2022
|
||||
| Host : irb121-12-w running 64-bit major release (build 9200)
|
||||
| Command : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt
|
||||
| Design : VGA_top
|
||||
| Device : xc7z010
|
||||
@ -23,8 +23,8 @@ Table of Contents
|
||||
+----------------------------------------------------------+-------+
|
||||
| Status | Count |
|
||||
+----------------------------------------------------------+-------+
|
||||
| Number of unique control sets | 2 |
|
||||
| Unused register locations in slices containing registers | 11 |
|
||||
| Number of unique control sets | 31 |
|
||||
| Unused register locations in slices containing registers | 180 |
|
||||
+----------------------------------------------------------+-------+
|
||||
|
||||
|
||||
@ -34,8 +34,14 @@ Table of Contents
|
||||
+--------+--------------+
|
||||
| Fanout | Control Sets |
|
||||
+--------+--------------+
|
||||
| 10 | 1 |
|
||||
| 11 | 1 |
|
||||
| 1 | 17 |
|
||||
| 3 | 2 |
|
||||
| 4 | 2 |
|
||||
| 10 | 2 |
|
||||
| 11 | 2 |
|
||||
| 13 | 1 |
|
||||
| 14 | 1 |
|
||||
| 16+ | 4 |
|
||||
+--------+--------------+
|
||||
|
||||
|
||||
@ -45,23 +51,52 @@ Table of Contents
|
||||
+--------------+-----------------------+------------------------+-----------------+--------------+
|
||||
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
|
||||
+--------------+-----------------------+------------------------+-----------------+--------------+
|
||||
| No | No | No | 0 | 0 |
|
||||
| No | No | Yes | 0 | 0 |
|
||||
| No | Yes | No | 11 | 4 |
|
||||
| Yes | No | No | 0 | 0 |
|
||||
| Yes | No | Yes | 0 | 0 |
|
||||
| Yes | Yes | No | 10 | 5 |
|
||||
| No | No | No | 71 | 29 |
|
||||
| No | No | Yes | 40 | 13 |
|
||||
| No | Yes | No | 34 | 21 |
|
||||
| Yes | No | No | 25 | 12 |
|
||||
| Yes | No | Yes | 32 | 18 |
|
||||
| Yes | Yes | No | 10 | 6 |
|
||||
+--------------+-----------------------+------------------------+-----------------+--------------+
|
||||
|
||||
|
||||
4. Detailed Control Set Information
|
||||
-----------------------------------
|
||||
|
||||
+-------------------+---------------+------------------+------------------+----------------+
|
||||
| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count |
|
||||
+-------------------+---------------+------------------+------------------+----------------+
|
||||
| U0/inst/clk_out1 | U1/eqOp | U1/comptY | 5 | 10 |
|
||||
| U0/inst/clk_out1 | | U1/clear | 4 | 11 |
|
||||
+-------------------+---------------+------------------+------------------+----------------+
|
||||
+----------------------------------+------------------------+---------------------------------------+------------------+----------------+
|
||||
| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count |
|
||||
+----------------------------------+------------------------+---------------------------------------+------------------+----------------+
|
||||
| U0/inst/clk_out1 | | SNAKE/startUpdate_i_2_n_0 | 1 | 1 |
|
||||
| UPD/dataOut_reg[19]_LDC_i_1_n_0 | | UPD/dataOut_reg[19]_LDC_i_2_n_0 | 1 | 1 |
|
||||
| UPD/dataOut_reg[18]_LDC_i_1_n_0 | | UPD/dataOut_reg[18]_LDC_i_2_n_0 | 1 | 1 |
|
||||
| UPD/dataOut_reg[1]_LDC_i_1_n_0 | | UPD/dataOut_reg[1]_LDC_i_2_n_0 | 1 | 1 |
|
||||
| UPD/dataOut_reg[4]_LDC_i_1_n_0 | | UPD/dataOut_reg[4]_LDC_i_2_n_0 | 1 | 1 |
|
||||
| UPD/dataOut_reg[21]_LDC_i_1_n_0 | | UPD/dataOut_reg[21]_LDC_i_2_n_0 | 1 | 1 |
|
||||
| UPD/dataOut_reg[20]_LDC_i_1_n_0 | | UPD/dataOut_reg[20]_LDC_i_2_n_0 | 1 | 1 |
|
||||
| H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[19]_LDC_i_1_n_0 | 1 | 1 |
|
||||
| H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[18]_LDC_i_1_n_0 | 1 | 1 |
|
||||
| H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[1]_LDC_i_1_n_0 | 1 | 1 |
|
||||
| H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[21]_LDC_i_2_n_0 | 1 | 1 |
|
||||
| H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[21]_LDC_i_1_n_0 | 1 | 1 |
|
||||
| H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[20]_LDC_i_2_n_0 | 1 | 1 |
|
||||
| H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[18]_LDC_i_2_n_0 | 1 | 1 |
|
||||
| H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[19]_LDC_i_2_n_0 | 1 | 1 |
|
||||
| H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[20]_LDC_i_1_n_0 | 1 | 1 |
|
||||
| H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[1]_LDC_i_2_n_0 | 1 | 1 |
|
||||
| H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[4]_LDC_i_1_n_0 | 1 | 3 |
|
||||
| H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[4]_LDC_i_2_n_0 | 1 | 3 |
|
||||
| H125MHz_IBUF_BUFG | | SNAKE/Q[0] | 4 | 4 |
|
||||
| H125MHz_IBUF_BUFG | UPD/update | | 2 | 4 |
|
||||
| U0/inst/clk_out1 | SYNC/eqOp | SYNC/comptY | 6 | 10 |
|
||||
| H125MHz_IBUF_BUFG | RAMCTRL/SNAKE_RAM/E[0] | | 3 | 10 |
|
||||
| U0/inst/clk_out1 | | SYNC/clear | 6 | 11 |
|
||||
| H125MHz_IBUF_BUFG | SNAKE/cCaseX0 | | 7 | 11 |
|
||||
| U0/inst/clk_out1 | | SNAKE/AR[0] | 4 | 13 |
|
||||
| H125MHz_IBUF_BUFG | | SNAKE/AR[0] | 6 | 14 |
|
||||
| H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/currentSnake_reg[dirY][0]_i_2_n_0 | 6 | 16 |
|
||||
| ~UPD/update | | | 5 | 17 |
|
||||
| U0/inst/clk_out1 | | UPD_CLK_DIV/temp[0]_i_2_n_0 | 7 | 25 |
|
||||
| H125MHz_IBUF_BUFG | | | 24 | 54 |
|
||||
+----------------------------------+------------------------+---------------------------------------+------------------+----------------+
|
||||
|
||||
|
||||
|
||||
@ -1,8 +1,8 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
|
||||
| Date : Tue Dec 7 12:43:21 2021
|
||||
| Host : irb121-02-w running 64-bit major release (build 9200)
|
||||
| Date : Tue Jan 4 12:19:12 2022
|
||||
| Host : irb121-12-w running 64-bit major release (build 9200)
|
||||
| Command : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
|
||||
| Design : VGA_top
|
||||
| Device : xc7z010clg400-1
|
||||
|
||||
Binary file not shown.
@ -1,8 +1,8 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
|
||||
| Date : Tue Dec 7 12:43:47 2021
|
||||
| Host : irb121-02-w running 64-bit major release (build 9200)
|
||||
| Date : Tue Jan 4 12:21:22 2022
|
||||
| Host : irb121-12-w running 64-bit major release (build 9200)
|
||||
| Command : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
|
||||
| Design : VGA_top
|
||||
| Device : xc7z010clg400-1
|
||||
@ -24,15 +24,46 @@ Table of Contents
|
||||
Design limits: <entire design considered>
|
||||
Ruledeck: default
|
||||
Max violations: <unlimited>
|
||||
Violations found: 1
|
||||
+--------+----------+--------------------+------------+
|
||||
| Rule | Severity | Description | Violations |
|
||||
+--------+----------+--------------------+------------+
|
||||
| ZPS7-1 | Warning | PS7 block required | 1 |
|
||||
+--------+----------+--------------------+------------+
|
||||
Violations found: 7
|
||||
+----------+----------+--------------------+------------+
|
||||
| Rule | Severity | Description | Violations |
|
||||
+----------+----------+--------------------+------------+
|
||||
| PDRC-153 | Warning | Gated clock check | 6 |
|
||||
| ZPS7-1 | Warning | PS7 block required | 1 |
|
||||
+----------+----------+--------------------+------------+
|
||||
|
||||
2. REPORT DETAILS
|
||||
-----------------
|
||||
PDRC-153#1 Warning
|
||||
Gated clock check
|
||||
Net UPD/dataOut_reg[18]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[18]_LDC_i_1/O, cell UPD/dataOut_reg[18]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
||||
Related violations: <none>
|
||||
|
||||
PDRC-153#2 Warning
|
||||
Gated clock check
|
||||
Net UPD/dataOut_reg[19]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[19]_LDC_i_1/O, cell UPD/dataOut_reg[19]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
||||
Related violations: <none>
|
||||
|
||||
PDRC-153#3 Warning
|
||||
Gated clock check
|
||||
Net UPD/dataOut_reg[1]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[1]_LDC_i_1/O, cell UPD/dataOut_reg[1]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
||||
Related violations: <none>
|
||||
|
||||
PDRC-153#4 Warning
|
||||
Gated clock check
|
||||
Net UPD/dataOut_reg[20]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[20]_LDC_i_1/O, cell UPD/dataOut_reg[20]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
||||
Related violations: <none>
|
||||
|
||||
PDRC-153#5 Warning
|
||||
Gated clock check
|
||||
Net UPD/dataOut_reg[21]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[21]_LDC_i_1/O, cell UPD/dataOut_reg[21]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
||||
Related violations: <none>
|
||||
|
||||
PDRC-153#6 Warning
|
||||
Gated clock check
|
||||
Net UPD/dataOut_reg[4]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[4]_LDC_i_1/O, cell UPD/dataOut_reg[4]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
||||
Related violations: <none>
|
||||
|
||||
ZPS7-1#1 Warning
|
||||
PS7 block required
|
||||
The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
|
||||
|
||||
Binary file not shown.
@ -1,8 +1,8 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
-------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
|
||||
| Date : Tue Dec 7 12:43:23 2021
|
||||
| Host : irb121-02-w running 64-bit major release (build 9200)
|
||||
| Date : Tue Jan 4 12:19:29 2022
|
||||
| Host : irb121-12-w running 64-bit major release (build 9200)
|
||||
| Command : report_io -file VGA_top_io_placed.rpt
|
||||
| Design : VGA_top
|
||||
| Device : xc7z010
|
||||
@ -112,7 +112,7 @@ Table of Contents
|
||||
| D15 | | | PS_MIO33_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| D16 | | | PS_MIO46_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| D17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| D18 | | High Range | IO_L3N_T0_DQS_AD1N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| D18 | led[3] | High Range | IO_L3N_T0_DQS_AD1N_35 | TRISTATE | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| D19 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| D20 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| E1 | | | PS_DDR_DQ7_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
@ -168,7 +168,7 @@ Table of Contents
|
||||
| G11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
|
||||
| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| G13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| G14 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| G14 | led[2] | High Range | IO_0_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| G15 | resetGeneral | High Range | IO_L19N_T3_VREF_35 | INPUT | LVCMOS33 | 35 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| G16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| G17 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
@ -268,8 +268,8 @@ Table of Contents
|
||||
| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| M12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| M13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| M14 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| M15 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| M14 | led[0] | High Range | IO_L23P_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| M15 | led[1] | High Range | IO_L23N_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| M16 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
|
||||
| M17 | | High Range | IO_L8P_T1_AD10P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| M18 | | High Range | IO_L8N_T1_AD10N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
@ -310,7 +310,7 @@ Table of Contents
|
||||
| P13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| P14 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| P15 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| P16 | bouton_down | High Range | IO_L24N_T3_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| P16 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| P17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| P18 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| P19 | vga_hs | High Range | IO_L13N_T2_MRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
@ -332,7 +332,7 @@ Table of Contents
|
||||
| R15 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
|
||||
| R16 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| R17 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| R18 | bouton_up | High Range | IO_L20N_T3_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| R18 | | High Range | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| R19 | vga_vs | High Range | IO_0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| R20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| T1 | | | PS_DDR_DM2_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
@ -390,7 +390,7 @@ Table of Contents
|
||||
| V13 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| V14 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
|
||||
| V15 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| V16 | bouton_left | High Range | IO_L18P_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| V16 | | High Range | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| V17 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| V18 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| V19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
@ -430,7 +430,7 @@ Table of Contents
|
||||
| Y13 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| Y14 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| Y15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| Y16 | bouton_right | High Range | IO_L7P_T1_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| Y16 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| Y17 | | High Range | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| Y18 | | High Range | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| Y19 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
|
||||
Binary file not shown.
@ -1,8 +1,8 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
|
||||
| Date : Tue Dec 7 12:43:47 2021
|
||||
| Host : irb121-02-w running 64-bit major release (build 9200)
|
||||
| Date : Tue Jan 4 12:21:24 2022
|
||||
| Host : irb121-12-w running 64-bit major release (build 9200)
|
||||
| Command : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
|
||||
| Design : VGA_top
|
||||
| Device : xc7z010clg400-1
|
||||
@ -23,23 +23,496 @@ Table of Contents
|
||||
Floorplan: design_1
|
||||
Design limits: <entire design considered>
|
||||
Max violations: <unlimited>
|
||||
Violations found: 2
|
||||
+----------+----------+------------------------------------------------+------------+
|
||||
| Rule | Severity | Description | Violations |
|
||||
+----------+----------+------------------------------------------------+------------+
|
||||
| TIMING-6 | Warning | No common primary clock between related clocks | 2 |
|
||||
+----------+----------+------------------------------------------------+------------+
|
||||
Violations found: 95
|
||||
+-----------+----------+----------------------------------------------------+------------+
|
||||
| Rule | Severity | Description | Violations |
|
||||
+-----------+----------+----------------------------------------------------+------------+
|
||||
| LUTAR-1 | Warning | LUT drives async reset alert | 14 |
|
||||
| SYNTH-6 | Warning | Timing of a block RAM might be sub-optimal | 26 |
|
||||
| TIMING-4 | Warning | Invalid primary clock redefinition on a clock tree | 1 |
|
||||
| TIMING-6 | Warning | No common primary clock between related clocks | 2 |
|
||||
| TIMING-7 | Warning | No common node between related clocks | 2 |
|
||||
| TIMING-16 | Warning | Large setup violation | 21 |
|
||||
| TIMING-18 | Warning | Missing input or output delay | 5 |
|
||||
| TIMING-20 | Warning | Non-clocked latch | 23 |
|
||||
| TIMING-27 | Warning | Invalid primary clock on hierarchical pin | 1 |
|
||||
+-----------+----------+----------------------------------------------------+------------+
|
||||
|
||||
2. REPORT DETAILS
|
||||
-----------------
|
||||
LUTAR-1#1 Warning
|
||||
LUT drives async reset alert
|
||||
LUT cell SNAKE/startUpdate_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) SNAKE/startUpdate_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
|
||||
Related violations: <none>
|
||||
|
||||
LUTAR-1#2 Warning
|
||||
LUT drives async reset alert
|
||||
LUT cell UPD/dataOut_reg[18]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) UPD/dataOut_reg[18]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
|
||||
Related violations: <none>
|
||||
|
||||
LUTAR-1#3 Warning
|
||||
LUT drives async reset alert
|
||||
LUT cell UPD/dataOut_reg[18]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) UPD/dataOut_reg[18]_C/CLR, UPD/dataOut_reg[18]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
|
||||
Related violations: <none>
|
||||
|
||||
LUTAR-1#4 Warning
|
||||
LUT drives async reset alert
|
||||
LUT cell UPD/dataOut_reg[19]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) UPD/dataOut_reg[19]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
|
||||
Related violations: <none>
|
||||
|
||||
LUTAR-1#5 Warning
|
||||
LUT drives async reset alert
|
||||
LUT cell UPD/dataOut_reg[19]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) UPD/dataOut_reg[19]_C/CLR, UPD/dataOut_reg[19]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
|
||||
Related violations: <none>
|
||||
|
||||
LUTAR-1#6 Warning
|
||||
LUT drives async reset alert
|
||||
LUT cell UPD/dataOut_reg[1]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) UPD/dataOut_reg[1]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
|
||||
Related violations: <none>
|
||||
|
||||
LUTAR-1#7 Warning
|
||||
LUT drives async reset alert
|
||||
LUT cell UPD/dataOut_reg[1]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) UPD/dataOut_reg[1]_C/CLR, UPD/dataOut_reg[1]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
|
||||
Related violations: <none>
|
||||
|
||||
LUTAR-1#8 Warning
|
||||
LUT drives async reset alert
|
||||
LUT cell UPD/dataOut_reg[20]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) UPD/dataOut_reg[20]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
|
||||
Related violations: <none>
|
||||
|
||||
LUTAR-1#9 Warning
|
||||
LUT drives async reset alert
|
||||
LUT cell UPD/dataOut_reg[20]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) UPD/dataOut_reg[20]_C/CLR, UPD/dataOut_reg[20]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
|
||||
Related violations: <none>
|
||||
|
||||
LUTAR-1#10 Warning
|
||||
LUT drives async reset alert
|
||||
LUT cell UPD/dataOut_reg[21]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) UPD/dataOut_reg[21]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
|
||||
Related violations: <none>
|
||||
|
||||
LUTAR-1#11 Warning
|
||||
LUT drives async reset alert
|
||||
LUT cell UPD/dataOut_reg[21]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) UPD/dataOut_reg[21]_C/CLR, UPD/dataOut_reg[21]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
|
||||
Related violations: <none>
|
||||
|
||||
LUTAR-1#12 Warning
|
||||
LUT drives async reset alert
|
||||
LUT cell UPD/dataOut_reg[4]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) UPD/dataOut_reg[0]_P/PRE, UPD/dataOut_reg[3]_P/PRE, UPD/dataOut_reg[4]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
|
||||
Related violations: <none>
|
||||
|
||||
LUTAR-1#13 Warning
|
||||
LUT drives async reset alert
|
||||
LUT cell UPD/dataOut_reg[4]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) UPD/dataOut_reg[0]_C/CLR, UPD/dataOut_reg[3]_C/CLR, UPD/dataOut_reg[4]_C/CLR, UPD/dataOut_reg[4]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
|
||||
Related violations: <none>
|
||||
|
||||
LUTAR-1#14 Warning
|
||||
LUT drives async reset alert
|
||||
LUT cell UPD_CLK_DIV/temp[0]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) UPD_CLK_DIV/temp_reg[0]/CLR, UPD_CLK_DIV/temp_reg[10]/CLR, UPD_CLK_DIV/temp_reg[11]/CLR, UPD_CLK_DIV/temp_reg[12]/CLR, UPD_CLK_DIV/temp_reg[13]/CLR, UPD_CLK_DIV/temp_reg[14]/CLR, UPD_CLK_DIV/temp_reg[15]/CLR, UPD_CLK_DIV/temp_reg[16]/CLR, UPD_CLK_DIV/temp_reg[17]/CLR, UPD_CLK_DIV/temp_reg[18]/CLR, UPD_CLK_DIV/temp_reg[19]/CLR, UPD_CLK_DIV/temp_reg[1]/CLR, UPD_CLK_DIV/temp_reg[20]/CLR, UPD_CLK_DIV/temp_reg[21]/CLR, UPD_CLK_DIV/temp_reg[22]/CLR (the first 15 of 25 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#1 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
The timing for the instance RAMCTRL/MAT_RAM/mem_reg_1, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#2 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
The timing for the instance RAMCTRL/MAT_RAM/mem_reg_2, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#3 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
The timing for the instance RAMCTRL/MAT_RAM/mem_reg_3, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#4 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
The timing for the instance RAMCTRL/MAT_RAM/mem_reg_4, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#5 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
The timing for the instance RAMCTRL/MAT_RAM/mem_reg_6, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#6 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
The timing for the instance RAMCTRL/MAT_RAM/mem_reg_7, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#7 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
The timing for the instance RAMCTRL/MAT_RAM/mem_reg_8, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#8 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
The timing for the instance RAMCTRL/MAT_RAM/mem_reg_9, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#9 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_1_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#10 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_1_1, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#11 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_2_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#12 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_2_1, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#13 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_3_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#14 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_3_1, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#15 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_4_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#16 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_4_1, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#17 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_5_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#18 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_5_1, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#19 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_6_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#20 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_6_1, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#21 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_7_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#22 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_7_1, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#23 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_8_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#24 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_8_1, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#25 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_9_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#26 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_9_1, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-4#1 Warning
|
||||
Invalid primary clock redefinition on a clock tree
|
||||
Invalid clock redefinition on a clock tree. The primary clock U0/inst/clk_in1 is defined downstream of clock sys_clk_pin and overrides its insertion delay and/or waveform definition
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-6#1 Warning
|
||||
No common primary clock between related clocks
|
||||
The clocks clk_out1_clk_wiz_1 and clk_out1_clk_wiz_1_1 are related (timed together) but they have no common primary clock. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks clk_out1_clk_wiz_1] -to [get_clocks clk_out1_clk_wiz_1_1]
|
||||
The clocks clk_out1_clk_wiz_1 and sys_clk_pin are related (timed together) but they have no common primary clock. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks clk_out1_clk_wiz_1] -to [get_clocks sys_clk_pin]
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-6#2 Warning
|
||||
No common primary clock between related clocks
|
||||
The clocks clk_out1_clk_wiz_1_1 and clk_out1_clk_wiz_1 are related (timed together) but they have no common primary clock. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks clk_out1_clk_wiz_1_1] -to [get_clocks clk_out1_clk_wiz_1]
|
||||
The clocks sys_clk_pin and clk_out1_clk_wiz_1 are related (timed together) but they have no common primary clock. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks sys_clk_pin] -to [get_clocks clk_out1_clk_wiz_1]
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-7#1 Warning
|
||||
No common node between related clocks
|
||||
The clocks clk_out1_clk_wiz_1 and sys_clk_pin are related (timed together) but they have no common node. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks clk_out1_clk_wiz_1] -to [get_clocks sys_clk_pin]
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-7#2 Warning
|
||||
No common node between related clocks
|
||||
The clocks sys_clk_pin and clk_out1_clk_wiz_1 are related (timed together) but they have no common node. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks sys_clk_pin] -to [get_clocks clk_out1_clk_wiz_1]
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-16#1 Warning
|
||||
Large setup violation
|
||||
There is a large setup violation of -2.757 ns between RAMCTRL/SNAKE_RAM/mem_reg_4_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/snakeHere_reg/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-16#2 Warning
|
||||
Large setup violation
|
||||
There is a large setup violation of -3.112 ns between RAMCTRL/SNAKE_RAM/mem_reg_5_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[0]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-16#3 Warning
|
||||
Large setup violation
|
||||
There is a large setup violation of -3.660 ns between RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[1]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-16#4 Warning
|
||||
Large setup violation
|
||||
There is a large setup violation of -3.702 ns between RAMCTRL/SNAKE_RAM/mem_reg_4_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[0]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-16#5 Warning
|
||||
Large setup violation
|
||||
There is a large setup violation of -3.702 ns between RAMCTRL/SNAKE_RAM/mem_reg_4_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[1]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-16#6 Warning
|
||||
Large setup violation
|
||||
There is a large setup violation of -3.702 ns between RAMCTRL/SNAKE_RAM/mem_reg_4_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[2]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-16#7 Warning
|
||||
Large setup violation
|
||||
There is a large setup violation of -3.702 ns between RAMCTRL/SNAKE_RAM/mem_reg_4_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[3]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-16#8 Warning
|
||||
Large setup violation
|
||||
There is a large setup violation of -3.740 ns between RAMCTRL/SNAKE_RAM/mem_reg_4_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[8]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-16#9 Warning
|
||||
Large setup violation
|
||||
There is a large setup violation of -3.740 ns between RAMCTRL/SNAKE_RAM/mem_reg_4_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[9]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-16#10 Warning
|
||||
Large setup violation
|
||||
There is a large setup violation of -3.881 ns between RAMCTRL/SNAKE_RAM/mem_reg_4_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[4]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-16#11 Warning
|
||||
Large setup violation
|
||||
There is a large setup violation of -3.881 ns between RAMCTRL/SNAKE_RAM/mem_reg_4_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[5]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-16#12 Warning
|
||||
Large setup violation
|
||||
There is a large setup violation of -3.881 ns between RAMCTRL/SNAKE_RAM/mem_reg_4_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[6]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-16#13 Warning
|
||||
Large setup violation
|
||||
There is a large setup violation of -3.881 ns between RAMCTRL/SNAKE_RAM/mem_reg_4_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[7]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-16#14 Warning
|
||||
Large setup violation
|
||||
There is a large setup violation of -4.008 ns between RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[2]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-16#15 Warning
|
||||
Large setup violation
|
||||
There is a large setup violation of -4.073 ns between RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[3]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-16#16 Warning
|
||||
Large setup violation
|
||||
There is a large setup violation of -4.846 ns between RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[4]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-16#17 Warning
|
||||
Large setup violation
|
||||
There is a large setup violation of -4.866 ns between RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[6]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-16#18 Warning
|
||||
Large setup violation
|
||||
There is a large setup violation of -4.942 ns between RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[7]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-16#19 Warning
|
||||
Large setup violation
|
||||
There is a large setup violation of -4.950 ns between RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[5]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-16#20 Warning
|
||||
Large setup violation
|
||||
There is a large setup violation of -5.507 ns between RAMCTRL/SNAKE_RAM/mem_reg_5_0/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[8]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-16#21 Warning
|
||||
Large setup violation
|
||||
There is a large setup violation of -5.611 ns between RAMCTRL/SNAKE_RAM/mem_reg_5_0/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[9]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#1 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on resetGeneral relative to clock(s) sys_clk_pin
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#2 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on led[0] relative to clock(s) sys_clk_pin
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#3 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on led[1] relative to clock(s) sys_clk_pin
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#4 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on led[2] relative to clock(s) sys_clk_pin
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#5 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on led[3] relative to clock(s) sys_clk_pin
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#1 Warning
|
||||
Non-clocked latch
|
||||
The latch UPD/currentSnake_reg[X][4] cannot be properly analyzed as its control pin UPD/currentSnake_reg[X][4]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#2 Warning
|
||||
Non-clocked latch
|
||||
The latch UPD/currentSnake_reg[X][5] cannot be properly analyzed as its control pin UPD/currentSnake_reg[X][5]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#3 Warning
|
||||
Non-clocked latch
|
||||
The latch UPD/currentSnake_reg[X][6] cannot be properly analyzed as its control pin UPD/currentSnake_reg[X][6]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#4 Warning
|
||||
Non-clocked latch
|
||||
The latch UPD/currentSnake_reg[X][7] cannot be properly analyzed as its control pin UPD/currentSnake_reg[X][7]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#5 Warning
|
||||
Non-clocked latch
|
||||
The latch UPD/currentSnake_reg[dirX][1] cannot be properly analyzed as its control pin UPD/currentSnake_reg[dirX][1]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#6 Warning
|
||||
Non-clocked latch
|
||||
The latch UPD/currentSnake_reg[dirY][0] cannot be properly analyzed as its control pin UPD/currentSnake_reg[dirY][0]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#7 Warning
|
||||
Non-clocked latch
|
||||
The latch UPD/dataOut_reg[18]_LDC cannot be properly analyzed as its control pin UPD/dataOut_reg[18]_LDC/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#8 Warning
|
||||
Non-clocked latch
|
||||
The latch UPD/dataOut_reg[19]_LDC cannot be properly analyzed as its control pin UPD/dataOut_reg[19]_LDC/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#9 Warning
|
||||
Non-clocked latch
|
||||
The latch UPD/dataOut_reg[1]_LDC cannot be properly analyzed as its control pin UPD/dataOut_reg[1]_LDC/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#10 Warning
|
||||
Non-clocked latch
|
||||
The latch UPD/dataOut_reg[20]_LDC cannot be properly analyzed as its control pin UPD/dataOut_reg[20]_LDC/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#11 Warning
|
||||
Non-clocked latch
|
||||
The latch UPD/dataOut_reg[21]_LDC cannot be properly analyzed as its control pin UPD/dataOut_reg[21]_LDC/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#12 Warning
|
||||
Non-clocked latch
|
||||
The latch UPD/dataOut_reg[4]_LDC cannot be properly analyzed as its control pin UPD/dataOut_reg[4]_LDC/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#13 Warning
|
||||
Non-clocked latch
|
||||
The latch UPD/matAddress_reg[0] cannot be properly analyzed as its control pin UPD/matAddress_reg[0]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#14 Warning
|
||||
Non-clocked latch
|
||||
The latch UPD/matAddress_reg[10] cannot be properly analyzed as its control pin UPD/matAddress_reg[10]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#15 Warning
|
||||
Non-clocked latch
|
||||
The latch UPD/matAddress_reg[1] cannot be properly analyzed as its control pin UPD/matAddress_reg[1]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#16 Warning
|
||||
Non-clocked latch
|
||||
The latch UPD/matAddress_reg[2] cannot be properly analyzed as its control pin UPD/matAddress_reg[2]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#17 Warning
|
||||
Non-clocked latch
|
||||
The latch UPD/matAddress_reg[3] cannot be properly analyzed as its control pin UPD/matAddress_reg[3]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#18 Warning
|
||||
Non-clocked latch
|
||||
The latch UPD/matAddress_reg[4] cannot be properly analyzed as its control pin UPD/matAddress_reg[4]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#19 Warning
|
||||
Non-clocked latch
|
||||
The latch UPD/matAddress_reg[5] cannot be properly analyzed as its control pin UPD/matAddress_reg[5]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#20 Warning
|
||||
Non-clocked latch
|
||||
The latch UPD/matAddress_reg[6] cannot be properly analyzed as its control pin UPD/matAddress_reg[6]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#21 Warning
|
||||
Non-clocked latch
|
||||
The latch UPD/matAddress_reg[7] cannot be properly analyzed as its control pin UPD/matAddress_reg[7]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#22 Warning
|
||||
Non-clocked latch
|
||||
The latch UPD/matAddress_reg[8] cannot be properly analyzed as its control pin UPD/matAddress_reg[8]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#23 Warning
|
||||
Non-clocked latch
|
||||
The latch UPD/matAddress_reg[9] cannot be properly analyzed as its control pin UPD/matAddress_reg[9]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-27#1 Warning
|
||||
Invalid primary clock on hierarchical pin
|
||||
A primary clock U0/inst/clk_in1 is created on an inappropriate internal pin U0/inst/clk_in1. It is not recommended to create a primary clock on a hierarchical pin when its driver pin has a fanout connected to multiple clock pins
|
||||
Related violations: <none>
|
||||
|
||||
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
@ -1,8 +1,8 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
-------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
|
||||
| Date : Tue Dec 7 12:43:47 2021
|
||||
| Host : irb121-02-w running 64-bit major release (build 9200)
|
||||
| Date : Tue Jan 4 12:21:24 2022
|
||||
| Host : irb121-12-w running 64-bit major release (build 9200)
|
||||
| Command : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
|
||||
| Design : VGA_top
|
||||
| Device : xc7z010clg400-1
|
||||
@ -30,14 +30,14 @@ Table of Contents
|
||||
----------
|
||||
|
||||
+--------------------------+--------------+
|
||||
| Total On-Chip Power (W) | 0.210 |
|
||||
| Total On-Chip Power (W) | 0.298 |
|
||||
| Design Power Budget (W) | Unspecified* |
|
||||
| Power Budget Margin (W) | NA |
|
||||
| Dynamic (W) | 0.116 |
|
||||
| Device Static (W) | 0.094 |
|
||||
| Dynamic (W) | 0.201 |
|
||||
| Device Static (W) | 0.097 |
|
||||
| Effective TJA (C/W) | 11.5 |
|
||||
| Max Ambient (C) | 82.6 |
|
||||
| Junction Temperature (C) | 27.4 |
|
||||
| Max Ambient (C) | 81.6 |
|
||||
| Junction Temperature (C) | 28.4 |
|
||||
| Confidence Level | Medium |
|
||||
| Setting File | --- |
|
||||
| Simulation Activity File | --- |
|
||||
@ -52,17 +52,19 @@ Table of Contents
|
||||
+----------------+-----------+----------+-----------+-----------------+
|
||||
| On-Chip | Power (W) | Used | Available | Utilization (%) |
|
||||
+----------------+-----------+----------+-----------+-----------------+
|
||||
| Clocks | <0.001 | 8 | --- | --- |
|
||||
| Slice Logic | <0.001 | 272 | --- | --- |
|
||||
| LUT as Logic | <0.001 | 168 | 17600 | 0.95 |
|
||||
| CARRY4 | <0.001 | 34 | 4400 | 0.77 |
|
||||
| Register | <0.001 | 21 | 35200 | 0.06 |
|
||||
| Others | 0.000 | 4 | --- | --- |
|
||||
| Signals | <0.001 | 149 | --- | --- |
|
||||
| Clocks | 0.004 | 6 | --- | --- |
|
||||
| Slice Logic | 0.002 | 2313 | --- | --- |
|
||||
| LUT as Logic | 0.002 | 1491 | 17600 | 8.47 |
|
||||
| CARRY4 | <0.001 | 266 | 4400 | 6.05 |
|
||||
| Register | <0.001 | 212 | 35200 | 0.60 |
|
||||
| F7/F8 Muxes | <0.001 | 20 | 17600 | 0.11 |
|
||||
| Others | 0.000 | 26 | --- | --- |
|
||||
| Signals | 0.004 | 1918 | --- | --- |
|
||||
| Block RAM | 0.075 | 22.5 | 60 | 37.50 |
|
||||
| MMCM | 0.115 | 1 | 2 | 50.00 |
|
||||
| I/O | <0.001 | 19 | 100 | 19.00 |
|
||||
| Static Power | 0.094 | | | |
|
||||
| Total | 0.210 | | | |
|
||||
| I/O | 0.002 | 24 | 100 | 24.00 |
|
||||
| Static Power | 0.097 | | | |
|
||||
| Total | 0.298 | | | |
|
||||
+----------------+-----------+----------+-----------+-----------------+
|
||||
|
||||
|
||||
@ -72,20 +74,20 @@ Table of Contents
|
||||
+-----------+-------------+-----------+-------------+------------+
|
||||
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
|
||||
+-----------+-------------+-----------+-------------+------------+
|
||||
| Vccint | 1.000 | 0.004 | 0.001 | 0.004 |
|
||||
| Vccaux | 1.800 | 0.069 | 0.064 | 0.005 |
|
||||
| Vcco33 | 3.300 | 0.001 | 0.000 | 0.001 |
|
||||
| Vccint | 1.000 | 0.083 | 0.078 | 0.005 |
|
||||
| Vccaux | 1.800 | 0.070 | 0.064 | 0.006 |
|
||||
| Vcco33 | 3.300 | 0.002 | 0.001 | 0.001 |
|
||||
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 |
|
||||
| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 |
|
||||
| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 |
|
||||
| Vccbram | 1.000 | 0.008 | 0.007 | 0.001 |
|
||||
| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 |
|
||||
| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 |
|
||||
| MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 |
|
||||
| Vccpint | 1.000 | 0.017 | 0.000 | 0.017 |
|
||||
| Vccpint | 1.000 | 0.018 | 0.000 | 0.018 |
|
||||
| Vccpaux | 1.800 | 0.010 | 0.000 | 0.010 |
|
||||
| Vccpll | 1.800 | 0.003 | 0.000 | 0.003 |
|
||||
| Vcco_ddr | 1.500 | 0.000 | 0.000 | 0.000 |
|
||||
@ -98,17 +100,17 @@ Table of Contents
|
||||
1.3 Confidence Level
|
||||
--------------------
|
||||
|
||||
+-----------------------------+------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------+
|
||||
| User Input Data | Confidence | Details | Action |
|
||||
+-----------------------------+------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------+
|
||||
| Design implementation state | High | Design is routed | |
|
||||
| Clock nodes activity | High | User specified more than 95% of clocks | |
|
||||
| I/O nodes activity | High | User specified more than 95% of inputs | |
|
||||
| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
|
||||
| Device models | High | Device models are Production | |
|
||||
| | | | |
|
||||
| Overall confidence level | Medium | | |
|
||||
+-----------------------------+------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------+
|
||||
+-----------------------------+------------+-------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
|
||||
| User Input Data | Confidence | Details | Action |
|
||||
+-----------------------------+------------+-------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
|
||||
| Design implementation state | High | Design is routed | |
|
||||
| Clock nodes activity | Medium | More than 5% of clocks are missing user specification | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view |
|
||||
| I/O nodes activity | Medium | More than 5% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
|
||||
| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
|
||||
| Device models | High | Device models are Production | |
|
||||
| | | | |
|
||||
| Overall confidence level | Medium | | |
|
||||
+-----------------------------+------------+-------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
2. Settings
|
||||
@ -132,16 +134,14 @@ Table of Contents
|
||||
2.2 Clock Constraints
|
||||
---------------------
|
||||
|
||||
+----------------------+----------------------------+-----------------+
|
||||
| Clock | Domain | Constraint (ns) |
|
||||
+----------------------+----------------------------+-----------------+
|
||||
| H125MHz | H125MHz | 8.0 |
|
||||
| clk_out1_clk_wiz_1 | U0/inst/clk_out1_clk_wiz_1 | 40.0 |
|
||||
| clk_out1_clk_wiz_1_1 | U0/inst/clk_out1_clk_wiz_1 | 40.0 |
|
||||
| clkfbout_clk_wiz_1 | U0/inst/clkfbout_clk_wiz_1 | 40.0 |
|
||||
| clkfbout_clk_wiz_1_1 | U0/inst/clkfbout_clk_wiz_1 | 40.0 |
|
||||
| sys_clk_pin | H125MHz | 8.0 |
|
||||
+----------------------+----------------------------+-----------------+
|
||||
+--------------------+----------------------------+-----------------+
|
||||
| Clock | Domain | Constraint (ns) |
|
||||
+--------------------+----------------------------+-----------------+
|
||||
| clk_out1_clk_wiz_1 | U0/inst/clk_out1_clk_wiz_1 | 40.0 |
|
||||
| clkfbout_clk_wiz_1 | U0/inst/clkfbout_clk_wiz_1 | 40.0 |
|
||||
| sys_clk_pin | H125MHz | 8.0 |
|
||||
| sys_clk_pin | H125MHz_IBUF_BUFG | 8.0 |
|
||||
+--------------------+----------------------------+-----------------+
|
||||
|
||||
|
||||
3. Detailed Reports
|
||||
@ -150,12 +150,16 @@ Table of Contents
|
||||
3.1 By Hierarchy
|
||||
----------------
|
||||
|
||||
+----------+-----------+
|
||||
| Name | Power (W) |
|
||||
+----------+-----------+
|
||||
| VGA_top | 0.116 |
|
||||
| U0 | 0.115 |
|
||||
| inst | 0.115 |
|
||||
+----------+-----------+
|
||||
+---------------+-----------+
|
||||
| Name | Power (W) |
|
||||
+---------------+-----------+
|
||||
| VGA_top | 0.201 |
|
||||
| RAMCTRL | 0.080 |
|
||||
| MAT_RAM | 0.031 |
|
||||
| SNAKE_RAM | 0.049 |
|
||||
| U0 | 0.115 |
|
||||
| inst | 0.115 |
|
||||
| UPD | 0.002 |
|
||||
+---------------+-----------+
|
||||
|
||||
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
@ -1,11 +1,11 @@
|
||||
Design Route Status
|
||||
: # nets :
|
||||
------------------------------------------- : ----------- :
|
||||
# of logical nets.......................... : 294 :
|
||||
# of nets not needing routing.......... : 138 :
|
||||
# of internally routed nets........ : 138 :
|
||||
# of routable nets..................... : 156 :
|
||||
# of fully routed nets............. : 156 :
|
||||
# of logical nets.......................... : 3111 :
|
||||
# of nets not needing routing.......... : 1185 :
|
||||
# of internally routed nets........ : 1185 :
|
||||
# of routable nets..................... : 1926 :
|
||||
# of fully routed nets............. : 1926 :
|
||||
# of nets with routing errors.......... : 0 :
|
||||
------------------------------------------- : ----------- :
|
||||
|
||||
|
||||
Binary file not shown.
Binary file not shown.
File diff suppressed because it is too large
Load Diff
Binary file not shown.
Binary file not shown.
@ -1,8 +1,8 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
-----------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
|
||||
| Date : Tue Dec 7 12:43:23 2021
|
||||
| Host : irb121-02-w running 64-bit major release (build 9200)
|
||||
| Date : Tue Jan 4 12:19:29 2022
|
||||
| Host : irb121-12-w running 64-bit major release (build 9200)
|
||||
| Command : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb
|
||||
| Design : VGA_top
|
||||
| Device : 7z010clg400-1
|
||||
@ -31,14 +31,14 @@ Table of Contents
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Slice LUTs | 168 | 0 | 17600 | 0.95 |
|
||||
| LUT as Logic | 168 | 0 | 17600 | 0.95 |
|
||||
| Slice LUTs | 1491 | 0 | 17600 | 8.47 |
|
||||
| LUT as Logic | 1491 | 0 | 17600 | 8.47 |
|
||||
| LUT as Memory | 0 | 0 | 6000 | 0.00 |
|
||||
| Slice Registers | 21 | 0 | 35200 | 0.06 |
|
||||
| Register as Flip Flop | 21 | 0 | 35200 | 0.06 |
|
||||
| Register as Latch | 0 | 0 | 35200 | 0.00 |
|
||||
| F7 Muxes | 0 | 0 | 8800 | 0.00 |
|
||||
| F8 Muxes | 0 | 0 | 4400 | 0.00 |
|
||||
| Slice Registers | 212 | 0 | 35200 | 0.60 |
|
||||
| Register as Flip Flop | 189 | 0 | 35200 | 0.54 |
|
||||
| Register as Latch | 23 | 0 | 35200 | 0.07 |
|
||||
| F7 Muxes | 19 | 0 | 8800 | 0.22 |
|
||||
| F8 Muxes | 1 | 0 | 4400 | 0.02 |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
@ -54,10 +54,10 @@ Table of Contents
|
||||
| 0 | _ | Set | - |
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 0 | Yes | - | Set |
|
||||
| 0 | Yes | - | Reset |
|
||||
| 0 | Yes | Set | - |
|
||||
| 21 | Yes | Reset | - |
|
||||
| 10 | Yes | - | Set |
|
||||
| 87 | Yes | - | Reset |
|
||||
| 1 | Yes | Set | - |
|
||||
| 114 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
@ -67,22 +67,22 @@ Table of Contents
|
||||
+--------------------------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+--------------------------------------------+------+-------+-----------+-------+
|
||||
| Slice | 61 | 0 | 4400 | 1.39 |
|
||||
| SLICEL | 45 | 0 | | |
|
||||
| SLICEM | 16 | 0 | | |
|
||||
| LUT as Logic | 168 | 0 | 17600 | 0.95 |
|
||||
| Slice | 541 | 0 | 4400 | 12.30 |
|
||||
| SLICEL | 361 | 0 | | |
|
||||
| SLICEM | 180 | 0 | | |
|
||||
| LUT as Logic | 1491 | 0 | 17600 | 8.47 |
|
||||
| using O5 output only | 0 | | | |
|
||||
| using O6 output only | 123 | | | |
|
||||
| using O5 and O6 | 45 | | | |
|
||||
| using O6 output only | 1193 | | | |
|
||||
| using O5 and O6 | 298 | | | |
|
||||
| LUT as Memory | 0 | 0 | 6000 | 0.00 |
|
||||
| LUT as Distributed RAM | 0 | 0 | | |
|
||||
| LUT as Shift Register | 0 | 0 | | |
|
||||
| Slice Registers | 21 | 0 | 35200 | 0.06 |
|
||||
| Register driven from within the Slice | 20 | | | |
|
||||
| Register driven from outside the Slice | 1 | | | |
|
||||
| LUT in front of the register is unused | 0 | | | |
|
||||
| LUT in front of the register is used | 1 | | | |
|
||||
| Unique Control Sets | 2 | | 4400 | 0.05 |
|
||||
| Slice Registers | 212 | 0 | 35200 | 0.60 |
|
||||
| Register driven from within the Slice | 165 | | | |
|
||||
| Register driven from outside the Slice | 47 | | | |
|
||||
| LUT in front of the register is unused | 21 | | | |
|
||||
| LUT in front of the register is used | 26 | | | |
|
||||
| Unique Control Sets | 31 | | 4400 | 0.70 |
|
||||
+--------------------------------------------+------+-------+-----------+-------+
|
||||
* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets.
|
||||
|
||||
@ -90,13 +90,15 @@ Table of Contents
|
||||
3. Memory
|
||||
---------
|
||||
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Block RAM Tile | 0 | 0 | 60 | 0.00 |
|
||||
| RAMB36/FIFO* | 0 | 0 | 60 | 0.00 |
|
||||
| RAMB18 | 0 | 0 | 120 | 0.00 |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
| Block RAM Tile | 22.5 | 0 | 60 | 37.50 |
|
||||
| RAMB36/FIFO* | 18 | 0 | 60 | 30.00 |
|
||||
| RAMB36E1 only | 18 | | | |
|
||||
| RAMB18 | 9 | 0 | 120 | 7.50 |
|
||||
| RAMB18E1 only | 9 | | | |
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||
|
||||
|
||||
@ -116,9 +118,9 @@ Table of Contents
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Bonded IOB | 19 | 19 | 100 | 19.00 |
|
||||
| IOB Master Pads | 9 | | | |
|
||||
| IOB Slave Pads | 9 | | | |
|
||||
| Bonded IOB | 24 | 24 | 100 | 24.00 |
|
||||
| IOB Master Pads | 10 | | | |
|
||||
| IOB Slave Pads | 12 | | | |
|
||||
| Bonded IPADs | 0 | 0 | 2 | 0.00 |
|
||||
| Bonded IOPADs | 0 | 0 | 130 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 2 | 0.00 |
|
||||
@ -141,7 +143,7 @@ Table of Contents
|
||||
+------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+------------+------+-------+-----------+-------+
|
||||
| BUFGCTRL | 2 | 0 | 32 | 6.25 |
|
||||
| BUFGCTRL | 3 | 0 | 32 | 9.38 |
|
||||
| BUFIO | 0 | 0 | 8 | 0.00 |
|
||||
| MMCME2_ADV | 1 | 0 | 2 | 50.00 |
|
||||
| PLLE2_ADV | 0 | 0 | 2 | 0.00 |
|
||||
@ -174,18 +176,27 @@ Table of Contents
|
||||
+------------+------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+------------+------+---------------------+
|
||||
| LUT4 | 64 | LUT |
|
||||
| LUT6 | 63 | LUT |
|
||||
| LUT5 | 47 | LUT |
|
||||
| CARRY4 | 34 | CarryLogic |
|
||||
| LUT2 | 28 | LUT |
|
||||
| FDRE | 21 | Flop & Latch |
|
||||
| OBUF | 18 | IO |
|
||||
| LUT3 | 7 | LUT |
|
||||
| LUT1 | 4 | LUT |
|
||||
| BUFG | 2 | Clock |
|
||||
| LUT6 | 447 | LUT |
|
||||
| LUT4 | 365 | LUT |
|
||||
| LUT5 | 358 | LUT |
|
||||
| LUT3 | 332 | LUT |
|
||||
| LUT2 | 275 | LUT |
|
||||
| CARRY4 | 266 | CarryLogic |
|
||||
| FDRE | 114 | Flop & Latch |
|
||||
| FDCE | 64 | Flop & Latch |
|
||||
| LDCE | 23 | Flop & Latch |
|
||||
| OBUF | 21 | IO |
|
||||
| MUXF7 | 19 | MuxFx |
|
||||
| RAMB36E1 | 18 | Block Memory |
|
||||
| LUT1 | 12 | LUT |
|
||||
| FDPE | 10 | Flop & Latch |
|
||||
| RAMB18E1 | 9 | Block Memory |
|
||||
| BUFG | 3 | Clock |
|
||||
| IBUF | 2 | IO |
|
||||
| OBUFT | 1 | IO |
|
||||
| MUXF8 | 1 | MuxFx |
|
||||
| MMCME2_ADV | 1 | Clock |
|
||||
| IBUF | 1 | IO |
|
||||
| FDSE | 1 | Flop & Latch |
|
||||
+------------+------+---------------------+
|
||||
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="impl_1" LaunchPart="xc7z010clg400-1" LaunchTime="1638877370">
|
||||
<GenRun Id="impl_1" LaunchPart="xc7z010clg400-1" LaunchTime="1641295056">
|
||||
<File Type="BITSTR-BMM" Name="VGA_top_bd.bmm"/>
|
||||
<File Type="OPT-METHODOLOGY-DRC" Name="VGA_top_methodology_drc_opted.rpt"/>
|
||||
<File Type="INIT-TIMING" Name="VGA_top_timing_summary_init.rpt"/>
|
||||
@ -71,52 +71,83 @@
|
||||
<File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
|
||||
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xci">
|
||||
<File Path="$PSRCDIR/sources_1/ip/clk_wiz_0_2/clk_wiz_0.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/Diviseur.vhd">
|
||||
<File Path="$PPRDIR/sources_snake/Diviseur.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../../../Downloads/VGA Game 2017 V1-20211109/GeneRGB_V1.vhd">
|
||||
<File Path="$PPRDIR/sources_snake/types.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="Library" Val="ourTypes"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/sources_snake/GeneRGB_V1.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../../../Downloads/VGA Game 2017 V1-20211109/GeneSync.vhd">
|
||||
<File Path="$PPRDIR/sources_snake/GeneSync.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/Gene_Position.vhd">
|
||||
<File Path="$PPRDIR/sources_snake/Gene_Snake.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/Gene_Snake.vhd">
|
||||
<File Path="$PPRDIR/sources_snake/updateSnake.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../../../Downloads/VGA Game 2017 V1-20211109/VGA_top.vhd">
|
||||
<File Path="$PPRDIR/sources_snake/RAMController.vhd">
|
||||
<FileInfo SFType="VHDL2008">
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/sources_snake/snakeRam.vhd">
|
||||
<FileInfo SFType="VHDL2008">
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/sources_snake/spritesRom.vhd">
|
||||
<FileInfo SFType="VHDL2008">
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/sources_snake/VGA_top.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/Gene_Balle.vhd">
|
||||
<File Path="$PPRDIR/sources_snake/testBench.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UserDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/sprites/sprites.mem">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
@ -129,7 +160,7 @@
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PPRDIR/../../../../../Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc">
|
||||
<File Path="$PPRDIR/sources_snake/ZYBO_Master.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
@ -1,5 +1,5 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:38:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3133:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
|
||||
@ -29,4 +29,4 @@ version:1
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:32:00:00
|
||||
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3535383763343761323538363466333061393431643931396134353838663432:506172656e742050412070726f6a656374204944:00
|
||||
eof:1227587853
|
||||
eof:2824691014
|
||||
|
||||
Binary file not shown.
@ -23,7 +23,7 @@ eval( EAInclude(ISEJScriptLib) );
|
||||
|
||||
|
||||
// pre-commands:
|
||||
ISETouchFile( "write_bitstream", "begin" );
|
||||
ISETouchFile( "init_design", "begin" );
|
||||
ISEStep( "vivado",
|
||||
"-log VGA_top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace" );
|
||||
|
||||
|
||||
@ -12,29 +12,32 @@ source VGA_top.tcl -notrace
|
||||
Command: link_design -top VGA_top -part xc7z010clg400-1
|
||||
Design is defaulting to srcset: sources_1
|
||||
Design is defaulting to constrset: constrs_1
|
||||
INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.dcp' for cell 'U0'
|
||||
INFO: [Netlist 29-17] Analyzing 35 Unisim elements for replacement
|
||||
INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0.dcp' for cell 'U0'
|
||||
INFO: [Netlist 29-17] Analyzing 314 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-479] Netlist was created with Vivado 2018.3
|
||||
INFO: [Device 21-403] Loading part xc7z010clg400-1
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
|
||||
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
|
||||
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
|
||||
INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
|
||||
get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1248.586 ; gain = 558.375
|
||||
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
|
||||
Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
|
||||
Finished Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
|
||||
WARNING: [Opt 31-35] Removing redundant IBUF, U0/inst/clkin1_ibufg, from the path connected to top-level port: H125MHz
|
||||
Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
|
||||
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'U0/clk_in1' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
|
||||
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0_board.xdc] for cell 'U0/inst'
|
||||
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0_board.xdc] for cell 'U0/inst'
|
||||
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0.xdc] for cell 'U0/inst'
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0.xdc:57]
|
||||
INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0.xdc:57]
|
||||
get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1251.785 ; gain = 552.953
|
||||
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0.xdc] for cell 'U0/inst'
|
||||
Parsing XDC File [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/ZYBO_Master.xdc]
|
||||
Finished Parsing XDC File [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/ZYBO_Master.xdc]
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1248.586 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1251.785 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
10 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
link_design completed successfully
|
||||
link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:16 . Memory (MB): peak = 1248.586 ; gain = 885.598
|
||||
link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:25 . Memory (MB): peak = 1251.785 ; gain = 888.395
|
||||
Command: opt_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
@ -45,57 +48,58 @@ INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Project 1-461] DRC finished with 0 Errors
|
||||
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.499 . Memory (MB): peak = 1248.586 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.501 . Memory (MB): peak = 1251.785 ; gain = 0.000
|
||||
|
||||
Starting Cache Timing Information Task
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [Timing 38-2] Deriving generated clocks
|
||||
Ending Cache Timing Information Task | Checksum: 20ae1d4cd
|
||||
Ending Cache Timing Information Task | Checksum: 19f3e8d5f
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1265.152 ; gain = 16.566
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.092 . Memory (MB): peak = 1265.977 ; gain = 14.191
|
||||
|
||||
Starting Logic Optimization Task
|
||||
|
||||
Phase 1 Retarget
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Opt 31-49] Retargeted 0 cell(s).
|
||||
Phase 1 Retarget | Checksum: ddde5939
|
||||
Phase 1 Retarget | Checksum: c8a6b5ae
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Retarget created 4 cells and removed 4 cells
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.096 . Memory (MB): peak = 1346.285 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
|
||||
INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
||||
|
||||
Phase 2 Constant propagation
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Phase 2 Constant propagation | Checksum: ddde5939
|
||||
Phase 2 Constant propagation | Checksum: 1409f9166
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.123 . Memory (MB): peak = 1346.285 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
|
||||
|
||||
Phase 3 Sweep
|
||||
Phase 3 Sweep | Checksum: fec5e707
|
||||
Phase 3 Sweep | Checksum: 1b7440179
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.178 . Memory (MB): peak = 1346.285 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
|
||||
INFO: [Opt 31-1021] In phase Sweep, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
||||
|
||||
Phase 4 BUFG optimization
|
||||
INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG
|
||||
INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets
|
||||
Phase 4 BUFG optimization | Checksum: 137e6b9d1
|
||||
INFO: [Opt 31-194] Inserted BUFG H125MHz_IBUF_BUFG_inst to drive 182 load(s) on clock net H125MHz_IBUF_BUFG
|
||||
INFO: [Opt 31-193] Inserted 2 BUFG(s) on clock nets
|
||||
Phase 4 BUFG optimization | Checksum: cecab300
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.259 . Memory (MB): peak = 1346.285 ; gain = 0.000
|
||||
INFO: [Opt 31-662] Phase BUFG optimization created 1 cells of which 1 are BUFGs and removed 0 cells.
|
||||
|
||||
Phase 5 Shift Register Optimization
|
||||
Phase 5 Shift Register Optimization | Checksum: 12c29fba6
|
||||
Phase 5 Shift Register Optimization | Checksum: 193828ea0
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.412 . Memory (MB): peak = 1346.285 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
|
||||
|
||||
Phase 6 Post Processing Netlist
|
||||
Phase 6 Post Processing Netlist | Checksum: 10c49128f
|
||||
Phase 6 Post Processing Netlist | Checksum: 16ceef5f4
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.421 . Memory (MB): peak = 1346.285 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
|
||||
Opt_design Change Summary
|
||||
=========================
|
||||
@ -104,10 +108,10 @@ Opt_design Change Summary
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Retarget | 4 | 4 | 1 |
|
||||
| Retarget | 0 | 0 | 1 |
|
||||
| Constant propagation | 0 | 0 | 0 |
|
||||
| Sweep | 0 | 0 | 0 |
|
||||
| BUFG optimization | 0 | 0 | 0 |
|
||||
| Sweep | 0 | 0 | 1 |
|
||||
| BUFG optimization | 1 | 0 | 0 |
|
||||
| Shift Register Optimization | 0 | 0 | 0 |
|
||||
| Post Processing Netlist | 0 | 0 | 0 |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
@ -116,44 +120,70 @@ Opt_design Change Summary
|
||||
|
||||
Starting Connectivity Check Task
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Ending Logic Optimization Task | Checksum: e54fefee
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1346.285 ; gain = 0.000
|
||||
Ending Logic Optimization Task | Checksum: 20356351c
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.057 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.429 . Memory (MB): peak = 1346.285 ; gain = 0.000
|
||||
|
||||
Starting Power Optimization Task
|
||||
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
|
||||
Ending Power Optimization Task | Checksum: e54fefee
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-4.133 | TNS=-46.099 |
|
||||
Running Vector-less Activity Propagation...
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Finished Running Vector-less Activity Propagation
|
||||
INFO: [Pwropt 34-9] Applying IDT optimizations ...
|
||||
INFO: [Pwropt 34-10] Applying ODC optimizations ...
|
||||
|
||||
|
||||
Starting PowerOpt Patch Enables Task
|
||||
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 27 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
|
||||
INFO: [Pwropt 34-201] Structural ODC has moved 16 WE to EN ports
|
||||
Number of BRAM Ports augmented: 0 newly gated: 25 Total Ports: 54
|
||||
Number of Flops added for Enable Generation: 2
|
||||
|
||||
Ending PowerOpt Patch Enables Task | Checksum: 215f1437d
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.085 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
Ending Power Optimization Task | Checksum: 215f1437d
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1500.016 ; gain = 153.730
|
||||
|
||||
Starting Final Cleanup Task
|
||||
Ending Final Cleanup Task | Checksum: e54fefee
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Starting Logic Optimization Task
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG
|
||||
INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets
|
||||
Ending Logic Optimization Task | Checksum: 2182f781c
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.228 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
Ending Final Cleanup Task | Checksum: 2182f781c
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.967 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Starting Netlist Obfuscation Task
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Ending Netlist Obfuscation Task | Checksum: e54fefee
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
Ending Netlist Obfuscation Task | Checksum: 2182f781c
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
40 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
opt_design completed successfully
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
|
||||
Command: report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt.
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt.
|
||||
report_drc completed successfully
|
||||
Command: place_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
@ -172,48 +202,56 @@ INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of
|
||||
Phase 1 Placer Initialization
|
||||
|
||||
Phase 1.1 Placer Initialization Netlist Sorting
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 4ed236ad
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 131936915
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1a1c16c9c
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: d8624408
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.262 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.459 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Phase 1.3 Build Placer Netlist Model
|
||||
Phase 1.3 Build Placer Netlist Model | Checksum: 2939760d0
|
||||
Phase 1.3 Build Placer Netlist Model | Checksum: 1315496dd
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.351 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.837 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Phase 1.4 Constrain Clocks/Macros
|
||||
Phase 1.4 Constrain Clocks/Macros | Checksum: 2939760d0
|
||||
Phase 1.4 Constrain Clocks/Macros | Checksum: 1315496dd
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.353 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Phase 1 Placer Initialization | Checksum: 2939760d0
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.840 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
Phase 1 Placer Initialization | Checksum: 1315496dd
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.353 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.843 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Phase 2 Global Placement
|
||||
|
||||
Phase 2.1 Floorplanning
|
||||
Phase 2.1 Floorplanning | Checksum: 28231f14d
|
||||
Phase 2.1 Floorplanning | Checksum: 1a8bfe1e0
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.397 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.991 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Phase 2.2 Physical Synthesis In Placer
|
||||
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
|
||||
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
|
||||
INFO: [Physopt 32-117] Net SNAKE/listRefs[8][0] could not be optimized because driver SNAKE/mem_reg_3_i_4 could not be replicated
|
||||
INFO: [Physopt 32-117] Net SNAKE/listRefs[6][2] could not be optimized because driver SNAKE/mem_reg_1_i_4 could not be replicated
|
||||
INFO: [Physopt 32-68] No nets found for critical-cell optimization.
|
||||
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
|
||||
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
INFO: [Physopt 32-949] No candidate nets found for HD net replication
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Summary of Physical Synthesis Optimizations
|
||||
============================================
|
||||
@ -223,60 +261,71 @@ Summary of Physical Synthesis Optimizations
|
||||
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| Critical Cell | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 |
|
||||
| Total | 0 | 0 | 0 | 0 | 6 | 00:00:00 |
|
||||
----------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Phase 2.2 Physical Synthesis In Placer | Checksum: 22348ffd6
|
||||
Phase 2.2 Physical Synthesis In Placer | Checksum: aaf1c87e
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Phase 2 Global Placement | Checksum: 2038a7242
|
||||
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
Phase 2 Global Placement | Checksum: 17a0bd3eb
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Phase 3 Detail Placement
|
||||
|
||||
Phase 3.1 Commit Multi Column Macros
|
||||
Phase 3.1 Commit Multi Column Macros | Checksum: 2038a7242
|
||||
Phase 3.1 Commit Multi Column Macros | Checksum: 17a0bd3eb
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 2c58c3354
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 18c86a722
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Phase 3.3 Area Swap Optimization
|
||||
Phase 3.3 Area Swap Optimization | Checksum: 279aeb7b4
|
||||
Phase 3.3 Area Swap Optimization | Checksum: 19f5ea993
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Phase 3.4 Pipeline Register Optimization
|
||||
Phase 3.4 Pipeline Register Optimization | Checksum: 279aeb7b4
|
||||
Phase 3.4 Pipeline Register Optimization | Checksum: 1bfb8a901
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Phase 3.5 Small Shape Detail Placement
|
||||
Phase 3.5 Small Shape Detail Placement | Checksum: 1e0aaeea1
|
||||
Phase 3.5 Fast Optimization
|
||||
Phase 3.5 Fast Optimization | Checksum: 108c906c7
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Phase 3.6 Re-assign LUT pins
|
||||
Phase 3.6 Re-assign LUT pins | Checksum: 2d338840d
|
||||
Phase 3.6 Small Shape Detail Placement
|
||||
Phase 3.6 Small Shape Detail Placement | Checksum: 1f5ba145a
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Phase 3.7 Pipeline Register Optimization
|
||||
Phase 3.7 Pipeline Register Optimization | Checksum: 2d338840d
|
||||
Phase 3.7 Re-assign LUT pins
|
||||
Phase 3.7 Re-assign LUT pins | Checksum: 1ca5326f1
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Phase 3 Detail Placement | Checksum: 2d338840d
|
||||
Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Phase 3.8 Pipeline Register Optimization
|
||||
Phase 3.8 Pipeline Register Optimization | Checksum: 1aa2d2687
|
||||
|
||||
Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Phase 3.9 Fast Optimization
|
||||
Phase 3.9 Fast Optimization | Checksum: a4f5789a
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
Phase 3 Detail Placement | Checksum: a4f5789a
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Phase 4 Post Placement Optimization and Clean-Up
|
||||
|
||||
@ -284,59 +333,60 @@ Phase 4.1 Post Commit Optimization
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
|
||||
Phase 4.1.1 Post Placement Optimization
|
||||
Post Placement Optimization Initialization | Checksum: 15c68dcd4
|
||||
Post Placement Optimization Initialization | Checksum: 100368e26
|
||||
|
||||
Phase 4.1.1.1 BUFG Insertion
|
||||
INFO: [Place 46-46] BUFG insertion identified 0 candidate nets, 0 success, 0 bufg driver replicated, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason
|
||||
Phase 4.1.1.1 BUFG Insertion | Checksum: 15c68dcd4
|
||||
Phase 4.1.1.1 BUFG Insertion | Checksum: 100368e26
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
INFO: [Place 30-746] Post Placement Timing Summary WNS=35.245. For the most accurate timing information please run report_timing.
|
||||
Phase 4.1.1 Post Placement Optimization | Checksum: 142e419cd
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
INFO: [Place 30-746] Post Placement Timing Summary WNS=-3.374. For the most accurate timing information please run report_timing.
|
||||
Phase 4.1.1 Post Placement Optimization | Checksum: be8bba9e
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Phase 4.1 Post Commit Optimization | Checksum: 142e419cd
|
||||
Time (s): cpu = 00:00:18 ; elapsed = 00:00:16 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
Phase 4.1 Post Commit Optimization | Checksum: be8bba9e
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:18 ; elapsed = 00:00:17 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Phase 4.2 Post Placement Cleanup
|
||||
Phase 4.2 Post Placement Cleanup | Checksum: 142e419cd
|
||||
Phase 4.2 Post Placement Cleanup | Checksum: be8bba9e
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:18 ; elapsed = 00:00:17 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Phase 4.3 Placer Reporting
|
||||
Phase 4.3 Placer Reporting | Checksum: 142e419cd
|
||||
Phase 4.3 Placer Reporting | Checksum: be8bba9e
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:18 ; elapsed = 00:00:17 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Phase 4.4 Final Placement Cleanup
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Phase 4.4 Final Placement Cleanup | Checksum: 20695260e
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
Phase 4.4 Final Placement Cleanup | Checksum: 540ff3bc
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 20695260e
|
||||
Time (s): cpu = 00:00:18 ; elapsed = 00:00:17 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 540ff3bc
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Ending Placer Task | Checksum: 1f2b3c1b8
|
||||
Time (s): cpu = 00:00:18 ; elapsed = 00:00:17 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
Ending Placer Task | Checksum: 531de2ac
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:18 ; elapsed = 00:00:17 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
57 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
75 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
place_design completed successfully
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:17 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.050 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.200 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_io -file VGA_top_io_placed.rpt
|
||||
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb
|
||||
INFO: [runtcl-4] Executing : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt
|
||||
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
||||
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
Command: route_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
@ -348,98 +398,150 @@ INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more in
|
||||
|
||||
Starting Routing Task
|
||||
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
|
||||
Checksum: PlaceDB: f9e7c0c6 ConstDB: 0 ShapeSum: f8cc00f2 RouteDB: 0
|
||||
Checksum: PlaceDB: 3ad47cdf ConstDB: 0 ShapeSum: 184965cd RouteDB: 0
|
||||
|
||||
Phase 1 Build RT Design
|
||||
Phase 1 Build RT Design | Checksum: 9a64d846
|
||||
Phase 1 Build RT Design | Checksum: 13e412dc8
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1417.348 ; gain = 66.250
|
||||
Post Restoration Checksum: NetGraph: 7c5b36de NumContArr: 1e09a168 Constraints: 0 Timing: 0
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
Post Restoration Checksum: NetGraph: 58741a68 NumContArr: e5cd1360 Constraints: 0 Timing: 0
|
||||
|
||||
Phase 2 Router Initialization
|
||||
|
||||
Phase 2.1 Create Timer
|
||||
Phase 2.1 Create Timer | Checksum: 9a64d846
|
||||
Phase 2.1 Create Timer | Checksum: 13e412dc8
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1449.676 ; gain = 98.578
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Phase 2.2 Fix Topology Constraints
|
||||
Phase 2.2 Fix Topology Constraints | Checksum: 9a64d846
|
||||
Phase 2.2 Fix Topology Constraints | Checksum: 13e412dc8
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1455.699 ; gain = 104.602
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Phase 2.3 Pre Route Cleanup
|
||||
Phase 2.3 Pre Route Cleanup | Checksum: 9a64d846
|
||||
Phase 2.3 Pre Route Cleanup | Checksum: 13e412dc8
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1455.699 ; gain = 104.602
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
Number of Nodes with overlaps = 0
|
||||
|
||||
Phase 2.4 Update Timing
|
||||
Phase 2.4 Update Timing | Checksum: 82bae049
|
||||
Phase 2.4 Update Timing | Checksum: 1195a0f5b
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.391 | TNS=0.000 | WHS=-0.239 | THS=-2.915 |
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-3.513 | TNS=-50.092| WHS=-1.636 | THS=-51.724|
|
||||
|
||||
Phase 2 Router Initialization | Checksum: cf693307
|
||||
Phase 2 Router Initialization | Checksum: 12ae7c807
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1500.016 ; gain = 0.000
|
||||
|
||||
Phase 3 Initial Routing
|
||||
Phase 3 Initial Routing | Checksum: 16fee48da
|
||||
Phase 3 Initial Routing | Checksum: 1b62d99da
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
||||
Time (s): cpu = 00:00:24 ; elapsed = 00:00:17 . Memory (MB): peak = 1546.250 ; gain = 46.234
|
||||
|
||||
Phase 4 Rip-up And Reroute
|
||||
|
||||
Phase 4.1 Global Iteration 0
|
||||
Number of Nodes with overlaps = 36
|
||||
Number of Nodes with overlaps = 954
|
||||
Number of Nodes with overlaps = 235
|
||||
Number of Nodes with overlaps = 66
|
||||
Number of Nodes with overlaps = 42
|
||||
Number of Nodes with overlaps = 19
|
||||
Number of Nodes with overlaps = 16
|
||||
Number of Nodes with overlaps = 15
|
||||
Number of Nodes with overlaps = 7
|
||||
Number of Nodes with overlaps = 1
|
||||
Number of Nodes with overlaps = 0
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=33.088 | TNS=0.000 | WHS=N/A | THS=N/A |
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-5.639 | TNS=-90.744| WHS=N/A | THS=N/A |
|
||||
|
||||
Phase 4.1 Global Iteration 0 | Checksum: 1c93f85f6
|
||||
Phase 4.1 Global Iteration 0 | Checksum: 1a754acba
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
||||
Phase 4 Rip-up And Reroute | Checksum: 1c93f85f6
|
||||
Time (s): cpu = 00:01:24 ; elapsed = 00:01:06 . Memory (MB): peak = 1596.598 ; gain = 96.582
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
||||
Phase 4.2 Global Iteration 1
|
||||
Number of Nodes with overlaps = 146
|
||||
Number of Nodes with overlaps = 24
|
||||
Number of Nodes with overlaps = 9
|
||||
Number of Nodes with overlaps = 8
|
||||
Number of Nodes with overlaps = 8
|
||||
Number of Nodes with overlaps = 5
|
||||
Number of Nodes with overlaps = 7
|
||||
Number of Nodes with overlaps = 5
|
||||
Number of Nodes with overlaps = 5
|
||||
Number of Nodes with overlaps = 2
|
||||
Number of Nodes with overlaps = 2
|
||||
Number of Nodes with overlaps = 1
|
||||
Number of Nodes with overlaps = 7
|
||||
Number of Nodes with overlaps = 1
|
||||
Number of Nodes with overlaps = 6
|
||||
Number of Nodes with overlaps = 0
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-5.630 | TNS=-88.178| WHS=N/A | THS=N/A |
|
||||
|
||||
Phase 4.2 Global Iteration 1 | Checksum: 13f25b21c
|
||||
|
||||
Time (s): cpu = 00:02:20 ; elapsed = 00:01:46 . Memory (MB): peak = 1630.195 ; gain = 130.180
|
||||
Phase 4 Rip-up And Reroute | Checksum: 13f25b21c
|
||||
|
||||
Time (s): cpu = 00:02:20 ; elapsed = 00:01:46 . Memory (MB): peak = 1630.195 ; gain = 130.180
|
||||
|
||||
Phase 5 Delay and Skew Optimization
|
||||
|
||||
Phase 5.1 Delay CleanUp
|
||||
Phase 5.1 Delay CleanUp | Checksum: 1c93f85f6
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
||||
Phase 5.1.1 Update Timing
|
||||
Phase 5.1.1 Update Timing | Checksum: 21c9bd585
|
||||
|
||||
Time (s): cpu = 00:02:20 ; elapsed = 00:01:46 . Memory (MB): peak = 1630.195 ; gain = 130.180
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-5.617 | TNS=-86.848| WHS=N/A | THS=N/A |
|
||||
|
||||
Number of Nodes with overlaps = 0
|
||||
Phase 5.1 Delay CleanUp | Checksum: e7e5e811
|
||||
|
||||
Time (s): cpu = 00:02:20 ; elapsed = 00:01:46 . Memory (MB): peak = 1630.195 ; gain = 130.180
|
||||
|
||||
Phase 5.2 Clock Skew Optimization
|
||||
Phase 5.2 Clock Skew Optimization | Checksum: 1c93f85f6
|
||||
Phase 5.2 Clock Skew Optimization | Checksum: e7e5e811
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
||||
Phase 5 Delay and Skew Optimization | Checksum: 1c93f85f6
|
||||
Time (s): cpu = 00:02:20 ; elapsed = 00:01:46 . Memory (MB): peak = 1630.195 ; gain = 130.180
|
||||
Phase 5 Delay and Skew Optimization | Checksum: e7e5e811
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
||||
Time (s): cpu = 00:02:20 ; elapsed = 00:01:46 . Memory (MB): peak = 1630.195 ; gain = 130.180
|
||||
|
||||
Phase 6 Post Hold Fix
|
||||
|
||||
Phase 6.1 Hold Fix Iter
|
||||
|
||||
Phase 6.1.1 Update Timing
|
||||
Phase 6.1.1 Update Timing | Checksum: 144941f51
|
||||
Phase 6.1.1 Update Timing | Checksum: ef9abc12
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=33.241 | TNS=0.000 | WHS=0.083 | THS=0.000 |
|
||||
Time (s): cpu = 00:02:21 ; elapsed = 00:01:47 . Memory (MB): peak = 1630.195 ; gain = 130.180
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-5.617 | TNS=-86.439| WHS=-0.443 | THS=-0.849 |
|
||||
|
||||
Phase 6.1 Hold Fix Iter | Checksum: 144941f51
|
||||
Phase 6.1 Hold Fix Iter | Checksum: 151f6c881
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
||||
Phase 6 Post Hold Fix | Checksum: 144941f51
|
||||
Time (s): cpu = 00:02:22 ; elapsed = 00:01:48 . Memory (MB): peak = 1630.195 ; gain = 130.180
|
||||
WARNING: [Route 35-468] The router encountered 388 pins that are both setup-critical and hold-critical and tried to fix hold violations at the expense of setup slack. Such pins are:
|
||||
RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_302/I0
|
||||
SYNC/ROMAddress_reg[3]_i_146/DI[3]
|
||||
SYNC/ROMAddress_reg[9]_i_237/DI[3]
|
||||
SYNC/ROMAddress[9]_i_588/I0
|
||||
SYNC/ROMAddress[9]_i_595/I0
|
||||
RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_589/I1
|
||||
RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_624/I1
|
||||
SYNC/ROMAddress_reg[9]_i_237/DI[2]
|
||||
SYNC/ROMAddress_reg[9]_i_266/DI[2]
|
||||
SYNC/ROMAddress[3]_i_103/I5
|
||||
.. and 378 more pins.
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
||||
Phase 6 Post Hold Fix | Checksum: 197295544
|
||||
|
||||
Time (s): cpu = 00:02:22 ; elapsed = 00:01:48 . Memory (MB): peak = 1630.195 ; gain = 130.180
|
||||
|
||||
Phase 7 Route finalize
|
||||
|
||||
Router Utilization Summary
|
||||
Global Vertical Routing Utilization = 0.0881194 %
|
||||
Global Horizontal Routing Utilization = 0.100414 %
|
||||
Global Vertical Routing Utilization = 2.83094 %
|
||||
Global Horizontal Routing Utilization = 3.41935 %
|
||||
Routable Net Status*
|
||||
*Does not include unroutable nets such as driverless and loadless.
|
||||
Run report_route_status for detailed report.
|
||||
@ -448,58 +550,90 @@ Router Utilization Summary
|
||||
Number of Partially Routed Nets = 0
|
||||
Number of Node Overlaps = 0
|
||||
|
||||
Phase 7 Route finalize | Checksum: 19cea99c1
|
||||
Congestion Report
|
||||
North Dir 1x1 Area, Max Cong = 54.0541%, No Congested Regions.
|
||||
South Dir 1x1 Area, Max Cong = 79.2793%, No Congested Regions.
|
||||
East Dir 1x1 Area, Max Cong = 60.2941%, No Congested Regions.
|
||||
West Dir 1x1 Area, Max Cong = 75%, No Congested Regions.
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
||||
------------------------------
|
||||
Reporting congestion hotspots
|
||||
------------------------------
|
||||
Direction: North
|
||||
----------------
|
||||
Congested clusters found at Level 0
|
||||
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
|
||||
Direction: South
|
||||
----------------
|
||||
Congested clusters found at Level 0
|
||||
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
|
||||
Direction: East
|
||||
----------------
|
||||
Congested clusters found at Level 0
|
||||
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
|
||||
Direction: West
|
||||
----------------
|
||||
Congested clusters found at Level 0
|
||||
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
|
||||
|
||||
Phase 7 Route finalize | Checksum: 1f1dffd6a
|
||||
|
||||
Time (s): cpu = 00:02:22 ; elapsed = 00:01:48 . Memory (MB): peak = 1630.195 ; gain = 130.180
|
||||
|
||||
Phase 8 Verifying routed nets
|
||||
|
||||
Verification completed successfully
|
||||
Phase 8 Verifying routed nets | Checksum: 19cea99c1
|
||||
Phase 8 Verifying routed nets | Checksum: 1f1dffd6a
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1461.477 ; gain = 110.379
|
||||
Time (s): cpu = 00:02:22 ; elapsed = 00:01:48 . Memory (MB): peak = 1630.195 ; gain = 130.180
|
||||
|
||||
Phase 9 Depositing Routes
|
||||
Phase 9 Depositing Routes | Checksum: 17f26a4e0
|
||||
Phase 9 Depositing Routes | Checksum: 238ddaa41
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1461.477 ; gain = 110.379
|
||||
Time (s): cpu = 00:02:23 ; elapsed = 00:01:49 . Memory (MB): peak = 1630.195 ; gain = 130.180
|
||||
|
||||
Phase 10 Post Router Timing
|
||||
INFO: [Route 35-57] Estimated Timing Summary | WNS=33.241 | TNS=0.000 | WHS=0.083 | THS=0.000 |
|
||||
|
||||
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
|
||||
Phase 10 Post Router Timing | Checksum: 17f26a4e0
|
||||
Phase 10.1 Update Timing
|
||||
Phase 10.1 Update Timing | Checksum: 1f42f7dac
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1461.477 ; gain = 110.379
|
||||
Time (s): cpu = 00:02:23 ; elapsed = 00:01:49 . Memory (MB): peak = 1630.195 ; gain = 130.180
|
||||
INFO: [Route 35-57] Estimated Timing Summary | WNS=-5.617 | TNS=-86.439| WHS=-0.027 | THS=-0.027 |
|
||||
|
||||
WARNING: [Route 35-328] Router estimated timing not met.
|
||||
Resolution: For a complete and accurate timing signoff, report_timing_summary must be run after route_design. Alternatively, route_design can be run with the -timing_summary option to enable a complete timing signoff at the end of route_design.
|
||||
Phase 10 Post Router Timing | Checksum: 1f42f7dac
|
||||
|
||||
Time (s): cpu = 00:02:23 ; elapsed = 00:01:49 . Memory (MB): peak = 1630.195 ; gain = 130.180
|
||||
INFO: [Route 35-16] Router Completed Successfully
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1461.477 ; gain = 110.379
|
||||
Time (s): cpu = 00:02:23 ; elapsed = 00:01:49 . Memory (MB): peak = 1630.195 ; gain = 130.180
|
||||
|
||||
Routing Is Done.
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
74 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
93 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
route_design completed successfully
|
||||
route_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:22 . Memory (MB): peak = 1461.477 ; gain = 110.379
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1461.477 ; gain = 0.000
|
||||
route_design: Time (s): cpu = 00:02:25 ; elapsed = 00:01:52 . Memory (MB): peak = 1630.195 ; gain = 130.180
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1630.195 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1630.195 ; gain = 0.000
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 1461.910 ; gain = 0.434
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1461.910 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.257 . Memory (MB): peak = 1630.195 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
|
||||
Command: report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt.
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt.
|
||||
report_drc completed successfully
|
||||
INFO: [runtcl-4] Executing : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
|
||||
Command: report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [DRC 23-133] Running Methodology with 2 threads
|
||||
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt.
|
||||
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt.
|
||||
report_methodology completed successfully
|
||||
INFO: [runtcl-4] Executing : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
|
||||
Command: report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
|
||||
@ -507,66 +641,33 @@ INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Running Vector-less Activity Propagation...
|
||||
|
||||
Finished Running Vector-less Activity Propagation
|
||||
86 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
105 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
report_power completed successfully
|
||||
INFO: [runtcl-4] Executing : report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb
|
||||
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
|
||||
INFO: [runtcl-4] Executing : report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt
|
||||
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
|
||||
INFO: [runtcl-4] Executing : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt
|
||||
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
INFO: [Common 17-206] Exiting Vivado at Tue Dec 7 12:43:48 2021...
|
||||
|
||||
*** Running vivado
|
||||
with args -log VGA_top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace
|
||||
|
||||
|
||||
****** Vivado v2018.3 (64-bit)
|
||||
**** SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
**** IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
source VGA_top.tcl -notrace
|
||||
Command: open_checkpoint VGA_top_routed.dcp
|
||||
|
||||
Starting open_checkpoint Task
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 250.652 ; gain = 0.000
|
||||
INFO: [Netlist 29-17] Analyzing 35 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-479] Netlist was created with Vivado 2018.3
|
||||
INFO: [Device 21-403] Loading part xc7z010clg400-1
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Timing 38-478] Restoring timing data from binary archive.
|
||||
INFO: [Timing 38-479] Binary timing data restore complete.
|
||||
INFO: [Project 1-856] Restoring constraints from binary archive.
|
||||
INFO: [Project 1-853] Binary constraint restore complete.
|
||||
Reading XDEF placement.
|
||||
Reading placer database...
|
||||
Reading XDEF routing.
|
||||
Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.095 . Memory (MB): peak = 1208.145 ; gain = 0.000
|
||||
Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB |
|
||||
Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.095 . Memory (MB): peak = 1208.145 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1208.145 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
INFO: [Project 1-604] Checkpoint was created with Vivado v2018.3 (64-bit) build 2405991
|
||||
open_checkpoint: Time (s): cpu = 00:00:12 ; elapsed = 00:00:17 . Memory (MB): peak = 1208.145 ; gain = 957.492
|
||||
Command: write_bitstream -force VGA_top.bit
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
Running DRC as a precondition to command write_bitstream
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1704] No user IP repositories specified
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.3/data/ip'.
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
WARNING: [DRC PDRC-153] Gated clock check: Net UPD/dataOut_reg[18]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[18]_LDC_i_1/O, cell UPD/dataOut_reg[18]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
||||
WARNING: [DRC PDRC-153] Gated clock check: Net UPD/dataOut_reg[19]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[19]_LDC_i_1/O, cell UPD/dataOut_reg[19]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
||||
WARNING: [DRC PDRC-153] Gated clock check: Net UPD/dataOut_reg[1]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[1]_LDC_i_1/O, cell UPD/dataOut_reg[1]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
||||
WARNING: [DRC PDRC-153] Gated clock check: Net UPD/dataOut_reg[20]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[20]_LDC_i_1/O, cell UPD/dataOut_reg[20]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
||||
WARNING: [DRC PDRC-153] Gated clock check: Net UPD/dataOut_reg[21]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[21]_LDC_i_1/O, cell UPD/dataOut_reg[21]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
||||
WARNING: [DRC PDRC-153] Gated clock check: Net UPD/dataOut_reg[4]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[4]_LDC_i_1/O, cell UPD/dataOut_reg[4]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
||||
WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
|
||||
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings
|
||||
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 7 Warnings
|
||||
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
|
||||
INFO: [Designutils 20-2272] Running write_bitstream with 2 threads.
|
||||
Loading data files...
|
||||
@ -577,9 +678,9 @@ Creating bitmap...
|
||||
Creating bitstream...
|
||||
Writing bitstream ./VGA_top.bit...
|
||||
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
|
||||
INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
|
||||
INFO: [Project 1-118] WebTalk data collection is enabled (User setting is ON. Install Setting is ON.).
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
22 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
124 Infos, 11 Warnings, 1 Critical Warnings and 0 Errors encountered.
|
||||
write_bitstream completed successfully
|
||||
write_bitstream: Time (s): cpu = 00:00:10 ; elapsed = 00:00:28 . Memory (MB): peak = 1679.344 ; gain = 471.199
|
||||
INFO: [Common 17-206] Exiting Vivado at Tue Dec 7 12:44:53 2021...
|
||||
write_bitstream: Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1942.887 ; gain = 312.691
|
||||
INFO: [Common 17-206] Exiting Vivado at Tue Jan 4 12:21:36 2022...
|
||||
|
||||
@ -24,7 +24,7 @@ else
|
||||
fi
|
||||
export LD_LIBRARY_PATH
|
||||
|
||||
HD_PWD='C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1'
|
||||
HD_PWD='C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1'
|
||||
cd "$HD_PWD"
|
||||
|
||||
HD_LOG=runme.log
|
||||
@ -41,7 +41,7 @@ EAStep()
|
||||
}
|
||||
|
||||
# pre-commands:
|
||||
/bin/touch .write_bitstream.begin.rst
|
||||
/bin/touch .init_design.begin.rst
|
||||
EAStep vivado -log VGA_top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace
|
||||
|
||||
|
||||
|
||||
@ -4,13 +4,13 @@
|
||||
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
|
||||
<TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>2405991</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Tue Dec 7 12:44:52 2021</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Tue Jan 4 12:21:35 2022</TD>
|
||||
<TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>WIN64</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>Vivado v2018.3 (64-bit)</TD>
|
||||
<TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>5587c47a25864f30a941d919a4588f42</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>43</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>49</TD>
|
||||
<TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>5c5083d208095dd793a4532428ca92e6</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>5c5083d208095dd793a4532428ca92e6</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>174121763_1777493939_210660961_260</TD>
|
||||
<TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>TRUE</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>target_device</B></TD><TD>xc7z010</TD>
|
||||
<TD BGCOLOR='#DBE5F1'><B>target_family</B></TD><TD>zynq</TD>
|
||||
@ -34,101 +34,122 @@
|
||||
<TR ALIGN='LEFT'> <TD>abstractcombinedpanel_add_element=9</TD>
|
||||
<TD>abstractcombinedpanel_remove_selected_elements=2</TD>
|
||||
<TD>abstractfileview_close=1</TD>
|
||||
<TD>basedialog_cancel=45</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>basedialog_close=1</TD>
|
||||
<TD>basedialog_no=1</TD>
|
||||
<TD>basedialog_ok=396</TD>
|
||||
<TD>basedialog_yes=2</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>constraintschooserpanel_add_files=1</TD>
|
||||
<TD>coretreetablepanel_core_tree_table=18</TD>
|
||||
<TD>abstractfileview_reload=2</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>addsrcwizard_specify_or_create_constraint_files=1</TD>
|
||||
<TD>basedialog_cancel=59</TD>
|
||||
<TD>basedialog_close=1</TD>
|
||||
<TD>basedialog_no=3</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>basedialog_ok=474</TD>
|
||||
<TD>basedialog_yes=4</TD>
|
||||
<TD>cmdmsgdialog_ok=2</TD>
|
||||
<TD>confirmsavetexteditsdialog_no=1</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>constraintschooserpanel_add_files=2</TD>
|
||||
<TD>coretreetablepanel_core_tree_table=24</TD>
|
||||
<TD>createnewdiagramdialog_design_name=1</TD>
|
||||
<TD>createsrcfiledialog_file_name=5</TD>
|
||||
<TD>definemodulesdialog_define_modules_and_specify_io_ports=95</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>filesetpanel_file_set_panel_tree=157</TD>
|
||||
<TD>flownavigatortreepanel_flow_navigator_tree=206</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>definemodulesdialog_define_modules_and_specify_io_ports=95</TD>
|
||||
<TD>filesetpanel_file_set_panel_tree=209</TD>
|
||||
<TD>flownavigatortreepanel_flow_navigator_tree=261</TD>
|
||||
<TD>fpgachooser_fpga_table=1</TD>
|
||||
<TD>gettingstartedview_create_new_project=1</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>hcodeeditor_blank_operations=17</TD>
|
||||
<TD>hcodeeditor_close=1</TD>
|
||||
<TD>hcodeeditor_commands_to_fold_text=2</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>gettingstartedview_create_new_project=2</TD>
|
||||
<TD>gettingstartedview_open_project=1</TD>
|
||||
<TD>hcodeeditor_blank_operations=17</TD>
|
||||
<TD>hcodeeditor_close=3</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>hcodeeditor_commands_to_fold_text=2</TD>
|
||||
<TD>hcodeeditor_diff_with=8</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>hcodeeditor_search_text_combo_box=15</TD>
|
||||
<TD>hcodeeditor_search_text_combo_box=20</TD>
|
||||
<TD>hinputhandler_indent_selection=1</TD>
|
||||
<TD>hinputhandler_toggle_line_comments=37</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>hinputhandler_toggle_line_comments=40</TD>
|
||||
<TD>hinputhandler_unindent_selection=2</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>hpopuptitle_close=1</TD>
|
||||
<TD>hpopuptitle_close=1</TD>
|
||||
<TD>logmonitor_monitor=3</TD>
|
||||
<TD>msgtreepanel_manage_suppression=1</TD>
|
||||
<TD>msgtreepanel_message_view_tree=79</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>msgview_clear_messages_resulting_from_user_executed=1</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>msgtreepanel_manage_suppression=1</TD>
|
||||
<TD>msgtreepanel_message_view_tree=137</TD>
|
||||
<TD>msgview_clear_messages_resulting_from_user_executed=4</TD>
|
||||
<TD>msgview_critical_warnings=2</TD>
|
||||
<TD>msgview_error_messages=4</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>msgview_error_messages=4</TD>
|
||||
<TD>msgview_information_messages=3</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>msgview_warning_messages=9</TD>
|
||||
<TD>numjobschooser_number_of_jobs=2</TD>
|
||||
<TD>pacommandnames_auto_connect_target=16</TD>
|
||||
<TD>pacommandnames_auto_update_hier=11</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>pacommandnames_goto_implemented_design=1</TD>
|
||||
<TD>pacommandnames_goto_netlist_design=1</TD>
|
||||
<TD>msgview_warning_messages=11</TD>
|
||||
<TD>netlisttreeview_netlist_tree=4</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>numjobschooser_number_of_jobs=3</TD>
|
||||
<TD>pacommandnames_auto_connect_target=18</TD>
|
||||
<TD>pacommandnames_auto_update_hier=15</TD>
|
||||
<TD>pacommandnames_goto_implemented_design=2</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>pacommandnames_goto_netlist_design=1</TD>
|
||||
<TD>pacommandnames_log_window=1</TD>
|
||||
<TD>pacommandnames_message_window=2</TD>
|
||||
<TD>pacommandnames_open_hardware_manager=2</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>pacommandnames_recustomize_core=1</TD>
|
||||
<TD>pacommandnames_run_bitgen=42</TD>
|
||||
<TD>pacommandnames_run_bitgen=45</TD>
|
||||
<TD>pacommandnames_run_implementation=8</TD>
|
||||
<TD>paviews_code=5</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>paviews_device=3</TD>
|
||||
<TD>paviews_ip_catalog=1</TD>
|
||||
<TD>paviews_project_summary=21</TD>
|
||||
<TD>paviews_schematic=9</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>programdebugtab_refresh_device=1</TD>
|
||||
<TD>programfpgadialog_program=45</TD>
|
||||
<TD>progressdialog_background=4</TD>
|
||||
<TD>pacommandnames_src_disable=1</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>paviews_code=7</TD>
|
||||
<TD>paviews_device=3</TD>
|
||||
<TD>paviews_ip_catalog=2</TD>
|
||||
<TD>paviews_project_summary=26</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>paviews_schematic=10</TD>
|
||||
<TD>programdebugtab_program_device=1</TD>
|
||||
<TD>programdebugtab_refresh_device=2</TD>
|
||||
<TD>programfpgadialog_program=51</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>progressdialog_background=5</TD>
|
||||
<TD>progressdialog_cancel=5</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>projectnamechooser_project_name=1</TD>
|
||||
<TD>projecttab_reload=6</TD>
|
||||
<TD>rdicommands_delete=4</TD>
|
||||
<TD>projectnamechooser_project_name=1</TD>
|
||||
<TD>projecttab_reload=9</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>rdicommands_copy=1</TD>
|
||||
<TD>rdicommands_delete=8</TD>
|
||||
<TD>removesourcesdialog_also_delete=2</TD>
|
||||
<TD>rungadget_show_warning_and_error_messages_in_messages=2</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>saveprojectutils_dont_save=8</TD>
|
||||
<TD>saveprojectutils_save=5</TD>
|
||||
<TD>saveprojectutils_save=6</TD>
|
||||
<TD>schematicview_previous=10</TD>
|
||||
<TD>simpleoutputproductdialog_generate_output_products_immediately=3</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>srcchooserpanel_add_hdl_and_netlist_files_to_your_project=1</TD>
|
||||
<TD>simpleoutputproductdialog_generate_output_products_immediately=4</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>specifylibrarydialog_library_name=1</TD>
|
||||
<TD>srcchooserpanel_add_directories=2</TD>
|
||||
<TD>srcchooserpanel_add_hdl_and_netlist_files_to_your_project=3</TD>
|
||||
<TD>srcchooserpanel_add_or_create_source_file=1</TD>
|
||||
<TD>srcchooserpanel_create_file=6</TD>
|
||||
<TD>srcmenu_ip_documentation=5</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>srcmenu_ip_hierarchy=8</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>srcchooserpanel_create_file=6</TD>
|
||||
<TD>srcfileproppanels_type=4</TD>
|
||||
<TD>srcfiletypecombobox_source_file_type=4</TD>
|
||||
<TD>srcmenu_ip_documentation=6</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>srcmenu_ip_hierarchy=10</TD>
|
||||
<TD>srcmenu_set_library=1</TD>
|
||||
<TD>stalerundialog_no=1</TD>
|
||||
<TD>syntheticagettingstartedview_recent_projects=4</TD>
|
||||
<TD>syntheticastatemonitor_cancel=5</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>taskbanner_close=16</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>syntheticastatemonitor_cancel=7</TD>
|
||||
<TD>taskbanner_close=19</TD>
|
||||
</TR> </TABLE>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>java_command_handlers</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>addsources=6</TD>
|
||||
<TD>autoconnecttarget=16</TD>
|
||||
<TD>coreview=3</TD>
|
||||
<TD>customizecore=4</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>editdelete=4</TD>
|
||||
<TD>editpaste=2</TD>
|
||||
<TR ALIGN='LEFT'> <TD>addsources=11</TD>
|
||||
<TD>autoconnecttarget=18</TD>
|
||||
<TD>coreview=4</TD>
|
||||
<TD>createblockdesign=3</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>customizecore=5</TD>
|
||||
<TD>editdelete=9</TD>
|
||||
<TD>editpaste=3</TD>
|
||||
<TD>editundo=1</TD>
|
||||
<TD>launchprogramfpga=45</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>newproject=1</TD>
|
||||
<TD>openhardwaremanager=67</TD>
|
||||
<TD>openrecenttarget=21</TD>
|
||||
<TD>programdevice=45</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>recustomizecore=3</TD>
|
||||
<TD>runbitgen=45</TD>
|
||||
<TD>runimplementation=59</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>fliptoviewtaskrtlanalysis=1</TD>
|
||||
<TD>launchprogramfpga=51</TD>
|
||||
<TD>newproject=2</TD>
|
||||
<TD>openhardwaremanager=74</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>openproject=1</TD>
|
||||
<TD>openrecenttarget=24</TD>
|
||||
<TD>programdevice=50</TD>
|
||||
<TD>recustomizecore=3</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>runbitgen=54</TD>
|
||||
<TD>runimplementation=68</TD>
|
||||
<TD>runschematic=7</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>runsynthesis=92</TD>
|
||||
<TD>savefileproxyhandler=3</TD>
|
||||
<TD>showview=24</TD>
|
||||
<TD>runsynthesis=114</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>savefileproxyhandler=3</TD>
|
||||
<TD>setsourceenabled=1</TD>
|
||||
<TD>showview=35</TD>
|
||||
<TD>viewtaskimplementation=8</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>viewtaskrtlanalysis=3</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>viewtaskrtlanalysis=7</TD>
|
||||
<TD>viewtasksynthesis=2</TD>
|
||||
</TR> </TABLE>
|
||||
</TR><TR ALIGN='LEFT'> <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>other_data</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>guimode=5</TD>
|
||||
<TR ALIGN='LEFT'> <TD>guimode=6</TD>
|
||||
</TR> </TABLE>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>project_data</B></TD></TR>
|
||||
@ -154,7 +175,7 @@
|
||||
<TD>launch_simulation_vcs=0</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>launch_simulation_xsim=0</TD>
|
||||
<TD>simulator_language=VHDL</TD>
|
||||
<TD>srcsetcount=8</TD>
|
||||
<TD>srcsetcount=13</TD>
|
||||
<TD>synthesisstrategy=Vivado Synthesis Defaults</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>target_language=VHDL</TD>
|
||||
<TD>target_simulator=XSim</TD>
|
||||
@ -168,38 +189,83 @@
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>post_unisim_transformation</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>bufg=2</TD>
|
||||
<TD>carry4=34</TD>
|
||||
<TD>fdre=21</TD>
|
||||
<TD>gnd=2</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>ibuf=1</TD>
|
||||
<TD>lut1=4</TD>
|
||||
<TD>lut2=28</TD>
|
||||
<TD>lut3=7</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>lut4=62</TD>
|
||||
<TD>lut5=47</TD>
|
||||
<TD>lut6=65</TD>
|
||||
<TD>carry4=266</TD>
|
||||
<TD>fdce=62</TD>
|
||||
<TD>fdpe=10</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>fdre=114</TD>
|
||||
<TD>fdse=1</TD>
|
||||
<TD>gnd=11</TD>
|
||||
<TD>ibuf=2</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>ldce=23</TD>
|
||||
<TD>lut1=12</TD>
|
||||
<TD>lut2=275</TD>
|
||||
<TD>lut3=323</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>lut4=365</TD>
|
||||
<TD>lut5=358</TD>
|
||||
<TD>lut6=447</TD>
|
||||
<TD>mmcme2_adv=1</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>obuf=18</TD>
|
||||
<TD>vcc=2</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>muxf7=19</TD>
|
||||
<TD>muxf8=1</TD>
|
||||
<TD>obuf=21</TD>
|
||||
<TD>obuft=1</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>ramb18e1=9</TD>
|
||||
<TD>ramb36e1=18</TD>
|
||||
<TD>vcc=11</TD>
|
||||
</TR> </TABLE>
|
||||
</TD></TR>
|
||||
<TR><TD>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>pre_unisim_transformation</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>bufg=2</TD>
|
||||
<TD>carry4=34</TD>
|
||||
<TD>fdre=21</TD>
|
||||
<TD>gnd=2</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>ibuf=1</TD>
|
||||
<TD>lut1=4</TD>
|
||||
<TD>lut2=28</TD>
|
||||
<TD>lut3=7</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>lut4=62</TD>
|
||||
<TD>lut5=47</TD>
|
||||
<TD>lut6=65</TD>
|
||||
<TD>carry4=266</TD>
|
||||
<TD>fdce=62</TD>
|
||||
<TD>fdpe=10</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>fdre=114</TD>
|
||||
<TD>fdse=1</TD>
|
||||
<TD>gnd=11</TD>
|
||||
<TD>ibuf=3</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>ldce=23</TD>
|
||||
<TD>lut1=12</TD>
|
||||
<TD>lut2=275</TD>
|
||||
<TD>lut3=323</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>lut4=365</TD>
|
||||
<TD>lut5=358</TD>
|
||||
<TD>lut6=447</TD>
|
||||
<TD>mmcme2_adv=1</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>obuf=18</TD>
|
||||
<TD>vcc=2</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>muxf7=19</TD>
|
||||
<TD>muxf8=1</TD>
|
||||
<TD>obuf=21</TD>
|
||||
<TD>obuft=1</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>ramb18e1=9</TD>
|
||||
<TD>ramb36e1=18</TD>
|
||||
<TD>vcc=11</TD>
|
||||
</TR> </TABLE>
|
||||
</TD></TR>
|
||||
</TABLE><BR>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>power_opt_design</B></TD></TR>
|
||||
<TR><TD>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options_spo</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>-cell_types=default::all</TD>
|
||||
<TD>-clocks=default::[not_specified]</TD>
|
||||
<TD>-exclude_cells=default::[not_specified]</TD>
|
||||
<TD>-include_cells=default::[not_specified]</TD>
|
||||
</TR> </TABLE>
|
||||
</TD></TR>
|
||||
<TR><TD>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>bram_ports_augmented=0</TD>
|
||||
<TD>bram_ports_newly_gated=25</TD>
|
||||
<TD>bram_ports_total=54</TD>
|
||||
<TD>flow_state=default</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>slice_registers_augmented=0</TD>
|
||||
<TD>slice_registers_newly_gated=0</TD>
|
||||
<TD>slice_registers_total=187</TD>
|
||||
<TD>srls_augmented=0</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>srls_newly_gated=0</TD>
|
||||
<TD>srls_total=0</TD>
|
||||
</TR> </TABLE>
|
||||
</TD></TR>
|
||||
</TABLE><BR>
|
||||
@ -257,7 +323,208 @@
|
||||
<TR><TD>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>results</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>zps7-1=1</TD>
|
||||
<TR ALIGN='LEFT'> <TD>pdrc-153=6</TD>
|
||||
<TD>zps7-1=1</TD>
|
||||
</TR> </TABLE>
|
||||
</TD></TR>
|
||||
</TABLE><BR>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_methodology</B></TD></TR>
|
||||
<TR><TD>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>-append=default::[not_specified]</TD>
|
||||
<TD>-checks=default::[not_specified]</TD>
|
||||
<TD>-fail_on=default::[not_specified]</TD>
|
||||
<TD>-force=default::[not_specified]</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>-format=default::[not_specified]</TD>
|
||||
<TD>-messages=default::[not_specified]</TD>
|
||||
<TD>-name=default::[not_specified]</TD>
|
||||
<TD>-return_string=default::[not_specified]</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>-slack_lesser_than=default::[not_specified]</TD>
|
||||
<TD>-waived=default::[not_specified]</TD>
|
||||
</TR> </TABLE>
|
||||
</TD></TR>
|
||||
<TR><TD>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>results</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>lutar-1=14</TD>
|
||||
<TD>synth-6=26</TD>
|
||||
<TD>timing-16=21</TD>
|
||||
<TD>timing-18=5</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>timing-20=23</TD>
|
||||
<TD>timing-27=1</TD>
|
||||
<TD>timing-4=1</TD>
|
||||
<TD>timing-6=2</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>timing-7=2</TD>
|
||||
</TR> </TABLE>
|
||||
</TD></TR>
|
||||
</TABLE><BR>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_power</B></TD></TR>
|
||||
<TR><TD>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>-advisory=default::[not_specified]</TD>
|
||||
<TD>-append=default::[not_specified]</TD>
|
||||
<TD>-file=[specified]</TD>
|
||||
<TD>-format=default::text</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>-hier=default::power</TD>
|
||||
<TD>-hierarchical_depth=default::4</TD>
|
||||
<TD>-l=default::[not_specified]</TD>
|
||||
<TD>-name=default::[not_specified]</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>-no_propagation=default::[not_specified]</TD>
|
||||
<TD>-return_string=default::[not_specified]</TD>
|
||||
<TD>-rpx=[specified]</TD>
|
||||
<TD>-verbose=default::[not_specified]</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>-vid=default::[not_specified]</TD>
|
||||
<TD>-xpe=default::[not_specified]</TD>
|
||||
</TR> </TABLE>
|
||||
</TD></TR>
|
||||
<TR><TD>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>airflow=250 (LFM)</TD>
|
||||
<TD>ambient_temp=25.0 (C)</TD>
|
||||
<TD>bi-dir_toggle=12.500000</TD>
|
||||
<TD>bidir_output_enable=1.000000</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>board_layers=8to11 (8 to 11 Layers)</TD>
|
||||
<TD>board_selection=medium (10"x10")</TD>
|
||||
<TD>bram=0.074844</TD>
|
||||
<TD>clocks=0.003860</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>confidence_level_clock_activity=Medium</TD>
|
||||
<TD>confidence_level_design_state=High</TD>
|
||||
<TD>confidence_level_device_models=High</TD>
|
||||
<TD>confidence_level_internal_activity=Medium</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>confidence_level_io_activity=Medium</TD>
|
||||
<TD>confidence_level_overall=Medium</TD>
|
||||
<TD>customer=TBD</TD>
|
||||
<TD>customer_class=TBD</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>devstatic=0.096510</TD>
|
||||
<TD>die=xc7z010clg400-1</TD>
|
||||
<TD>dsp_output_toggle=12.500000</TD>
|
||||
<TD>dynamic=0.201475</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>effective_thetaja=11.5</TD>
|
||||
<TD>enable_probability=0.990000</TD>
|
||||
<TD>family=zynq</TD>
|
||||
<TD>ff_toggle=12.500000</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>flow_state=routed</TD>
|
||||
<TD>heatsink=none</TD>
|
||||
<TD>i/o=0.001879</TD>
|
||||
<TD>input_toggle=12.500000</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>junction_temp=28.4 (C)</TD>
|
||||
<TD>logic=0.002055</TD>
|
||||
<TD>mgtavcc_dynamic_current=0.000000</TD>
|
||||
<TD>mgtavcc_static_current=0.000000</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>mgtavcc_total_current=0.000000</TD>
|
||||
<TD>mgtavcc_voltage=1.000000</TD>
|
||||
<TD>mgtavtt_dynamic_current=0.000000</TD>
|
||||
<TD>mgtavtt_static_current=0.000000</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>mgtavtt_total_current=0.000000</TD>
|
||||
<TD>mgtavtt_voltage=1.200000</TD>
|
||||
<TD>mgtvccaux_dynamic_current=0.000000</TD>
|
||||
<TD>mgtvccaux_static_current=0.000000</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>mgtvccaux_total_current=0.000000</TD>
|
||||
<TD>mgtvccaux_voltage=1.800000</TD>
|
||||
<TD>mmcm=0.115225</TD>
|
||||
<TD>netlist_net_matched=NA</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>off-chip_power=0.000000</TD>
|
||||
<TD>on-chip_power=0.297985</TD>
|
||||
<TD>output_enable=1.000000</TD>
|
||||
<TD>output_load=5.000000</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>output_toggle=12.500000</TD>
|
||||
<TD>package=clg400</TD>
|
||||
<TD>pct_clock_constrained=1.000000</TD>
|
||||
<TD>pct_inputs_defined=50</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>platform=nt64</TD>
|
||||
<TD>process=typical</TD>
|
||||
<TD>ram_enable=50.000000</TD>
|
||||
<TD>ram_write=50.000000</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>read_saif=False</TD>
|
||||
<TD>set/reset_probability=0.000000</TD>
|
||||
<TD>signal_rate=False</TD>
|
||||
<TD>signals=0.003612</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>simulation_file=None</TD>
|
||||
<TD>speedgrade=-1</TD>
|
||||
<TD>static_prob=False</TD>
|
||||
<TD>temp_grade=commercial</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>thetajb=9.3 (C/W)</TD>
|
||||
<TD>thetasa=0.0 (C/W)</TD>
|
||||
<TD>toggle_rate=False</TD>
|
||||
<TD>user_board_temp=25.0 (C)</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>user_effective_thetaja=11.5</TD>
|
||||
<TD>user_junc_temp=28.4 (C)</TD>
|
||||
<TD>user_thetajb=9.3 (C/W)</TD>
|
||||
<TD>user_thetasa=0.0 (C/W)</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>vccadc_dynamic_current=0.000000</TD>
|
||||
<TD>vccadc_static_current=0.020000</TD>
|
||||
<TD>vccadc_total_current=0.020000</TD>
|
||||
<TD>vccadc_voltage=1.800000</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>vccaux_dynamic_current=0.064022</TD>
|
||||
<TD>vccaux_io_dynamic_current=0.000000</TD>
|
||||
<TD>vccaux_io_static_current=0.000000</TD>
|
||||
<TD>vccaux_io_total_current=0.000000</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>vccaux_io_voltage=1.800000</TD>
|
||||
<TD>vccaux_static_current=0.005617</TD>
|
||||
<TD>vccaux_total_current=0.069639</TD>
|
||||
<TD>vccaux_voltage=1.800000</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>vccbram_dynamic_current=0.006550</TD>
|
||||
<TD>vccbram_static_current=0.001052</TD>
|
||||
<TD>vccbram_total_current=0.007602</TD>
|
||||
<TD>vccbram_voltage=1.000000</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>vccint_dynamic_current=0.078006</TD>
|
||||
<TD>vccint_static_current=0.004501</TD>
|
||||
<TD>vccint_total_current=0.082507</TD>
|
||||
<TD>vccint_voltage=1.000000</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>vcco12_dynamic_current=0.000000</TD>
|
||||
<TD>vcco12_static_current=0.000000</TD>
|
||||
<TD>vcco12_total_current=0.000000</TD>
|
||||
<TD>vcco12_voltage=1.200000</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>vcco135_dynamic_current=0.000000</TD>
|
||||
<TD>vcco135_static_current=0.000000</TD>
|
||||
<TD>vcco135_total_current=0.000000</TD>
|
||||
<TD>vcco135_voltage=1.350000</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>vcco15_dynamic_current=0.000000</TD>
|
||||
<TD>vcco15_static_current=0.000000</TD>
|
||||
<TD>vcco15_total_current=0.000000</TD>
|
||||
<TD>vcco15_voltage=1.500000</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>vcco18_dynamic_current=0.000000</TD>
|
||||
<TD>vcco18_static_current=0.000000</TD>
|
||||
<TD>vcco18_total_current=0.000000</TD>
|
||||
<TD>vcco18_voltage=1.800000</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>vcco25_dynamic_current=0.000000</TD>
|
||||
<TD>vcco25_static_current=0.000000</TD>
|
||||
<TD>vcco25_total_current=0.000000</TD>
|
||||
<TD>vcco25_voltage=2.500000</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>vcco33_dynamic_current=0.000509</TD>
|
||||
<TD>vcco33_static_current=0.001000</TD>
|
||||
<TD>vcco33_total_current=0.001509</TD>
|
||||
<TD>vcco33_voltage=3.300000</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>vcco_ddr_dynamic_current=0.000000</TD>
|
||||
<TD>vcco_ddr_static_current=0.000000</TD>
|
||||
<TD>vcco_ddr_total_current=0.000000</TD>
|
||||
<TD>vcco_ddr_voltage=1.500000</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>vcco_mio0_dynamic_current=0.000000</TD>
|
||||
<TD>vcco_mio0_static_current=0.000000</TD>
|
||||
<TD>vcco_mio0_total_current=0.000000</TD>
|
||||
<TD>vcco_mio0_voltage=1.800000</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>vcco_mio1_dynamic_current=0.000000</TD>
|
||||
<TD>vcco_mio1_static_current=0.000000</TD>
|
||||
<TD>vcco_mio1_total_current=0.000000</TD>
|
||||
<TD>vcco_mio1_voltage=1.800000</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>vccpaux_dynamic_current=0.000000</TD>
|
||||
<TD>vccpaux_static_current=0.010330</TD>
|
||||
<TD>vccpaux_total_current=0.010330</TD>
|
||||
<TD>vccpaux_voltage=1.800000</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>vccpint_dynamic_current=0.000000</TD>
|
||||
<TD>vccpint_static_current=0.017552</TD>
|
||||
<TD>vccpint_total_current=0.017552</TD>
|
||||
<TD>vccpint_voltage=1.000000</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>vccpll_dynamic_current=0.000000</TD>
|
||||
<TD>vccpll_static_current=0.003000</TD>
|
||||
<TD>vccpll_total_current=0.003000</TD>
|
||||
<TD>vccpll_voltage=1.800000</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>version=2018.3</TD>
|
||||
</TR> </TABLE>
|
||||
</TD></TR>
|
||||
</TABLE><BR>
|
||||
@ -268,8 +535,8 @@
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>clocking</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>bufgctrl_available=32</TD>
|
||||
<TD>bufgctrl_fixed=0</TD>
|
||||
<TD>bufgctrl_used=2</TD>
|
||||
<TD>bufgctrl_util_percentage=6.25</TD>
|
||||
<TD>bufgctrl_used=3</TD>
|
||||
<TD>bufgctrl_util_percentage=9.38</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>bufhce_available=48</TD>
|
||||
<TD>bufhce_fixed=0</TD>
|
||||
<TD>bufhce_used=0</TD>
|
||||
@ -352,45 +619,65 @@
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>memory</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>block_ram_tile_available=60</TD>
|
||||
<TD>block_ram_tile_fixed=0</TD>
|
||||
<TD>block_ram_tile_used=0</TD>
|
||||
<TD>block_ram_tile_util_percentage=0.00</TD>
|
||||
<TD>block_ram_tile_used=22.5</TD>
|
||||
<TD>block_ram_tile_util_percentage=37.50</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>ramb18_available=120</TD>
|
||||
<TD>ramb18_fixed=0</TD>
|
||||
<TD>ramb18_used=0</TD>
|
||||
<TD>ramb18_util_percentage=0.00</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>ramb36_fifo_available=60</TD>
|
||||
<TD>ramb18_used=9</TD>
|
||||
<TD>ramb18_util_percentage=7.50</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>ramb18e1_only_used=9</TD>
|
||||
<TD>ramb36_fifo_available=60</TD>
|
||||
<TD>ramb36_fifo_fixed=0</TD>
|
||||
<TD>ramb36_fifo_used=0</TD>
|
||||
<TD>ramb36_fifo_util_percentage=0.00</TD>
|
||||
<TD>ramb36_fifo_used=18</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>ramb36_fifo_util_percentage=30.00</TD>
|
||||
<TD>ramb36e1_only_used=18</TD>
|
||||
</TR> </TABLE>
|
||||
</TD></TR>
|
||||
<TR><TD>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>primitives</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>bufg_functional_category=Clock</TD>
|
||||
<TD>bufg_used=2</TD>
|
||||
<TD>bufg_used=3</TD>
|
||||
<TD>carry4_functional_category=CarryLogic</TD>
|
||||
<TD>carry4_used=34</TD>
|
||||
<TD>carry4_used=266</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>fdce_functional_category=Flop & Latch</TD>
|
||||
<TD>fdce_used=64</TD>
|
||||
<TD>fdpe_functional_category=Flop & Latch</TD>
|
||||
<TD>fdpe_used=10</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>fdre_functional_category=Flop & Latch</TD>
|
||||
<TD>fdre_used=21</TD>
|
||||
<TD>ibuf_functional_category=IO</TD>
|
||||
<TD>ibuf_used=1</TD>
|
||||
<TD>fdre_used=114</TD>
|
||||
<TD>fdse_functional_category=Flop & Latch</TD>
|
||||
<TD>fdse_used=1</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>ibuf_functional_category=IO</TD>
|
||||
<TD>ibuf_used=2</TD>
|
||||
<TD>ldce_functional_category=Flop & Latch</TD>
|
||||
<TD>ldce_used=23</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>lut1_functional_category=LUT</TD>
|
||||
<TD>lut1_used=4</TD>
|
||||
<TD>lut1_used=12</TD>
|
||||
<TD>lut2_functional_category=LUT</TD>
|
||||
<TD>lut2_used=28</TD>
|
||||
<TD>lut2_used=275</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>lut3_functional_category=LUT</TD>
|
||||
<TD>lut3_used=7</TD>
|
||||
<TD>lut3_used=332</TD>
|
||||
<TD>lut4_functional_category=LUT</TD>
|
||||
<TD>lut4_used=64</TD>
|
||||
<TD>lut4_used=365</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>lut5_functional_category=LUT</TD>
|
||||
<TD>lut5_used=47</TD>
|
||||
<TD>lut5_used=358</TD>
|
||||
<TD>lut6_functional_category=LUT</TD>
|
||||
<TD>lut6_used=63</TD>
|
||||
<TD>lut6_used=447</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>mmcme2_adv_functional_category=Clock</TD>
|
||||
<TD>mmcme2_adv_used=1</TD>
|
||||
<TD>muxf7_functional_category=MuxFx</TD>
|
||||
<TD>muxf7_used=19</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>muxf8_functional_category=MuxFx</TD>
|
||||
<TD>muxf8_used=1</TD>
|
||||
<TD>obuf_functional_category=IO</TD>
|
||||
<TD>obuf_used=18</TD>
|
||||
<TD>obuf_used=21</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>obuft_functional_category=IO</TD>
|
||||
<TD>obuft_used=1</TD>
|
||||
<TD>ramb18e1_functional_category=Block Memory</TD>
|
||||
<TD>ramb18e1_used=9</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>ramb36e1_functional_category=Block Memory</TD>
|
||||
<TD>ramb36e1_used=18</TD>
|
||||
</TR> </TABLE>
|
||||
</TD></TR>
|
||||
<TR><TD>
|
||||
@ -398,42 +685,42 @@
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>slice_logic</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>f7_muxes_available=8800</TD>
|
||||
<TD>f7_muxes_fixed=0</TD>
|
||||
<TD>f7_muxes_used=0</TD>
|
||||
<TD>f7_muxes_util_percentage=0.00</TD>
|
||||
<TD>f7_muxes_used=19</TD>
|
||||
<TD>f7_muxes_util_percentage=0.22</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>f8_muxes_available=4400</TD>
|
||||
<TD>f8_muxes_fixed=0</TD>
|
||||
<TD>f8_muxes_used=0</TD>
|
||||
<TD>f8_muxes_util_percentage=0.00</TD>
|
||||
<TD>f8_muxes_used=1</TD>
|
||||
<TD>f8_muxes_util_percentage=0.02</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>lut_as_logic_available=17600</TD>
|
||||
<TD>lut_as_logic_fixed=0</TD>
|
||||
<TD>lut_as_logic_used=168</TD>
|
||||
<TD>lut_as_logic_util_percentage=0.95</TD>
|
||||
<TD>lut_as_logic_used=1491</TD>
|
||||
<TD>lut_as_logic_util_percentage=8.47</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>lut_as_memory_available=6000</TD>
|
||||
<TD>lut_as_memory_fixed=0</TD>
|
||||
<TD>lut_as_memory_used=0</TD>
|
||||
<TD>lut_as_memory_util_percentage=0.00</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>register_as_flip_flop_available=35200</TD>
|
||||
<TD>register_as_flip_flop_fixed=0</TD>
|
||||
<TD>register_as_flip_flop_used=21</TD>
|
||||
<TD>register_as_flip_flop_util_percentage=0.06</TD>
|
||||
<TD>register_as_flip_flop_used=189</TD>
|
||||
<TD>register_as_flip_flop_util_percentage=0.54</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>register_as_latch_available=35200</TD>
|
||||
<TD>register_as_latch_fixed=0</TD>
|
||||
<TD>register_as_latch_used=0</TD>
|
||||
<TD>register_as_latch_util_percentage=0.00</TD>
|
||||
<TD>register_as_latch_used=23</TD>
|
||||
<TD>register_as_latch_util_percentage=0.07</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>slice_luts_available=17600</TD>
|
||||
<TD>slice_luts_fixed=0</TD>
|
||||
<TD>slice_luts_used=168</TD>
|
||||
<TD>slice_luts_util_percentage=0.95</TD>
|
||||
<TD>slice_luts_used=1491</TD>
|
||||
<TD>slice_luts_util_percentage=8.47</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>slice_registers_available=35200</TD>
|
||||
<TD>slice_registers_fixed=0</TD>
|
||||
<TD>slice_registers_used=21</TD>
|
||||
<TD>slice_registers_util_percentage=0.06</TD>
|
||||
<TD>slice_registers_used=212</TD>
|
||||
<TD>slice_registers_util_percentage=0.60</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>lut_as_distributed_ram_fixed=0</TD>
|
||||
<TD>lut_as_distributed_ram_used=0</TD>
|
||||
<TD>lut_as_logic_available=17600</TD>
|
||||
<TD>lut_as_logic_fixed=0</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>lut_as_logic_used=168</TD>
|
||||
<TD>lut_as_logic_util_percentage=0.95</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>lut_as_logic_used=1491</TD>
|
||||
<TD>lut_as_logic_util_percentage=8.47</TD>
|
||||
<TD>lut_as_memory_available=6000</TD>
|
||||
<TD>lut_as_memory_fixed=0</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>lut_as_memory_used=0</TD>
|
||||
@ -441,35 +728,35 @@
|
||||
<TD>lut_as_shift_register_fixed=0</TD>
|
||||
<TD>lut_as_shift_register_used=0</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>lut_in_front_of_the_register_is_unused_fixed=0</TD>
|
||||
<TD>lut_in_front_of_the_register_is_unused_used=0</TD>
|
||||
<TD>lut_in_front_of_the_register_is_used_fixed=0</TD>
|
||||
<TD>lut_in_front_of_the_register_is_used_used=1</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>register_driven_from_outside_the_slice_fixed=1</TD>
|
||||
<TD>register_driven_from_outside_the_slice_used=1</TD>
|
||||
<TD>register_driven_from_within_the_slice_fixed=1</TD>
|
||||
<TD>register_driven_from_within_the_slice_used=20</TD>
|
||||
<TD>lut_in_front_of_the_register_is_unused_used=21</TD>
|
||||
<TD>lut_in_front_of_the_register_is_used_fixed=21</TD>
|
||||
<TD>lut_in_front_of_the_register_is_used_used=26</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>register_driven_from_outside_the_slice_fixed=26</TD>
|
||||
<TD>register_driven_from_outside_the_slice_used=47</TD>
|
||||
<TD>register_driven_from_within_the_slice_fixed=47</TD>
|
||||
<TD>register_driven_from_within_the_slice_used=165</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>slice_available=4400</TD>
|
||||
<TD>slice_fixed=0</TD>
|
||||
<TD>slice_registers_available=35200</TD>
|
||||
<TD>slice_registers_fixed=0</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>slice_registers_used=21</TD>
|
||||
<TD>slice_registers_util_percentage=0.06</TD>
|
||||
<TD>slice_used=61</TD>
|
||||
<TD>slice_util_percentage=1.39</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>slice_registers_used=212</TD>
|
||||
<TD>slice_registers_util_percentage=0.60</TD>
|
||||
<TD>slice_used=541</TD>
|
||||
<TD>slice_util_percentage=12.30</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>slicel_fixed=0</TD>
|
||||
<TD>slicel_used=45</TD>
|
||||
<TD>slicel_used=361</TD>
|
||||
<TD>slicem_fixed=0</TD>
|
||||
<TD>slicem_used=16</TD>
|
||||
<TD>slicem_used=180</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>unique_control_sets_available=4400</TD>
|
||||
<TD>unique_control_sets_fixed=4400</TD>
|
||||
<TD>unique_control_sets_used=2</TD>
|
||||
<TD>unique_control_sets_util_percentage=0.05</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>using_o5_and_o6_fixed=0.05</TD>
|
||||
<TD>using_o5_and_o6_used=45</TD>
|
||||
<TD>using_o5_output_only_fixed=45</TD>
|
||||
<TD>unique_control_sets_used=31</TD>
|
||||
<TD>unique_control_sets_util_percentage=0.70</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>using_o5_and_o6_fixed=0.70</TD>
|
||||
<TD>using_o5_and_o6_used=298</TD>
|
||||
<TD>using_o5_output_only_fixed=298</TD>
|
||||
<TD>using_o5_output_only_used=0</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>using_o6_output_only_fixed=0</TD>
|
||||
<TD>using_o6_output_only_used=123</TD>
|
||||
<TD>using_o6_output_only_used=1193</TD>
|
||||
</TR> </TABLE>
|
||||
</TD></TR>
|
||||
<TR><TD>
|
||||
@ -554,10 +841,10 @@
|
||||
<TR><TD>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>elapsed=00:01:36s</TD>
|
||||
<TR ALIGN='LEFT'> <TD>elapsed=00:00:46s</TD>
|
||||
<TD>hls_ip=0</TD>
|
||||
<TD>memory_gain=948.426MB</TD>
|
||||
<TD>memory_peak=1310.512MB</TD>
|
||||
<TD>memory_gain=613.590MB</TD>
|
||||
<TD>memory_peak=976.145MB</TD>
|
||||
</TR> </TABLE>
|
||||
</TD></TR>
|
||||
</TABLE><BR>
|
||||
|
||||
@ -1,16 +1,16 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<webTalkData fileName='usage_statistics_webtalk.xml' majorVersion='1' minorVersion='0' timeStamp='Tue Dec 7 12:44:52 2021'>
|
||||
<webTalkData fileName='usage_statistics_webtalk.xml' majorVersion='1' minorVersion='0' timeStamp='Tue Jan 4 12:21:35 2022'>
|
||||
<section name="__ROOT__" level="0" order="1" description="">
|
||||
<section name="software_version_and_target_device" level="1" order="1" description="">
|
||||
<keyValuePair key="beta" value="FALSE" description="" />
|
||||
<keyValuePair key="build_version" value="2405991" description="" />
|
||||
<keyValuePair key="date_generated" value="Tue Dec 7 12:44:52 2021" description="" />
|
||||
<keyValuePair key="date_generated" value="Tue Jan 4 12:21:35 2022" description="" />
|
||||
<keyValuePair key="os_platform" value="WIN64" description="" />
|
||||
<keyValuePair key="product_version" value="Vivado v2018.3 (64-bit)" description="" />
|
||||
<keyValuePair key="project_id" value="5587c47a25864f30a941d919a4588f42" description="" />
|
||||
<keyValuePair key="project_iteration" value="43" description="" />
|
||||
<keyValuePair key="project_iteration" value="49" description="" />
|
||||
<keyValuePair key="random_id" value="5c5083d208095dd793a4532428ca92e6" description="" />
|
||||
<keyValuePair key="registration_id" value="5c5083d208095dd793a4532428ca92e6" description="" />
|
||||
<keyValuePair key="registration_id" value="174121763_1777493939_210660961_260" description="" />
|
||||
<keyValuePair key="route_design" value="TRUE" description="" />
|
||||
<keyValuePair key="target_device" value="xc7z010" description="" />
|
||||
<keyValuePair key="target_family" value="zynq" description="" />
|
||||
@ -52,7 +52,27 @@
|
||||
<keyValuePair key="use_reset" value="false" description="" />
|
||||
</section>
|
||||
</section>
|
||||
<section name="report_drc" level="1" order="4" description="">
|
||||
<section name="power_opt_design" level="1" order="4" description="">
|
||||
<section name="command_line_options_spo" level="2" order="1" description="">
|
||||
<keyValuePair key="-cell_types" value="default::all" description="" />
|
||||
<keyValuePair key="-clocks" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-exclude_cells" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-include_cells" value="default::[not_specified]" description="" />
|
||||
</section>
|
||||
<section name="usage" level="2" order="2" description="">
|
||||
<keyValuePair key="bram_ports_augmented" value="0" description="" />
|
||||
<keyValuePair key="bram_ports_newly_gated" value="25" description="" />
|
||||
<keyValuePair key="bram_ports_total" value="54" description="" />
|
||||
<keyValuePair key="flow_state" value="default" description="" />
|
||||
<keyValuePair key="slice_registers_augmented" value="0" description="" />
|
||||
<keyValuePair key="slice_registers_newly_gated" value="0" description="" />
|
||||
<keyValuePair key="slice_registers_total" value="187" description="" />
|
||||
<keyValuePair key="srls_augmented" value="0" description="" />
|
||||
<keyValuePair key="srls_newly_gated" value="0" description="" />
|
||||
<keyValuePair key="srls_total" value="0" description="" />
|
||||
</section>
|
||||
</section>
|
||||
<section name="report_drc" level="1" order="5" description="">
|
||||
<section name="command_line_options" level="2" order="1" description="">
|
||||
<keyValuePair key="-append" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-checks" value="default::[not_specified]" description="" />
|
||||
@ -70,15 +90,202 @@
|
||||
<keyValuePair key="-waived" value="default::[not_specified]" description="" />
|
||||
</section>
|
||||
<section name="results" level="2" order="2" description="">
|
||||
<keyValuePair key="pdrc-153" value="6" description="" />
|
||||
<keyValuePair key="zps7-1" value="1" description="" />
|
||||
</section>
|
||||
</section>
|
||||
<section name="report_utilization" level="1" order="5" description="">
|
||||
<section name="report_methodology" level="1" order="6" description="">
|
||||
<section name="command_line_options" level="2" order="1" description="">
|
||||
<keyValuePair key="-append" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-checks" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-fail_on" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-force" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-format" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-messages" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-name" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-return_string" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-slack_lesser_than" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-waived" value="default::[not_specified]" description="" />
|
||||
</section>
|
||||
<section name="results" level="2" order="2" description="">
|
||||
<keyValuePair key="lutar-1" value="14" description="" />
|
||||
<keyValuePair key="synth-6" value="26" description="" />
|
||||
<keyValuePair key="timing-16" value="21" description="" />
|
||||
<keyValuePair key="timing-18" value="5" description="" />
|
||||
<keyValuePair key="timing-20" value="23" description="" />
|
||||
<keyValuePair key="timing-27" value="1" description="" />
|
||||
<keyValuePair key="timing-4" value="1" description="" />
|
||||
<keyValuePair key="timing-6" value="2" description="" />
|
||||
<keyValuePair key="timing-7" value="2" description="" />
|
||||
</section>
|
||||
</section>
|
||||
<section name="report_power" level="1" order="7" description="">
|
||||
<section name="command_line_options" level="2" order="1" description="">
|
||||
<keyValuePair key="-advisory" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-append" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-file" value="[specified]" description="" />
|
||||
<keyValuePair key="-format" value="default::text" description="" />
|
||||
<keyValuePair key="-hier" value="default::power" description="" />
|
||||
<keyValuePair key="-hierarchical_depth" value="default::4" description="" />
|
||||
<keyValuePair key="-l" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-name" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-no_propagation" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-return_string" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-rpx" value="[specified]" description="" />
|
||||
<keyValuePair key="-verbose" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-vid" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-xpe" value="default::[not_specified]" description="" />
|
||||
</section>
|
||||
<section name="usage" level="2" order="2" description="">
|
||||
<keyValuePair key="airflow" value="250 (LFM)" description="" />
|
||||
<keyValuePair key="ambient_temp" value="25.0 (C)" description="" />
|
||||
<keyValuePair key="bi-dir_toggle" value="12.500000" description="" />
|
||||
<keyValuePair key="bidir_output_enable" value="1.000000" description="" />
|
||||
<keyValuePair key="board_layers" value="8to11 (8 to 11 Layers)" description="" />
|
||||
<keyValuePair key="board_selection" value="medium (10"x10")" description="" />
|
||||
<keyValuePair key="bram" value="0.074844" description="" />
|
||||
<keyValuePair key="clocks" value="0.003860" description="" />
|
||||
<keyValuePair key="confidence_level_clock_activity" value="Medium" description="" />
|
||||
<keyValuePair key="confidence_level_design_state" value="High" description="" />
|
||||
<keyValuePair key="confidence_level_device_models" value="High" description="" />
|
||||
<keyValuePair key="confidence_level_internal_activity" value="Medium" description="" />
|
||||
<keyValuePair key="confidence_level_io_activity" value="Medium" description="" />
|
||||
<keyValuePair key="confidence_level_overall" value="Medium" description="" />
|
||||
<keyValuePair key="customer" value="TBD" description="" />
|
||||
<keyValuePair key="customer_class" value="TBD" description="" />
|
||||
<keyValuePair key="devstatic" value="0.096510" description="" />
|
||||
<keyValuePair key="die" value="xc7z010clg400-1" description="" />
|
||||
<keyValuePair key="dsp_output_toggle" value="12.500000" description="" />
|
||||
<keyValuePair key="dynamic" value="0.201475" description="" />
|
||||
<keyValuePair key="effective_thetaja" value="11.5" description="" />
|
||||
<keyValuePair key="enable_probability" value="0.990000" description="" />
|
||||
<keyValuePair key="family" value="zynq" description="" />
|
||||
<keyValuePair key="ff_toggle" value="12.500000" description="" />
|
||||
<keyValuePair key="flow_state" value="routed" description="" />
|
||||
<keyValuePair key="heatsink" value="none" description="" />
|
||||
<keyValuePair key="i/o" value="0.001879" description="" />
|
||||
<keyValuePair key="input_toggle" value="12.500000" description="" />
|
||||
<keyValuePair key="junction_temp" value="28.4 (C)" description="" />
|
||||
<keyValuePair key="logic" value="0.002055" description="" />
|
||||
<keyValuePair key="mgtavcc_dynamic_current" value="0.000000" description="" />
|
||||
<keyValuePair key="mgtavcc_static_current" value="0.000000" description="" />
|
||||
<keyValuePair key="mgtavcc_total_current" value="0.000000" description="" />
|
||||
<keyValuePair key="mgtavcc_voltage" value="1.000000" description="" />
|
||||
<keyValuePair key="mgtavtt_dynamic_current" value="0.000000" description="" />
|
||||
<keyValuePair key="mgtavtt_static_current" value="0.000000" description="" />
|
||||
<keyValuePair key="mgtavtt_total_current" value="0.000000" description="" />
|
||||
<keyValuePair key="mgtavtt_voltage" value="1.200000" description="" />
|
||||
<keyValuePair key="mgtvccaux_dynamic_current" value="0.000000" description="" />
|
||||
<keyValuePair key="mgtvccaux_static_current" value="0.000000" description="" />
|
||||
<keyValuePair key="mgtvccaux_total_current" value="0.000000" description="" />
|
||||
<keyValuePair key="mgtvccaux_voltage" value="1.800000" description="" />
|
||||
<keyValuePair key="mmcm" value="0.115225" description="" />
|
||||
<keyValuePair key="netlist_net_matched" value="NA" description="" />
|
||||
<keyValuePair key="off-chip_power" value="0.000000" description="" />
|
||||
<keyValuePair key="on-chip_power" value="0.297985" description="" />
|
||||
<keyValuePair key="output_enable" value="1.000000" description="" />
|
||||
<keyValuePair key="output_load" value="5.000000" description="" />
|
||||
<keyValuePair key="output_toggle" value="12.500000" description="" />
|
||||
<keyValuePair key="package" value="clg400" description="" />
|
||||
<keyValuePair key="pct_clock_constrained" value="1.000000" description="" />
|
||||
<keyValuePair key="pct_inputs_defined" value="50" description="" />
|
||||
<keyValuePair key="platform" value="nt64" description="" />
|
||||
<keyValuePair key="process" value="typical" description="" />
|
||||
<keyValuePair key="ram_enable" value="50.000000" description="" />
|
||||
<keyValuePair key="ram_write" value="50.000000" description="" />
|
||||
<keyValuePair key="read_saif" value="False" description="" />
|
||||
<keyValuePair key="set/reset_probability" value="0.000000" description="" />
|
||||
<keyValuePair key="signal_rate" value="False" description="" />
|
||||
<keyValuePair key="signals" value="0.003612" description="" />
|
||||
<keyValuePair key="simulation_file" value="None" description="" />
|
||||
<keyValuePair key="speedgrade" value="-1" description="" />
|
||||
<keyValuePair key="static_prob" value="False" description="" />
|
||||
<keyValuePair key="temp_grade" value="commercial" description="" />
|
||||
<keyValuePair key="thetajb" value="9.3 (C/W)" description="" />
|
||||
<keyValuePair key="thetasa" value="0.0 (C/W)" description="" />
|
||||
<keyValuePair key="toggle_rate" value="False" description="" />
|
||||
<keyValuePair key="user_board_temp" value="25.0 (C)" description="" />
|
||||
<keyValuePair key="user_effective_thetaja" value="11.5" description="" />
|
||||
<keyValuePair key="user_junc_temp" value="28.4 (C)" description="" />
|
||||
<keyValuePair key="user_thetajb" value="9.3 (C/W)" description="" />
|
||||
<keyValuePair key="user_thetasa" value="0.0 (C/W)" description="" />
|
||||
<keyValuePair key="vccadc_dynamic_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vccadc_static_current" value="0.020000" description="" />
|
||||
<keyValuePair key="vccadc_total_current" value="0.020000" description="" />
|
||||
<keyValuePair key="vccadc_voltage" value="1.800000" description="" />
|
||||
<keyValuePair key="vccaux_dynamic_current" value="0.064022" description="" />
|
||||
<keyValuePair key="vccaux_io_dynamic_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vccaux_io_static_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vccaux_io_total_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vccaux_io_voltage" value="1.800000" description="" />
|
||||
<keyValuePair key="vccaux_static_current" value="0.005617" description="" />
|
||||
<keyValuePair key="vccaux_total_current" value="0.069639" description="" />
|
||||
<keyValuePair key="vccaux_voltage" value="1.800000" description="" />
|
||||
<keyValuePair key="vccbram_dynamic_current" value="0.006550" description="" />
|
||||
<keyValuePair key="vccbram_static_current" value="0.001052" description="" />
|
||||
<keyValuePair key="vccbram_total_current" value="0.007602" description="" />
|
||||
<keyValuePair key="vccbram_voltage" value="1.000000" description="" />
|
||||
<keyValuePair key="vccint_dynamic_current" value="0.078006" description="" />
|
||||
<keyValuePair key="vccint_static_current" value="0.004501" description="" />
|
||||
<keyValuePair key="vccint_total_current" value="0.082507" description="" />
|
||||
<keyValuePair key="vccint_voltage" value="1.000000" description="" />
|
||||
<keyValuePair key="vcco12_dynamic_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vcco12_static_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vcco12_total_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vcco12_voltage" value="1.200000" description="" />
|
||||
<keyValuePair key="vcco135_dynamic_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vcco135_static_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vcco135_total_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vcco135_voltage" value="1.350000" description="" />
|
||||
<keyValuePair key="vcco15_dynamic_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vcco15_static_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vcco15_total_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vcco15_voltage" value="1.500000" description="" />
|
||||
<keyValuePair key="vcco18_dynamic_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vcco18_static_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vcco18_total_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vcco18_voltage" value="1.800000" description="" />
|
||||
<keyValuePair key="vcco25_dynamic_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vcco25_static_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vcco25_total_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vcco25_voltage" value="2.500000" description="" />
|
||||
<keyValuePair key="vcco33_dynamic_current" value="0.000509" description="" />
|
||||
<keyValuePair key="vcco33_static_current" value="0.001000" description="" />
|
||||
<keyValuePair key="vcco33_total_current" value="0.001509" description="" />
|
||||
<keyValuePair key="vcco33_voltage" value="3.300000" description="" />
|
||||
<keyValuePair key="vcco_ddr_dynamic_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vcco_ddr_static_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vcco_ddr_total_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vcco_ddr_voltage" value="1.500000" description="" />
|
||||
<keyValuePair key="vcco_mio0_dynamic_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vcco_mio0_static_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vcco_mio0_total_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vcco_mio0_voltage" value="1.800000" description="" />
|
||||
<keyValuePair key="vcco_mio1_dynamic_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vcco_mio1_static_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vcco_mio1_total_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vcco_mio1_voltage" value="1.800000" description="" />
|
||||
<keyValuePair key="vccpaux_dynamic_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vccpaux_static_current" value="0.010330" description="" />
|
||||
<keyValuePair key="vccpaux_total_current" value="0.010330" description="" />
|
||||
<keyValuePair key="vccpaux_voltage" value="1.800000" description="" />
|
||||
<keyValuePair key="vccpint_dynamic_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vccpint_static_current" value="0.017552" description="" />
|
||||
<keyValuePair key="vccpint_total_current" value="0.017552" description="" />
|
||||
<keyValuePair key="vccpint_voltage" value="1.000000" description="" />
|
||||
<keyValuePair key="vccpll_dynamic_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vccpll_static_current" value="0.003000" description="" />
|
||||
<keyValuePair key="vccpll_total_current" value="0.003000" description="" />
|
||||
<keyValuePair key="vccpll_voltage" value="1.800000" description="" />
|
||||
<keyValuePair key="version" value="2018.3" description="" />
|
||||
</section>
|
||||
</section>
|
||||
<section name="report_utilization" level="1" order="8" description="">
|
||||
<section name="clocking" level="2" order="1" description="">
|
||||
<keyValuePair key="bufgctrl_available" value="32" description="" />
|
||||
<keyValuePair key="bufgctrl_fixed" value="0" description="" />
|
||||
<keyValuePair key="bufgctrl_used" value="2" description="" />
|
||||
<keyValuePair key="bufgctrl_util_percentage" value="6.25" description="" />
|
||||
<keyValuePair key="bufgctrl_used" value="3" description="" />
|
||||
<keyValuePair key="bufgctrl_util_percentage" value="9.38" description="" />
|
||||
<keyValuePair key="bufhce_available" value="48" description="" />
|
||||
<keyValuePair key="bufhce_fixed" value="0" description="" />
|
||||
<keyValuePair key="bufhce_used" value="0" description="" />
|
||||
@ -152,62 +359,82 @@
|
||||
<section name="memory" level="2" order="4" description="">
|
||||
<keyValuePair key="block_ram_tile_available" value="60" description="" />
|
||||
<keyValuePair key="block_ram_tile_fixed" value="0" description="" />
|
||||
<keyValuePair key="block_ram_tile_used" value="0" description="" />
|
||||
<keyValuePair key="block_ram_tile_util_percentage" value="0.00" description="" />
|
||||
<keyValuePair key="block_ram_tile_used" value="22.5" description="" />
|
||||
<keyValuePair key="block_ram_tile_util_percentage" value="37.50" description="" />
|
||||
<keyValuePair key="ramb18_available" value="120" description="" />
|
||||
<keyValuePair key="ramb18_fixed" value="0" description="" />
|
||||
<keyValuePair key="ramb18_used" value="0" description="" />
|
||||
<keyValuePair key="ramb18_util_percentage" value="0.00" description="" />
|
||||
<keyValuePair key="ramb18_used" value="9" description="" />
|
||||
<keyValuePair key="ramb18_util_percentage" value="7.50" description="" />
|
||||
<keyValuePair key="ramb18e1_only_used" value="9" description="" />
|
||||
<keyValuePair key="ramb36_fifo_available" value="60" description="" />
|
||||
<keyValuePair key="ramb36_fifo_fixed" value="0" description="" />
|
||||
<keyValuePair key="ramb36_fifo_used" value="0" description="" />
|
||||
<keyValuePair key="ramb36_fifo_util_percentage" value="0.00" description="" />
|
||||
<keyValuePair key="ramb36_fifo_used" value="18" description="" />
|
||||
<keyValuePair key="ramb36_fifo_util_percentage" value="30.00" description="" />
|
||||
<keyValuePair key="ramb36e1_only_used" value="18" description="" />
|
||||
</section>
|
||||
<section name="primitives" level="2" order="5" description="">
|
||||
<keyValuePair key="bufg_functional_category" value="Clock" description="" />
|
||||
<keyValuePair key="bufg_used" value="2" description="" />
|
||||
<keyValuePair key="bufg_used" value="3" description="" />
|
||||
<keyValuePair key="carry4_functional_category" value="CarryLogic" description="" />
|
||||
<keyValuePair key="carry4_used" value="34" description="" />
|
||||
<keyValuePair key="carry4_used" value="266" description="" />
|
||||
<keyValuePair key="fdce_functional_category" value="Flop & Latch" description="" />
|
||||
<keyValuePair key="fdce_used" value="64" description="" />
|
||||
<keyValuePair key="fdpe_functional_category" value="Flop & Latch" description="" />
|
||||
<keyValuePair key="fdpe_used" value="10" description="" />
|
||||
<keyValuePair key="fdre_functional_category" value="Flop & Latch" description="" />
|
||||
<keyValuePair key="fdre_used" value="21" description="" />
|
||||
<keyValuePair key="fdre_used" value="114" description="" />
|
||||
<keyValuePair key="fdse_functional_category" value="Flop & Latch" description="" />
|
||||
<keyValuePair key="fdse_used" value="1" description="" />
|
||||
<keyValuePair key="ibuf_functional_category" value="IO" description="" />
|
||||
<keyValuePair key="ibuf_used" value="1" description="" />
|
||||
<keyValuePair key="ibuf_used" value="2" description="" />
|
||||
<keyValuePair key="ldce_functional_category" value="Flop & Latch" description="" />
|
||||
<keyValuePair key="ldce_used" value="23" description="" />
|
||||
<keyValuePair key="lut1_functional_category" value="LUT" description="" />
|
||||
<keyValuePair key="lut1_used" value="4" description="" />
|
||||
<keyValuePair key="lut1_used" value="12" description="" />
|
||||
<keyValuePair key="lut2_functional_category" value="LUT" description="" />
|
||||
<keyValuePair key="lut2_used" value="28" description="" />
|
||||
<keyValuePair key="lut2_used" value="275" description="" />
|
||||
<keyValuePair key="lut3_functional_category" value="LUT" description="" />
|
||||
<keyValuePair key="lut3_used" value="7" description="" />
|
||||
<keyValuePair key="lut3_used" value="332" description="" />
|
||||
<keyValuePair key="lut4_functional_category" value="LUT" description="" />
|
||||
<keyValuePair key="lut4_used" value="64" description="" />
|
||||
<keyValuePair key="lut4_used" value="365" description="" />
|
||||
<keyValuePair key="lut5_functional_category" value="LUT" description="" />
|
||||
<keyValuePair key="lut5_used" value="47" description="" />
|
||||
<keyValuePair key="lut5_used" value="358" description="" />
|
||||
<keyValuePair key="lut6_functional_category" value="LUT" description="" />
|
||||
<keyValuePair key="lut6_used" value="63" description="" />
|
||||
<keyValuePair key="lut6_used" value="447" description="" />
|
||||
<keyValuePair key="mmcme2_adv_functional_category" value="Clock" description="" />
|
||||
<keyValuePair key="mmcme2_adv_used" value="1" description="" />
|
||||
<keyValuePair key="muxf7_functional_category" value="MuxFx" description="" />
|
||||
<keyValuePair key="muxf7_used" value="19" description="" />
|
||||
<keyValuePair key="muxf8_functional_category" value="MuxFx" description="" />
|
||||
<keyValuePair key="muxf8_used" value="1" description="" />
|
||||
<keyValuePair key="obuf_functional_category" value="IO" description="" />
|
||||
<keyValuePair key="obuf_used" value="18" description="" />
|
||||
<keyValuePair key="obuf_used" value="21" description="" />
|
||||
<keyValuePair key="obuft_functional_category" value="IO" description="" />
|
||||
<keyValuePair key="obuft_used" value="1" description="" />
|
||||
<keyValuePair key="ramb18e1_functional_category" value="Block Memory" description="" />
|
||||
<keyValuePair key="ramb18e1_used" value="9" description="" />
|
||||
<keyValuePair key="ramb36e1_functional_category" value="Block Memory" description="" />
|
||||
<keyValuePair key="ramb36e1_used" value="18" description="" />
|
||||
</section>
|
||||
<section name="slice_logic" level="2" order="6" description="">
|
||||
<keyValuePair key="f7_muxes_available" value="8800" description="" />
|
||||
<keyValuePair key="f7_muxes_fixed" value="0" description="" />
|
||||
<keyValuePair key="f7_muxes_used" value="0" description="" />
|
||||
<keyValuePair key="f7_muxes_util_percentage" value="0.00" description="" />
|
||||
<keyValuePair key="f7_muxes_used" value="19" description="" />
|
||||
<keyValuePair key="f7_muxes_util_percentage" value="0.22" description="" />
|
||||
<keyValuePair key="f8_muxes_available" value="4400" description="" />
|
||||
<keyValuePair key="f8_muxes_fixed" value="0" description="" />
|
||||
<keyValuePair key="f8_muxes_used" value="0" description="" />
|
||||
<keyValuePair key="f8_muxes_util_percentage" value="0.00" description="" />
|
||||
<keyValuePair key="f8_muxes_used" value="1" description="" />
|
||||
<keyValuePair key="f8_muxes_util_percentage" value="0.02" description="" />
|
||||
<keyValuePair key="lut_as_distributed_ram_fixed" value="0" description="" />
|
||||
<keyValuePair key="lut_as_distributed_ram_used" value="0" description="" />
|
||||
<keyValuePair key="lut_as_logic_available" value="17600" description="" />
|
||||
<keyValuePair key="lut_as_logic_available" value="17600" description="" />
|
||||
<keyValuePair key="lut_as_logic_fixed" value="0" description="" />
|
||||
<keyValuePair key="lut_as_logic_fixed" value="0" description="" />
|
||||
<keyValuePair key="lut_as_logic_used" value="168" description="" />
|
||||
<keyValuePair key="lut_as_logic_used" value="168" description="" />
|
||||
<keyValuePair key="lut_as_logic_util_percentage" value="0.95" description="" />
|
||||
<keyValuePair key="lut_as_logic_util_percentage" value="0.95" description="" />
|
||||
<keyValuePair key="lut_as_logic_used" value="1491" description="" />
|
||||
<keyValuePair key="lut_as_logic_used" value="1491" description="" />
|
||||
<keyValuePair key="lut_as_logic_util_percentage" value="8.47" description="" />
|
||||
<keyValuePair key="lut_as_logic_util_percentage" value="8.47" description="" />
|
||||
<keyValuePair key="lut_as_memory_available" value="6000" description="" />
|
||||
<keyValuePair key="lut_as_memory_available" value="6000" description="" />
|
||||
<keyValuePair key="lut_as_memory_fixed" value="0" description="" />
|
||||
@ -219,51 +446,51 @@
|
||||
<keyValuePair key="lut_as_shift_register_fixed" value="0" description="" />
|
||||
<keyValuePair key="lut_as_shift_register_used" value="0" description="" />
|
||||
<keyValuePair key="lut_in_front_of_the_register_is_unused_fixed" value="0" description="" />
|
||||
<keyValuePair key="lut_in_front_of_the_register_is_unused_used" value="0" description="" />
|
||||
<keyValuePair key="lut_in_front_of_the_register_is_used_fixed" value="0" description="" />
|
||||
<keyValuePair key="lut_in_front_of_the_register_is_used_used" value="1" description="" />
|
||||
<keyValuePair key="lut_in_front_of_the_register_is_unused_used" value="21" description="" />
|
||||
<keyValuePair key="lut_in_front_of_the_register_is_used_fixed" value="21" description="" />
|
||||
<keyValuePair key="lut_in_front_of_the_register_is_used_used" value="26" description="" />
|
||||
<keyValuePair key="register_as_flip_flop_available" value="35200" description="" />
|
||||
<keyValuePair key="register_as_flip_flop_fixed" value="0" description="" />
|
||||
<keyValuePair key="register_as_flip_flop_used" value="21" description="" />
|
||||
<keyValuePair key="register_as_flip_flop_util_percentage" value="0.06" description="" />
|
||||
<keyValuePair key="register_as_flip_flop_used" value="189" description="" />
|
||||
<keyValuePair key="register_as_flip_flop_util_percentage" value="0.54" description="" />
|
||||
<keyValuePair key="register_as_latch_available" value="35200" description="" />
|
||||
<keyValuePair key="register_as_latch_fixed" value="0" description="" />
|
||||
<keyValuePair key="register_as_latch_used" value="0" description="" />
|
||||
<keyValuePair key="register_as_latch_util_percentage" value="0.00" description="" />
|
||||
<keyValuePair key="register_driven_from_outside_the_slice_fixed" value="1" description="" />
|
||||
<keyValuePair key="register_driven_from_outside_the_slice_used" value="1" description="" />
|
||||
<keyValuePair key="register_driven_from_within_the_slice_fixed" value="1" description="" />
|
||||
<keyValuePair key="register_driven_from_within_the_slice_used" value="20" description="" />
|
||||
<keyValuePair key="register_as_latch_used" value="23" description="" />
|
||||
<keyValuePair key="register_as_latch_util_percentage" value="0.07" description="" />
|
||||
<keyValuePair key="register_driven_from_outside_the_slice_fixed" value="26" description="" />
|
||||
<keyValuePair key="register_driven_from_outside_the_slice_used" value="47" description="" />
|
||||
<keyValuePair key="register_driven_from_within_the_slice_fixed" value="47" description="" />
|
||||
<keyValuePair key="register_driven_from_within_the_slice_used" value="165" description="" />
|
||||
<keyValuePair key="slice_available" value="4400" description="" />
|
||||
<keyValuePair key="slice_fixed" value="0" description="" />
|
||||
<keyValuePair key="slice_luts_available" value="17600" description="" />
|
||||
<keyValuePair key="slice_luts_fixed" value="0" description="" />
|
||||
<keyValuePair key="slice_luts_used" value="168" description="" />
|
||||
<keyValuePair key="slice_luts_util_percentage" value="0.95" description="" />
|
||||
<keyValuePair key="slice_luts_used" value="1491" description="" />
|
||||
<keyValuePair key="slice_luts_util_percentage" value="8.47" description="" />
|
||||
<keyValuePair key="slice_registers_available" value="35200" description="" />
|
||||
<keyValuePair key="slice_registers_available" value="35200" description="" />
|
||||
<keyValuePair key="slice_registers_fixed" value="0" description="" />
|
||||
<keyValuePair key="slice_registers_fixed" value="0" description="" />
|
||||
<keyValuePair key="slice_registers_used" value="21" description="" />
|
||||
<keyValuePair key="slice_registers_used" value="21" description="" />
|
||||
<keyValuePair key="slice_registers_util_percentage" value="0.06" description="" />
|
||||
<keyValuePair key="slice_registers_util_percentage" value="0.06" description="" />
|
||||
<keyValuePair key="slice_used" value="61" description="" />
|
||||
<keyValuePair key="slice_util_percentage" value="1.39" description="" />
|
||||
<keyValuePair key="slice_registers_used" value="212" description="" />
|
||||
<keyValuePair key="slice_registers_used" value="212" description="" />
|
||||
<keyValuePair key="slice_registers_util_percentage" value="0.60" description="" />
|
||||
<keyValuePair key="slice_registers_util_percentage" value="0.60" description="" />
|
||||
<keyValuePair key="slice_used" value="541" description="" />
|
||||
<keyValuePair key="slice_util_percentage" value="12.30" description="" />
|
||||
<keyValuePair key="slicel_fixed" value="0" description="" />
|
||||
<keyValuePair key="slicel_used" value="45" description="" />
|
||||
<keyValuePair key="slicel_used" value="361" description="" />
|
||||
<keyValuePair key="slicem_fixed" value="0" description="" />
|
||||
<keyValuePair key="slicem_used" value="16" description="" />
|
||||
<keyValuePair key="slicem_used" value="180" description="" />
|
||||
<keyValuePair key="unique_control_sets_available" value="4400" description="" />
|
||||
<keyValuePair key="unique_control_sets_fixed" value="4400" description="" />
|
||||
<keyValuePair key="unique_control_sets_used" value="2" description="" />
|
||||
<keyValuePair key="unique_control_sets_util_percentage" value="0.05" description="" />
|
||||
<keyValuePair key="using_o5_and_o6_fixed" value="0.05" description="" />
|
||||
<keyValuePair key="using_o5_and_o6_used" value="45" description="" />
|
||||
<keyValuePair key="using_o5_output_only_fixed" value="45" description="" />
|
||||
<keyValuePair key="unique_control_sets_used" value="31" description="" />
|
||||
<keyValuePair key="unique_control_sets_util_percentage" value="0.70" description="" />
|
||||
<keyValuePair key="using_o5_and_o6_fixed" value="0.70" description="" />
|
||||
<keyValuePair key="using_o5_and_o6_used" value="298" description="" />
|
||||
<keyValuePair key="using_o5_output_only_fixed" value="298" description="" />
|
||||
<keyValuePair key="using_o5_output_only_used" value="0" description="" />
|
||||
<keyValuePair key="using_o6_output_only_fixed" value="0" description="" />
|
||||
<keyValuePair key="using_o6_output_only_used" value="123" description="" />
|
||||
<keyValuePair key="using_o6_output_only_used" value="1193" description="" />
|
||||
</section>
|
||||
<section name="specific_feature" level="2" order="7" description="">
|
||||
<keyValuePair key="bscane2_available" value="4" description="" />
|
||||
@ -300,7 +527,7 @@
|
||||
<keyValuePair key="xadc_util_percentage" value="0.00" description="" />
|
||||
</section>
|
||||
</section>
|
||||
<section name="synthesis" level="1" order="6" description="">
|
||||
<section name="synthesis" level="1" order="9" description="">
|
||||
<section name="command_line_options" level="2" order="1" description="">
|
||||
<keyValuePair key="-assert" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-bufg" value="default::12" description="" />
|
||||
@ -338,144 +565,183 @@
|
||||
<keyValuePair key="-verilog_define" value="default::[not_specified]" description="" />
|
||||
</section>
|
||||
<section name="usage" level="2" order="2" description="">
|
||||
<keyValuePair key="elapsed" value="00:01:36s" description="" />
|
||||
<keyValuePair key="elapsed" value="00:00:46s" description="" />
|
||||
<keyValuePair key="hls_ip" value="0" description="" />
|
||||
<keyValuePair key="memory_gain" value="948.426MB" description="" />
|
||||
<keyValuePair key="memory_peak" value="1310.512MB" description="" />
|
||||
<keyValuePair key="memory_gain" value="613.590MB" description="" />
|
||||
<keyValuePair key="memory_peak" value="976.145MB" description="" />
|
||||
</section>
|
||||
</section>
|
||||
<section name="unisim_transformation" level="1" order="7" description="">
|
||||
<section name="unisim_transformation" level="1" order="10" description="">
|
||||
<section name="post_unisim_transformation" level="2" order="1" description="">
|
||||
<keyValuePair key="bufg" value="2" description="" />
|
||||
<keyValuePair key="carry4" value="34" description="" />
|
||||
<keyValuePair key="fdre" value="21" description="" />
|
||||
<keyValuePair key="gnd" value="2" description="" />
|
||||
<keyValuePair key="ibuf" value="1" description="" />
|
||||
<keyValuePair key="lut1" value="4" description="" />
|
||||
<keyValuePair key="lut2" value="28" description="" />
|
||||
<keyValuePair key="lut3" value="7" description="" />
|
||||
<keyValuePair key="lut4" value="62" description="" />
|
||||
<keyValuePair key="lut5" value="47" description="" />
|
||||
<keyValuePair key="lut6" value="65" description="" />
|
||||
<keyValuePair key="carry4" value="266" description="" />
|
||||
<keyValuePair key="fdce" value="62" description="" />
|
||||
<keyValuePair key="fdpe" value="10" description="" />
|
||||
<keyValuePair key="fdre" value="114" description="" />
|
||||
<keyValuePair key="fdse" value="1" description="" />
|
||||
<keyValuePair key="gnd" value="11" description="" />
|
||||
<keyValuePair key="ibuf" value="2" description="" />
|
||||
<keyValuePair key="ldce" value="23" description="" />
|
||||
<keyValuePair key="lut1" value="12" description="" />
|
||||
<keyValuePair key="lut2" value="275" description="" />
|
||||
<keyValuePair key="lut3" value="323" description="" />
|
||||
<keyValuePair key="lut4" value="365" description="" />
|
||||
<keyValuePair key="lut5" value="358" description="" />
|
||||
<keyValuePair key="lut6" value="447" description="" />
|
||||
<keyValuePair key="mmcme2_adv" value="1" description="" />
|
||||
<keyValuePair key="obuf" value="18" description="" />
|
||||
<keyValuePair key="vcc" value="2" description="" />
|
||||
<keyValuePair key="muxf7" value="19" description="" />
|
||||
<keyValuePair key="muxf8" value="1" description="" />
|
||||
<keyValuePair key="obuf" value="21" description="" />
|
||||
<keyValuePair key="obuft" value="1" description="" />
|
||||
<keyValuePair key="ramb18e1" value="9" description="" />
|
||||
<keyValuePair key="ramb36e1" value="18" description="" />
|
||||
<keyValuePair key="vcc" value="11" description="" />
|
||||
</section>
|
||||
<section name="pre_unisim_transformation" level="2" order="2" description="">
|
||||
<keyValuePair key="bufg" value="2" description="" />
|
||||
<keyValuePair key="carry4" value="34" description="" />
|
||||
<keyValuePair key="fdre" value="21" description="" />
|
||||
<keyValuePair key="gnd" value="2" description="" />
|
||||
<keyValuePair key="ibuf" value="1" description="" />
|
||||
<keyValuePair key="lut1" value="4" description="" />
|
||||
<keyValuePair key="lut2" value="28" description="" />
|
||||
<keyValuePair key="lut3" value="7" description="" />
|
||||
<keyValuePair key="lut4" value="62" description="" />
|
||||
<keyValuePair key="lut5" value="47" description="" />
|
||||
<keyValuePair key="lut6" value="65" description="" />
|
||||
<keyValuePair key="carry4" value="266" description="" />
|
||||
<keyValuePair key="fdce" value="62" description="" />
|
||||
<keyValuePair key="fdpe" value="10" description="" />
|
||||
<keyValuePair key="fdre" value="114" description="" />
|
||||
<keyValuePair key="fdse" value="1" description="" />
|
||||
<keyValuePair key="gnd" value="11" description="" />
|
||||
<keyValuePair key="ibuf" value="3" description="" />
|
||||
<keyValuePair key="ldce" value="23" description="" />
|
||||
<keyValuePair key="lut1" value="12" description="" />
|
||||
<keyValuePair key="lut2" value="275" description="" />
|
||||
<keyValuePair key="lut3" value="323" description="" />
|
||||
<keyValuePair key="lut4" value="365" description="" />
|
||||
<keyValuePair key="lut5" value="358" description="" />
|
||||
<keyValuePair key="lut6" value="447" description="" />
|
||||
<keyValuePair key="mmcme2_adv" value="1" description="" />
|
||||
<keyValuePair key="obuf" value="18" description="" />
|
||||
<keyValuePair key="vcc" value="2" description="" />
|
||||
<keyValuePair key="muxf7" value="19" description="" />
|
||||
<keyValuePair key="muxf8" value="1" description="" />
|
||||
<keyValuePair key="obuf" value="21" description="" />
|
||||
<keyValuePair key="obuft" value="1" description="" />
|
||||
<keyValuePair key="ramb18e1" value="9" description="" />
|
||||
<keyValuePair key="ramb36e1" value="18" description="" />
|
||||
<keyValuePair key="vcc" value="11" description="" />
|
||||
</section>
|
||||
</section>
|
||||
<section name="vivado_usage" level="1" order="8" description="">
|
||||
<section name="vivado_usage" level="1" order="11" description="">
|
||||
<section name="gui_handlers" level="2" order="1" description="">
|
||||
<keyValuePair key="abstractcombinedpanel_add_element" value="9" description="" />
|
||||
<keyValuePair key="abstractcombinedpanel_remove_selected_elements" value="2" description="" />
|
||||
<keyValuePair key="abstractfileview_close" value="1" description="" />
|
||||
<keyValuePair key="basedialog_cancel" value="45" description="" />
|
||||
<keyValuePair key="abstractfileview_reload" value="2" description="" />
|
||||
<keyValuePair key="addsrcwizard_specify_or_create_constraint_files" value="1" description="" />
|
||||
<keyValuePair key="basedialog_cancel" value="59" description="" />
|
||||
<keyValuePair key="basedialog_close" value="1" description="" />
|
||||
<keyValuePair key="basedialog_no" value="1" description="" />
|
||||
<keyValuePair key="basedialog_ok" value="396" description="" />
|
||||
<keyValuePair key="basedialog_yes" value="2" description="" />
|
||||
<keyValuePair key="constraintschooserpanel_add_files" value="1" description="" />
|
||||
<keyValuePair key="coretreetablepanel_core_tree_table" value="18" description="" />
|
||||
<keyValuePair key="basedialog_no" value="3" description="" />
|
||||
<keyValuePair key="basedialog_ok" value="474" description="" />
|
||||
<keyValuePair key="basedialog_yes" value="4" description="" />
|
||||
<keyValuePair key="cmdmsgdialog_ok" value="2" description="" />
|
||||
<keyValuePair key="confirmsavetexteditsdialog_no" value="1" description="" />
|
||||
<keyValuePair key="constraintschooserpanel_add_files" value="2" description="" />
|
||||
<keyValuePair key="coretreetablepanel_core_tree_table" value="24" description="" />
|
||||
<keyValuePair key="createnewdiagramdialog_design_name" value="1" description="" />
|
||||
<keyValuePair key="createsrcfiledialog_file_name" value="5" description="" />
|
||||
<keyValuePair key="definemodulesdialog_define_modules_and_specify_io_ports" value="95" description="" />
|
||||
<keyValuePair key="filesetpanel_file_set_panel_tree" value="157" description="" />
|
||||
<keyValuePair key="flownavigatortreepanel_flow_navigator_tree" value="206" description="" />
|
||||
<keyValuePair key="filesetpanel_file_set_panel_tree" value="209" description="" />
|
||||
<keyValuePair key="flownavigatortreepanel_flow_navigator_tree" value="261" description="" />
|
||||
<keyValuePair key="fpgachooser_fpga_table" value="1" description="" />
|
||||
<keyValuePair key="gettingstartedview_create_new_project" value="1" description="" />
|
||||
<keyValuePair key="gettingstartedview_create_new_project" value="2" description="" />
|
||||
<keyValuePair key="gettingstartedview_open_project" value="1" description="" />
|
||||
<keyValuePair key="hcodeeditor_blank_operations" value="17" description="" />
|
||||
<keyValuePair key="hcodeeditor_close" value="1" description="" />
|
||||
<keyValuePair key="hcodeeditor_close" value="3" description="" />
|
||||
<keyValuePair key="hcodeeditor_commands_to_fold_text" value="2" description="" />
|
||||
<keyValuePair key="hcodeeditor_diff_with" value="8" description="" />
|
||||
<keyValuePair key="hcodeeditor_search_text_combo_box" value="15" description="" />
|
||||
<keyValuePair key="hcodeeditor_search_text_combo_box" value="20" description="" />
|
||||
<keyValuePair key="hinputhandler_indent_selection" value="1" description="" />
|
||||
<keyValuePair key="hinputhandler_toggle_line_comments" value="37" description="" />
|
||||
<keyValuePair key="hinputhandler_toggle_line_comments" value="40" description="" />
|
||||
<keyValuePair key="hinputhandler_unindent_selection" value="2" description="" />
|
||||
<keyValuePair key="hpopuptitle_close" value="1" description="" />
|
||||
<keyValuePair key="logmonitor_monitor" value="3" description="" />
|
||||
<keyValuePair key="msgtreepanel_manage_suppression" value="1" description="" />
|
||||
<keyValuePair key="msgtreepanel_message_view_tree" value="79" description="" />
|
||||
<keyValuePair key="msgview_clear_messages_resulting_from_user_executed" value="1" description="" />
|
||||
<keyValuePair key="msgtreepanel_message_view_tree" value="137" description="" />
|
||||
<keyValuePair key="msgview_clear_messages_resulting_from_user_executed" value="4" description="" />
|
||||
<keyValuePair key="msgview_critical_warnings" value="2" description="" />
|
||||
<keyValuePair key="msgview_error_messages" value="4" description="" />
|
||||
<keyValuePair key="msgview_information_messages" value="3" description="" />
|
||||
<keyValuePair key="msgview_warning_messages" value="9" description="" />
|
||||
<keyValuePair key="numjobschooser_number_of_jobs" value="2" description="" />
|
||||
<keyValuePair key="pacommandnames_auto_connect_target" value="16" description="" />
|
||||
<keyValuePair key="pacommandnames_auto_update_hier" value="11" description="" />
|
||||
<keyValuePair key="pacommandnames_goto_implemented_design" value="1" description="" />
|
||||
<keyValuePair key="msgview_warning_messages" value="11" description="" />
|
||||
<keyValuePair key="netlisttreeview_netlist_tree" value="4" description="" />
|
||||
<keyValuePair key="numjobschooser_number_of_jobs" value="3" description="" />
|
||||
<keyValuePair key="pacommandnames_auto_connect_target" value="18" description="" />
|
||||
<keyValuePair key="pacommandnames_auto_update_hier" value="15" description="" />
|
||||
<keyValuePair key="pacommandnames_goto_implemented_design" value="2" description="" />
|
||||
<keyValuePair key="pacommandnames_goto_netlist_design" value="1" description="" />
|
||||
<keyValuePair key="pacommandnames_log_window" value="1" description="" />
|
||||
<keyValuePair key="pacommandnames_message_window" value="2" description="" />
|
||||
<keyValuePair key="pacommandnames_open_hardware_manager" value="2" description="" />
|
||||
<keyValuePair key="pacommandnames_recustomize_core" value="1" description="" />
|
||||
<keyValuePair key="pacommandnames_run_bitgen" value="42" description="" />
|
||||
<keyValuePair key="pacommandnames_run_bitgen" value="45" description="" />
|
||||
<keyValuePair key="pacommandnames_run_implementation" value="8" description="" />
|
||||
<keyValuePair key="paviews_code" value="5" description="" />
|
||||
<keyValuePair key="pacommandnames_src_disable" value="1" description="" />
|
||||
<keyValuePair key="paviews_code" value="7" description="" />
|
||||
<keyValuePair key="paviews_device" value="3" description="" />
|
||||
<keyValuePair key="paviews_ip_catalog" value="1" description="" />
|
||||
<keyValuePair key="paviews_project_summary" value="21" description="" />
|
||||
<keyValuePair key="paviews_schematic" value="9" description="" />
|
||||
<keyValuePair key="programdebugtab_refresh_device" value="1" description="" />
|
||||
<keyValuePair key="programfpgadialog_program" value="45" description="" />
|
||||
<keyValuePair key="progressdialog_background" value="4" description="" />
|
||||
<keyValuePair key="paviews_ip_catalog" value="2" description="" />
|
||||
<keyValuePair key="paviews_project_summary" value="26" description="" />
|
||||
<keyValuePair key="paviews_schematic" value="10" description="" />
|
||||
<keyValuePair key="programdebugtab_program_device" value="1" description="" />
|
||||
<keyValuePair key="programdebugtab_refresh_device" value="2" description="" />
|
||||
<keyValuePair key="programfpgadialog_program" value="51" description="" />
|
||||
<keyValuePair key="progressdialog_background" value="5" description="" />
|
||||
<keyValuePair key="progressdialog_cancel" value="5" description="" />
|
||||
<keyValuePair key="projectnamechooser_project_name" value="1" description="" />
|
||||
<keyValuePair key="projecttab_reload" value="6" description="" />
|
||||
<keyValuePair key="rdicommands_delete" value="4" description="" />
|
||||
<keyValuePair key="projecttab_reload" value="9" description="" />
|
||||
<keyValuePair key="rdicommands_copy" value="1" description="" />
|
||||
<keyValuePair key="rdicommands_delete" value="8" description="" />
|
||||
<keyValuePair key="removesourcesdialog_also_delete" value="2" description="" />
|
||||
<keyValuePair key="rungadget_show_warning_and_error_messages_in_messages" value="2" description="" />
|
||||
<keyValuePair key="saveprojectutils_dont_save" value="8" description="" />
|
||||
<keyValuePair key="saveprojectutils_save" value="5" description="" />
|
||||
<keyValuePair key="saveprojectutils_save" value="6" description="" />
|
||||
<keyValuePair key="schematicview_previous" value="10" description="" />
|
||||
<keyValuePair key="simpleoutputproductdialog_generate_output_products_immediately" value="3" description="" />
|
||||
<keyValuePair key="srcchooserpanel_add_hdl_and_netlist_files_to_your_project" value="1" description="" />
|
||||
<keyValuePair key="simpleoutputproductdialog_generate_output_products_immediately" value="4" description="" />
|
||||
<keyValuePair key="specifylibrarydialog_library_name" value="1" description="" />
|
||||
<keyValuePair key="srcchooserpanel_add_directories" value="2" description="" />
|
||||
<keyValuePair key="srcchooserpanel_add_hdl_and_netlist_files_to_your_project" value="3" description="" />
|
||||
<keyValuePair key="srcchooserpanel_add_or_create_source_file" value="1" description="" />
|
||||
<keyValuePair key="srcchooserpanel_create_file" value="6" description="" />
|
||||
<keyValuePair key="srcmenu_ip_documentation" value="5" description="" />
|
||||
<keyValuePair key="srcmenu_ip_hierarchy" value="8" description="" />
|
||||
<keyValuePair key="srcfileproppanels_type" value="4" description="" />
|
||||
<keyValuePair key="srcfiletypecombobox_source_file_type" value="4" description="" />
|
||||
<keyValuePair key="srcmenu_ip_documentation" value="6" description="" />
|
||||
<keyValuePair key="srcmenu_ip_hierarchy" value="10" description="" />
|
||||
<keyValuePair key="srcmenu_set_library" value="1" description="" />
|
||||
<keyValuePair key="stalerundialog_no" value="1" description="" />
|
||||
<keyValuePair key="syntheticagettingstartedview_recent_projects" value="4" description="" />
|
||||
<keyValuePair key="syntheticastatemonitor_cancel" value="5" description="" />
|
||||
<keyValuePair key="taskbanner_close" value="16" description="" />
|
||||
<keyValuePair key="syntheticastatemonitor_cancel" value="7" description="" />
|
||||
<keyValuePair key="taskbanner_close" value="19" description="" />
|
||||
</section>
|
||||
<section name="java_command_handlers" level="2" order="2" description="">
|
||||
<keyValuePair key="addsources" value="6" description="" />
|
||||
<keyValuePair key="autoconnecttarget" value="16" description="" />
|
||||
<keyValuePair key="coreview" value="3" description="" />
|
||||
<keyValuePair key="customizecore" value="4" description="" />
|
||||
<keyValuePair key="editdelete" value="4" description="" />
|
||||
<keyValuePair key="editpaste" value="2" description="" />
|
||||
<keyValuePair key="addsources" value="11" description="" />
|
||||
<keyValuePair key="autoconnecttarget" value="18" description="" />
|
||||
<keyValuePair key="coreview" value="4" description="" />
|
||||
<keyValuePair key="createblockdesign" value="3" description="" />
|
||||
<keyValuePair key="customizecore" value="5" description="" />
|
||||
<keyValuePair key="editdelete" value="9" description="" />
|
||||
<keyValuePair key="editpaste" value="3" description="" />
|
||||
<keyValuePair key="editundo" value="1" description="" />
|
||||
<keyValuePair key="launchprogramfpga" value="45" description="" />
|
||||
<keyValuePair key="newproject" value="1" description="" />
|
||||
<keyValuePair key="openhardwaremanager" value="67" description="" />
|
||||
<keyValuePair key="openrecenttarget" value="21" description="" />
|
||||
<keyValuePair key="programdevice" value="45" description="" />
|
||||
<keyValuePair key="fliptoviewtaskrtlanalysis" value="1" description="" />
|
||||
<keyValuePair key="launchprogramfpga" value="51" description="" />
|
||||
<keyValuePair key="newproject" value="2" description="" />
|
||||
<keyValuePair key="openhardwaremanager" value="74" description="" />
|
||||
<keyValuePair key="openproject" value="1" description="" />
|
||||
<keyValuePair key="openrecenttarget" value="24" description="" />
|
||||
<keyValuePair key="programdevice" value="50" description="" />
|
||||
<keyValuePair key="recustomizecore" value="3" description="" />
|
||||
<keyValuePair key="runbitgen" value="45" description="" />
|
||||
<keyValuePair key="runimplementation" value="59" description="" />
|
||||
<keyValuePair key="runbitgen" value="54" description="" />
|
||||
<keyValuePair key="runimplementation" value="68" description="" />
|
||||
<keyValuePair key="runschematic" value="7" description="" />
|
||||
<keyValuePair key="runsynthesis" value="92" description="" />
|
||||
<keyValuePair key="runsynthesis" value="114" description="" />
|
||||
<keyValuePair key="savefileproxyhandler" value="3" description="" />
|
||||
<keyValuePair key="showview" value="24" description="" />
|
||||
<keyValuePair key="setsourceenabled" value="1" description="" />
|
||||
<keyValuePair key="showview" value="35" description="" />
|
||||
<keyValuePair key="viewtaskimplementation" value="8" description="" />
|
||||
<keyValuePair key="viewtaskrtlanalysis" value="3" description="" />
|
||||
<keyValuePair key="viewtaskrtlanalysis" value="7" description="" />
|
||||
<keyValuePair key="viewtasksynthesis" value="2" description="" />
|
||||
</section>
|
||||
<section name="other_data" level="2" order="3" description="">
|
||||
<keyValuePair key="guimode" value="5" description="" />
|
||||
<keyValuePair key="guimode" value="6" description="" />
|
||||
</section>
|
||||
<section name="project_data" level="2" order="4" description="">
|
||||
<keyValuePair key="constraintsetcount" value="1" description="" />
|
||||
@ -500,7 +766,7 @@
|
||||
<keyValuePair key="launch_simulation_vcs" value="0" description="" />
|
||||
<keyValuePair key="launch_simulation_xsim" value="0" description="" />
|
||||
<keyValuePair key="simulator_language" value="VHDL" description="" />
|
||||
<keyValuePair key="srcsetcount" value="8" description="" />
|
||||
<keyValuePair key="srcsetcount" value="13" description="" />
|
||||
<keyValuePair key="synthesisstrategy" value="Vivado Synthesis Defaults" description="" />
|
||||
<keyValuePair key="target_language" value="VHDL" description="" />
|
||||
<keyValuePair key="target_simulator" value="XSim" description="" />
|
||||
|
||||
@ -2,11 +2,11 @@
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Tue Dec 7 12:44:06 2021
|
||||
# Process ID: 5252
|
||||
# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1
|
||||
# Start of session at: Tue Jan 4 12:18:37 2022
|
||||
# Process ID: 13232
|
||||
# Current directory: C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1
|
||||
# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace
|
||||
# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi
|
||||
# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou
|
||||
# Log file: C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1/VGA_top.vdi
|
||||
# Journal file: C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source VGA_top.tcl -notrace
|
||||
|
||||
Binary file not shown.
@ -1,12 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Tue Nov 23 09:55:17 2021
|
||||
# Process ID: 11872
|
||||
# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1
|
||||
# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace
|
||||
# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi
|
||||
# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source VGA_top.tcl -notrace
|
||||
@ -1,12 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Tue Nov 30 12:02:04 2021
|
||||
# Process ID: 12280
|
||||
# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1
|
||||
# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace
|
||||
# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi
|
||||
# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source VGA_top.tcl -notrace
|
||||
@ -1,12 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Tue Dec 7 12:19:39 2021
|
||||
# Process ID: 12864
|
||||
# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1
|
||||
# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace
|
||||
# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi
|
||||
# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source VGA_top.tcl -notrace
|
||||
@ -1,12 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Tue Nov 30 12:20:41 2021
|
||||
# Process ID: 12968
|
||||
# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1
|
||||
# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace
|
||||
# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi
|
||||
# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source VGA_top.tcl -notrace
|
||||
@ -1,12 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Tue Nov 30 12:26:23 2021
|
||||
# Process ID: 13936
|
||||
# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1
|
||||
# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace
|
||||
# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi
|
||||
# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source VGA_top.tcl -notrace
|
||||
@ -1,12 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Tue Nov 23 10:29:07 2021
|
||||
# Process ID: 14844
|
||||
# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1
|
||||
# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace
|
||||
# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi
|
||||
# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source VGA_top.tcl -notrace
|
||||
@ -1,12 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Tue Nov 30 12:16:55 2021
|
||||
# Process ID: 15112
|
||||
# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1
|
||||
# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace
|
||||
# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi
|
||||
# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source VGA_top.tcl -notrace
|
||||
@ -1,12 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Tue Nov 30 12:43:37 2021
|
||||
# Process ID: 1568
|
||||
# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1
|
||||
# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace
|
||||
# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi
|
||||
# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source VGA_top.tcl -notrace
|
||||
@ -1,12 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Tue Nov 23 10:08:25 2021
|
||||
# Process ID: 4688
|
||||
# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1
|
||||
# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace
|
||||
# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi
|
||||
# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source VGA_top.tcl -notrace
|
||||
@ -1,12 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Tue Dec 7 12:30:30 2021
|
||||
# Process ID: 4708
|
||||
# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1
|
||||
# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace
|
||||
# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi
|
||||
# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source VGA_top.tcl -notrace
|
||||
@ -1,12 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Tue Dec 7 12:42:58 2021
|
||||
# Process ID: 4856
|
||||
# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1
|
||||
# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace
|
||||
# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi
|
||||
# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source VGA_top.tcl -notrace
|
||||
@ -1,12 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Tue Dec 7 12:35:58 2021
|
||||
# Process ID: 6484
|
||||
# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1
|
||||
# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace
|
||||
# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi
|
||||
# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source VGA_top.tcl -notrace
|
||||
@ -1,12 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Tue Nov 23 10:20:49 2021
|
||||
# Process ID: 8972
|
||||
# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1
|
||||
# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace
|
||||
# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi
|
||||
# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source VGA_top.tcl -notrace
|
||||
@ -1,12 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Tue Dec 7 12:26:40 2021
|
||||
# Process ID: 9384
|
||||
# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1
|
||||
# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace
|
||||
# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi
|
||||
# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source VGA_top.tcl -notrace
|
||||
@ -1,12 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Tue Nov 23 10:14:24 2021
|
||||
# Process ID: 9960
|
||||
# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1
|
||||
# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace
|
||||
# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi
|
||||
# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source VGA_top.tcl -notrace
|
||||
Binary file not shown.
@ -1,49 +1,49 @@
|
||||
set_property SRC_FILE_INFO {cfile:{C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc} rfile:{../../../../../../../../../e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc} id:1} [current_design]
|
||||
set_property SRC_FILE_INFO {cfile:C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/ZYBO_Master.xdc rfile:../../../sources_snake/ZYBO_Master.xdc id:1} [current_design]
|
||||
set_property src_info {type:XDC file:1 line:8 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN L16 [get_ports H125MHz]
|
||||
set_property src_info {type:XDC file:1 line:17 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property src_info {type:XDC file:1 line:14 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN G15 [get_ports resetGeneral]
|
||||
set_property src_info {type:XDC file:1 line:34 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN R18 [get_ports bouton_up]
|
||||
set_property src_info {type:XDC file:1 line:38 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN P16 [get_ports bouton_down]
|
||||
set_property src_info {type:XDC file:1 line:42 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN V16 [get_ports bouton_left]
|
||||
set_property src_info {type:XDC file:1 line:46 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN Y16 [get_ports bouton_right]
|
||||
set_property src_info {type:XDC file:1 line:341 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property src_info {type:XDC file:1 line:48 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN M14 [get_ports {led[0]}]
|
||||
set_property src_info {type:XDC file:1 line:52 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN M15 [get_ports {led[1]}]
|
||||
set_property src_info {type:XDC file:1 line:56 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN G14 [get_ports {led[2]}]
|
||||
set_property src_info {type:XDC file:1 line:60 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN D18 [get_ports {led[3]}]
|
||||
set_property src_info {type:XDC file:1 line:337 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN M19 [get_ports {vga_r[0]}]
|
||||
set_property src_info {type:XDC file:1 line:345 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property src_info {type:XDC file:1 line:341 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN L20 [get_ports {vga_r[1]}]
|
||||
set_property src_info {type:XDC file:1 line:349 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property src_info {type:XDC file:1 line:345 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN J20 [get_ports {vga_r[2]}]
|
||||
set_property src_info {type:XDC file:1 line:353 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property src_info {type:XDC file:1 line:349 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN G20 [get_ports {vga_r[3]}]
|
||||
set_property src_info {type:XDC file:1 line:357 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property src_info {type:XDC file:1 line:353 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN F19 [get_ports {vga_r[4]}]
|
||||
set_property src_info {type:XDC file:1 line:361 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property src_info {type:XDC file:1 line:357 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN H18 [get_ports {vga_g[0]}]
|
||||
set_property src_info {type:XDC file:1 line:365 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property src_info {type:XDC file:1 line:361 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN N20 [get_ports {vga_g[1]}]
|
||||
set_property src_info {type:XDC file:1 line:369 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property src_info {type:XDC file:1 line:365 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN L19 [get_ports {vga_g[2]}]
|
||||
set_property src_info {type:XDC file:1 line:373 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property src_info {type:XDC file:1 line:369 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN J19 [get_ports {vga_g[3]}]
|
||||
set_property src_info {type:XDC file:1 line:377 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property src_info {type:XDC file:1 line:373 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN H20 [get_ports {vga_g[4]}]
|
||||
set_property src_info {type:XDC file:1 line:381 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property src_info {type:XDC file:1 line:377 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN F20 [get_ports {vga_g[5]}]
|
||||
set_property src_info {type:XDC file:1 line:385 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property src_info {type:XDC file:1 line:381 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN P20 [get_ports {vga_b[0]}]
|
||||
set_property src_info {type:XDC file:1 line:389 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property src_info {type:XDC file:1 line:385 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN M20 [get_ports {vga_b[1]}]
|
||||
set_property src_info {type:XDC file:1 line:393 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property src_info {type:XDC file:1 line:389 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN K19 [get_ports {vga_b[2]}]
|
||||
set_property src_info {type:XDC file:1 line:397 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property src_info {type:XDC file:1 line:393 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN J18 [get_ports {vga_b[3]}]
|
||||
set_property src_info {type:XDC file:1 line:401 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property src_info {type:XDC file:1 line:397 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN G19 [get_ports {vga_b[4]}]
|
||||
set_property src_info {type:XDC file:1 line:405 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property src_info {type:XDC file:1 line:401 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN P19 [get_ports vga_hs]
|
||||
set_property src_info {type:XDC file:1 line:409 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property src_info {type:XDC file:1 line:405 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN R19 [get_ports vga_vs]
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado.bat" Owner="E209098F" Host="irb121-02-w" Pid="10912">
|
||||
<Process Command="vivado.bat" Owner="e209098F" Host="irb121-12-w" Pid="12220">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
|
||||
Binary file not shown.
@ -17,9 +17,7 @@ proc create_report { reportName command } {
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
set_param synth.incrementalSynthesisCache C:/Users/E209098F/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-12508-irb121-02-w/incrSyn
|
||||
set_param xicom.use_bs_reader 1
|
||||
set_msg_config -id {Common 17-41} -limit 10000000
|
||||
set_msg_config -id {Synth 8-256} -limit 10000
|
||||
set_msg_config -id {Synth 8-638} -limit 10000
|
||||
create_project -in_memory -part xc7z010clg400-1
|
||||
@ -28,25 +26,32 @@ set_param project.singleFileAddWarning.threshold 0
|
||||
set_param project.compositeFile.enableAutoGeneration 0
|
||||
set_param synth.vivado.isSynthRun true
|
||||
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
|
||||
set_property webtalk.parent_dir C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.cache/wt [current_project]
|
||||
set_property parent.project_path C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.xpr [current_project]
|
||||
set_property webtalk.parent_dir C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.cache/wt [current_project]
|
||||
set_property parent.project_path C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.xpr [current_project]
|
||||
set_property XPM_LIBRARIES XPM_CDC [current_project]
|
||||
set_property default_lib xil_defaultlib [current_project]
|
||||
set_property target_language VHDL [current_project]
|
||||
set_property ip_output_repo c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.cache/ip [current_project]
|
||||
set_property ip_output_repo c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
read_mem C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sprites/sprites.mem
|
||||
read_vhdl -library xil_defaultlib {
|
||||
C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Diviseur.vhd
|
||||
{C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/GeneRGB_V1.vhd}
|
||||
{C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/GeneSync.vhd}
|
||||
C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Position.vhd
|
||||
C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd
|
||||
{C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/VGA_top.vhd}
|
||||
C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Diviseur.vhd
|
||||
C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/GeneRGB_V1.vhd
|
||||
C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/GeneSync.vhd
|
||||
C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd
|
||||
C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd
|
||||
C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/VGA_top.vhd
|
||||
}
|
||||
read_ip -quiet C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xci
|
||||
set_property used_in_implementation false [get_files -all c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc]
|
||||
set_property used_in_implementation false [get_files -all c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc]
|
||||
set_property used_in_implementation false [get_files -all c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_ooc.xdc]
|
||||
read_vhdl -library ourTypes C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/types.vhd
|
||||
read_vhdl -vhdl2008 -library xil_defaultlib {
|
||||
C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/RAMController.vhd
|
||||
C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/snakeRam.vhd
|
||||
C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/spritesRom.vhd
|
||||
}
|
||||
read_ip -quiet c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0.xci
|
||||
set_property used_in_implementation false [get_files -all c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0_board.xdc]
|
||||
set_property used_in_implementation false [get_files -all c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0.xdc]
|
||||
set_property used_in_implementation false [get_files -all c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0_ooc.xdc]
|
||||
|
||||
# Mark all dcp files as not used in implementation to prevent them from being
|
||||
# stitched into the results of this synthesis run. Any black boxes in the
|
||||
@ -56,8 +61,8 @@ set_property used_in_implementation false [get_files -all c:/Users/e209098F/Docu
|
||||
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
|
||||
set_property used_in_implementation false $dcp
|
||||
}
|
||||
read_xdc {{C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc}}
|
||||
set_property used_in_implementation false [get_files {{C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc}}]
|
||||
read_xdc C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/ZYBO_Master.xdc
|
||||
set_property used_in_implementation false [get_files C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/ZYBO_Master.xdc]
|
||||
|
||||
read_xdc dont_touch.xdc
|
||||
set_property used_in_implementation false [get_files dont_touch.xdc]
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Binary file not shown.
@ -1,8 +1,8 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
|
||||
| Date : Tue Dec 7 12:42:42 2021
|
||||
| Host : irb121-02-w running 64-bit major release (build 9200)
|
||||
| Date : Tue Jan 4 12:18:30 2022
|
||||
| Host : irb121-12-w running 64-bit major release (build 9200)
|
||||
| Command : report_utilization -file VGA_top_utilization_synth.rpt -pb VGA_top_utilization_synth.pb
|
||||
| Design : VGA_top
|
||||
| Device : 7z010clg400-1
|
||||
@ -30,14 +30,14 @@ Table of Contents
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Slice LUTs* | 170 | 0 | 17600 | 0.97 |
|
||||
| LUT as Logic | 170 | 0 | 17600 | 0.97 |
|
||||
| Slice LUTs* | 1481 | 0 | 17600 | 8.41 |
|
||||
| LUT as Logic | 1481 | 0 | 17600 | 8.41 |
|
||||
| LUT as Memory | 0 | 0 | 6000 | 0.00 |
|
||||
| Slice Registers | 21 | 0 | 35200 | 0.06 |
|
||||
| Register as Flip Flop | 21 | 0 | 35200 | 0.06 |
|
||||
| Register as Latch | 0 | 0 | 35200 | 0.00 |
|
||||
| F7 Muxes | 0 | 0 | 8800 | 0.00 |
|
||||
| F8 Muxes | 0 | 0 | 4400 | 0.00 |
|
||||
| Slice Registers | 210 | 0 | 35200 | 0.60 |
|
||||
| Register as Flip Flop | 187 | 0 | 35200 | 0.53 |
|
||||
| Register as Latch | 23 | 0 | 35200 | 0.07 |
|
||||
| F7 Muxes | 19 | 0 | 8800 | 0.22 |
|
||||
| F8 Muxes | 1 | 0 | 4400 | 0.02 |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
|
||||
|
||||
@ -54,23 +54,25 @@ Table of Contents
|
||||
| 0 | _ | Set | - |
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 0 | Yes | - | Set |
|
||||
| 0 | Yes | - | Reset |
|
||||
| 0 | Yes | Set | - |
|
||||
| 21 | Yes | Reset | - |
|
||||
| 10 | Yes | - | Set |
|
||||
| 85 | Yes | - | Reset |
|
||||
| 1 | Yes | Set | - |
|
||||
| 114 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
2. Memory
|
||||
---------
|
||||
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Block RAM Tile | 0 | 0 | 60 | 0.00 |
|
||||
| RAMB36/FIFO* | 0 | 0 | 60 | 0.00 |
|
||||
| RAMB18 | 0 | 0 | 120 | 0.00 |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
| Block RAM Tile | 22.5 | 0 | 60 | 37.50 |
|
||||
| RAMB36/FIFO* | 18 | 0 | 60 | 30.00 |
|
||||
| RAMB36E1 only | 18 | | | |
|
||||
| RAMB18 | 9 | 0 | 120 | 7.50 |
|
||||
| RAMB18E1 only | 9 | | | |
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||
|
||||
|
||||
@ -90,7 +92,7 @@ Table of Contents
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Bonded IOB | 18 | 0 | 100 | 18.00 |
|
||||
| Bonded IOB | 24 | 0 | 100 | 24.00 |
|
||||
| Bonded IPADs | 0 | 0 | 2 | 0.00 |
|
||||
| Bonded IOPADs | 0 | 0 | 130 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 2 | 0.00 |
|
||||
@ -146,15 +148,25 @@ Table of Contents
|
||||
+----------+------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+------+---------------------+
|
||||
| LUT6 | 65 | LUT |
|
||||
| LUT4 | 62 | LUT |
|
||||
| LUT5 | 47 | LUT |
|
||||
| CARRY4 | 34 | CarryLogic |
|
||||
| LUT2 | 28 | LUT |
|
||||
| FDRE | 21 | Flop & Latch |
|
||||
| OBUF | 18 | IO |
|
||||
| LUT3 | 7 | LUT |
|
||||
| LUT1 | 4 | LUT |
|
||||
| LUT6 | 447 | LUT |
|
||||
| LUT4 | 365 | LUT |
|
||||
| LUT5 | 358 | LUT |
|
||||
| LUT3 | 323 | LUT |
|
||||
| LUT2 | 275 | LUT |
|
||||
| CARRY4 | 266 | CarryLogic |
|
||||
| FDRE | 114 | Flop & Latch |
|
||||
| FDCE | 62 | Flop & Latch |
|
||||
| LDCE | 23 | Flop & Latch |
|
||||
| OBUF | 21 | IO |
|
||||
| MUXF7 | 19 | MuxFx |
|
||||
| RAMB36E1 | 18 | Block Memory |
|
||||
| LUT1 | 12 | LUT |
|
||||
| FDPE | 10 | Flop & Latch |
|
||||
| RAMB18E1 | 9 | Block Memory |
|
||||
| IBUF | 2 | IO |
|
||||
| OBUFT | 1 | IO |
|
||||
| MUXF8 | 1 | MuxFx |
|
||||
| FDSE | 1 | Flop & Latch |
|
||||
+----------+------+---------------------+
|
||||
|
||||
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
# This file is automatically generated.
|
||||
# It contains project source information necessary for synthesis and implementation.
|
||||
|
||||
# XDC: C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc
|
||||
# XDC: C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/ZYBO_Master.xdc
|
||||
|
||||
# IP: ip/clk_wiz_0_1/clk_wiz_0.xci
|
||||
# IP: ip/clk_wiz_0_2/clk_wiz_0.xci
|
||||
set_property DONT_TOUCH TRUE [get_cells -hier -filter {REF_NAME==clk_wiz_0 || ORIG_REF_NAME==clk_wiz_0} -quiet] -quiet
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="synth_1" LaunchPart="xc7z010clg400-1" LaunchTime="1638877259">
|
||||
<GenRun Id="synth_1" LaunchPart="xc7z010clg400-1" LaunchTime="1641295056">
|
||||
<File Type="PA-TCL" Name="VGA_top.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="VGA_top_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="VGA_top_reports.tcl"/>
|
||||
@ -11,52 +11,83 @@
|
||||
<File Type="VDS-TIMING-PB" Name="VGA_top_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xci">
|
||||
<File Path="$PSRCDIR/sources_1/ip/clk_wiz_0_2/clk_wiz_0.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/Diviseur.vhd">
|
||||
<File Path="$PPRDIR/sources_snake/Diviseur.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../../../Downloads/VGA Game 2017 V1-20211109/GeneRGB_V1.vhd">
|
||||
<File Path="$PPRDIR/sources_snake/types.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="Library" Val="ourTypes"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/sources_snake/GeneRGB_V1.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../../../Downloads/VGA Game 2017 V1-20211109/GeneSync.vhd">
|
||||
<File Path="$PPRDIR/sources_snake/GeneSync.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/Gene_Position.vhd">
|
||||
<File Path="$PPRDIR/sources_snake/Gene_Snake.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/Gene_Snake.vhd">
|
||||
<File Path="$PPRDIR/sources_snake/updateSnake.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../../../Downloads/VGA Game 2017 V1-20211109/VGA_top.vhd">
|
||||
<File Path="$PPRDIR/sources_snake/RAMController.vhd">
|
||||
<FileInfo SFType="VHDL2008">
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/sources_snake/snakeRam.vhd">
|
||||
<FileInfo SFType="VHDL2008">
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/sources_snake/spritesRom.vhd">
|
||||
<FileInfo SFType="VHDL2008">
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/sources_snake/VGA_top.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/Gene_Balle.vhd">
|
||||
<File Path="$PPRDIR/sources_snake/testBench.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UserDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/sprites/sprites.mem">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
@ -69,7 +100,7 @@
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PPRDIR/../../../../../Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc">
|
||||
<File Path="$PPRDIR/sources_snake/ZYBO_Master.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
|
||||
@ -1,32 +0,0 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:38:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:5648444c:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:5648444c:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c636c6b5f77697a5f76365f305f325c636c6b5f77697a5f30:636f72655f636f6e7461696e6572:66616c7365:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:32:00:00
|
||||
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3535383763343761323538363466333061393431643931396134353838663432:506172656e742050412070726f6a656374204944:00
|
||||
eof:1227587853
|
||||
File diff suppressed because it is too large
Load Diff
@ -24,7 +24,7 @@ else
|
||||
fi
|
||||
export LD_LIBRARY_PATH
|
||||
|
||||
HD_PWD='C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/synth_1'
|
||||
HD_PWD='C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/synth_1'
|
||||
cd "$HD_PWD"
|
||||
|
||||
HD_LOG=runme.log
|
||||
|
||||
@ -2,11 +2,11 @@
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Tue Dec 7 12:41:01 2021
|
||||
# Process ID: 5952
|
||||
# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/synth_1
|
||||
# Start of session at: Tue Jan 4 12:17:37 2022
|
||||
# Process ID: 5272
|
||||
# Current directory: C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/synth_1
|
||||
# Command line: vivado.exe -log VGA_top.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source VGA_top.tcl
|
||||
# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/synth_1/VGA_top.vds
|
||||
# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/synth_1\vivado.jou
|
||||
# Log file: C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/synth_1/VGA_top.vds
|
||||
# Journal file: C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/synth_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source VGA_top.tcl -notrace
|
||||
|
||||
Binary file not shown.
Some files were not shown because too many files have changed in this diff Show More
Loading…
x
Reference in New Issue
Block a user