8 lines
394 B
Tcl
8 lines
394 B
Tcl
# This file is automatically generated.
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# It contains project source information necessary for synthesis and implementation.
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# XDC: C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/ZYBO_Master.xdc
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# IP: ip/clk_wiz_0_2/clk_wiz_0.xci
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set_property DONT_TOUCH TRUE [get_cells -hier -filter {REF_NAME==clk_wiz_0 || ORIG_REF_NAME==clk_wiz_0} -quiet] -quiet
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