63 lines
1.4 KiB
VHDL
63 lines
1.4 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 23.11.2021 11:56:55
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-- Design Name:
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-- Module Name: Diviseur - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity Diviseur is
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generic (nbBits : integer:=8);
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Port ( clk_in : in STD_LOGIC;
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reset : in STD_LOGIC;
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max : in unsigned (nbBits-1 downto 0);
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clk_out : out STD_LOGIC);
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end Diviseur;
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architecture Behavioral of Diviseur is
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signal temp : unsigned (nbBits-1 downto 0);
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begin
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process(clk_in,reset)
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begin
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if reset='0' then
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temp<=(others=>'0');
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elsif (clk_in'event and clk_in='1') then
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temp <= temp+1;
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if temp=max then
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clk_out <= '1';
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temp <= (others => '0');
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else
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clk_out <= '0';
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end if;
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end if;
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end process;
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end Behavioral;
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