176 lines
6.3 KiB
Tcl
176 lines
6.3 KiB
Tcl
#
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# Report generation script generated by Vivado
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#
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proc create_report { reportName command } {
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set status "."
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append status $reportName ".fail"
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if { [file exists $status] } {
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eval file delete [glob $status]
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}
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send_msg_id runtcl-4 info "Executing : $command"
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set retval [eval catch { $command } msg]
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if { $retval != 0 } {
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set fp [open $status w]
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close $fp
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send_msg_id runtcl-5 warning "$msg"
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}
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}
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proc start_step { step } {
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set stopFile ".stop.rst"
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if {[file isfile .stop.rst]} {
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puts ""
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puts "*** Halting run - EA reset detected ***"
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puts ""
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puts ""
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return -code error
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}
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set beginFile ".$step.begin.rst"
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set platform "$::tcl_platform(platform)"
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set user "$::tcl_platform(user)"
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set pid [pid]
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set host ""
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if { [string equal $platform unix] } {
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if { [info exist ::env(HOSTNAME)] } {
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set host $::env(HOSTNAME)
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}
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} else {
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if { [info exist ::env(COMPUTERNAME)] } {
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set host $::env(COMPUTERNAME)
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}
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}
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set ch [open $beginFile w]
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puts $ch "<?xml version=\"1.0\"?>"
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puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
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puts $ch " <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
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puts $ch " </Process>"
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puts $ch "</ProcessHandle>"
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close $ch
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}
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proc end_step { step } {
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set endFile ".$step.end.rst"
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set ch [open $endFile w]
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close $ch
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}
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proc step_failed { step } {
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set endFile ".$step.error.rst"
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set ch [open $endFile w]
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close $ch
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}
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set_msg_config -id {Synth 8-256} -limit 10000
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set_msg_config -id {Synth 8-638} -limit 10000
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start_step init_design
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set ACTIVE_STEP init_design
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set rc [catch {
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create_msg_db init_design.pb
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set_param xicom.use_bs_reader 1
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create_project -in_memory -part xc7z010clg400-1
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set_property design_mode GateLvl [current_fileset]
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set_param project.singleFileAddWarning.threshold 0
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set_property webtalk.parent_dir C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.cache/wt [current_project]
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set_property parent.project_path C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.xpr [current_project]
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set_property ip_output_repo C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.cache/ip [current_project]
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set_property ip_cache_permissions {read write} [current_project]
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set_property XPM_LIBRARIES XPM_CDC [current_project]
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add_files -quiet C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/synth_1/VGA_top.dcp
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read_ip -quiet c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0.xci
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read_xdc C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/ZYBO_Master.xdc
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link_design -top VGA_top -part xc7z010clg400-1
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close_msg_db -file init_design.pb
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} RESULT]
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if {$rc} {
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step_failed init_design
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return -code error $RESULT
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} else {
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end_step init_design
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unset ACTIVE_STEP
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}
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start_step opt_design
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set ACTIVE_STEP opt_design
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set rc [catch {
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create_msg_db opt_design.pb
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opt_design
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write_checkpoint -force VGA_top_opt.dcp
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create_report "impl_1_opt_report_drc_0" "report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx"
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close_msg_db -file opt_design.pb
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} RESULT]
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if {$rc} {
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step_failed opt_design
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return -code error $RESULT
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} else {
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end_step opt_design
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unset ACTIVE_STEP
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}
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start_step place_design
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set ACTIVE_STEP place_design
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set rc [catch {
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create_msg_db place_design.pb
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if { [llength [get_debug_cores -quiet] ] > 0 } {
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implement_debug_core
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}
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place_design
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write_checkpoint -force VGA_top_placed.dcp
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create_report "impl_1_place_report_io_0" "report_io -file VGA_top_io_placed.rpt"
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create_report "impl_1_place_report_utilization_0" "report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb"
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create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file VGA_top_control_sets_placed.rpt"
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close_msg_db -file place_design.pb
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} RESULT]
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if {$rc} {
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step_failed place_design
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return -code error $RESULT
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} else {
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end_step place_design
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unset ACTIVE_STEP
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}
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start_step route_design
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set ACTIVE_STEP route_design
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set rc [catch {
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create_msg_db route_design.pb
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route_design
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write_checkpoint -force VGA_top_routed.dcp
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create_report "impl_1_route_report_drc_0" "report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx"
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create_report "impl_1_route_report_methodology_0" "report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx"
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create_report "impl_1_route_report_power_0" "report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx"
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create_report "impl_1_route_report_route_status_0" "report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb"
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create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation "
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create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt"
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create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file VGA_top_clock_utilization_routed.rpt"
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create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx"
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close_msg_db -file route_design.pb
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} RESULT]
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if {$rc} {
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write_checkpoint -force VGA_top_routed_error.dcp
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step_failed route_design
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return -code error $RESULT
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} else {
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end_step route_design
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unset ACTIVE_STEP
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}
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start_step write_bitstream
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set ACTIVE_STEP write_bitstream
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set rc [catch {
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create_msg_db write_bitstream.pb
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set_property XPM_LIBRARIES XPM_CDC [current_project]
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catch { write_mem_info -force VGA_top.mmi }
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write_bitstream -force VGA_top.bit
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catch {write_debug_probes -quiet -force VGA_top}
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catch {file copy -force VGA_top.ltx debug_nets.ltx}
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close_msg_db -file write_bitstream.pb
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} RESULT]
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if {$rc} {
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step_failed write_bitstream
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return -code error $RESULT
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} else {
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end_step write_bitstream
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unset ACTIVE_STEP
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}
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