128 lines
4.2 KiB
VHDL
128 lines
4.2 KiB
VHDL
----------------------------------------------------------------------------------
|
|
-- Company:
|
|
-- Engineer:
|
|
--
|
|
-- Create Date: 12/15/2021 02:06:27 PM
|
|
-- Design Name:
|
|
-- Module Name: updateSnake - Behavioral
|
|
-- Project Name:
|
|
-- Target Devices:
|
|
-- Tool Versions:
|
|
-- Description:
|
|
--
|
|
-- Dependencies:
|
|
--
|
|
-- Revision:
|
|
-- Revision 0.01 - File Created
|
|
-- Additional Comments:
|
|
--
|
|
----------------------------------------------------------------------------------
|
|
|
|
|
|
library IEEE;
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
|
|
|
-- Uncomment the following library declaration if using
|
|
-- arithmetic functions with Signed or Unsigned values
|
|
use IEEE.NUMERIC_STD.ALL;
|
|
|
|
library ourTypes;
|
|
use ourTypes.types.all;
|
|
|
|
-- Uncomment the following library declaration if instantiating
|
|
-- any Xilinx leaf cells in this code.
|
|
--library UNISIM;
|
|
--use UNISIM.VComponents.all;
|
|
|
|
entity updateSnake is
|
|
generic ( dataSize : integer);
|
|
Port (
|
|
clk_lente : in std_logic;
|
|
clk_rapide : in std_logic;
|
|
reset : in std_logic;
|
|
|
|
address : out unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
|
|
dataIn : in std_logic_vector(dataSize-1 downto 0);
|
|
dataOut : out std_logic_vector(dataSize-1 downto 0);
|
|
writeEnable : out std_logic := '1';
|
|
|
|
matAddress : out unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
|
|
matDataIn : inout std_logic_vector(SNAKE_ADDRESS_SIZE-1 downto 0);
|
|
matDataOut : out std_logic_vector(SNAKE_ADDRESS_SIZE-1 downto 0);
|
|
matWriteEnable : out std_logic := '1'
|
|
);
|
|
end updateSnake;
|
|
|
|
architecture Behavioral of updateSnake is
|
|
signal index : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0) := to_unsigned(0,SNAKE_ADDRESS_SIZE);
|
|
signal currentSnake : pos;
|
|
signal update: std_logic;
|
|
signal isUpdating: std_logic;
|
|
signal updateIndex : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
|
|
signal state : unsigned(3 downto 0);
|
|
begin
|
|
process(currentSnake, updateIndex, update, clk_rapide, clk_lente,reset,index) --process de reset
|
|
variable cSnake : pos;
|
|
begin
|
|
|
|
if rising_edge(clk_lente) then
|
|
isUpdating <= '1';
|
|
updateIndex <= to_unsigned(0,SNAKE_ADDRESS_SIZE);
|
|
end if;
|
|
if(clk_rapide'event and clk_rapide = '1') then
|
|
if(reset = '0') then --il faut qu'on ai le reset sur la clk car il controle indirectement l'entrée de la RAM
|
|
index <= to_unsigned(0,SNAKE_ADDRESS_SIZE);
|
|
writeEnable <= '1';
|
|
matWriteEnable <= '1';
|
|
update <= '0';
|
|
else
|
|
index <= index + 1;
|
|
if(index = MAX_SNAKE-1) then
|
|
index <= to_unsigned(0,SNAKE_ADDRESS_SIZE);
|
|
writeEnable <= '0';
|
|
matWriteEnable <= '0';
|
|
update <= '1';
|
|
end if;
|
|
end if;
|
|
if(update = '1') then
|
|
state <= state + 1;
|
|
|
|
if(state = 0) then
|
|
writeEnable <= '0';
|
|
elsif(state = 1) then
|
|
cSnake := to_pos(dataIn);
|
|
cSnake.X := cSnake.X + to_integer(cSnake.dirX);
|
|
cSnake.Y := cSnake.Y + to_integer(cSnake.dirY);
|
|
dataOut <= to_stdlogicvector(cSnake);
|
|
writeEnable <= '1';
|
|
elsif(state = 2) then
|
|
writeEnable <= '0';
|
|
isUpdating <= '0';
|
|
updateIndex <= updateIndex + 1;
|
|
state <= to_unsigned(0,4);
|
|
end if;
|
|
end if;
|
|
end if;
|
|
|
|
if update = '0' then
|
|
dataOut <= to_stdlogicvector(currentSnake);
|
|
if(index < 13) then
|
|
currentSnake.X <= to_unsigned(8+to_integer(index)*16,10);
|
|
currentSnake.Y <= to_unsigned(8,9);
|
|
currentSnake.dirX <= to_signed(-1,2);
|
|
currentSnake.dirY <= to_signed(0,2);
|
|
currentSnake.isDefined <= '1';
|
|
else
|
|
currentSnake.X <= to_unsigned(8,10);
|
|
currentSnake.Y <= to_unsigned(8,9);
|
|
currentSnake.dirX <= to_signed(0,2);
|
|
currentSnake.dirY <= to_signed(1,2);
|
|
currentSnake.isDefined <= '0';
|
|
end if;
|
|
matAddress <= to_unsigned(to_integer(index),SNAKE_ADDRESS_SIZE);
|
|
matDataOut <= std_logic_vector(to_unsigned(to_integer(index),SNAKE_ADDRESS_SIZE));
|
|
end if;
|
|
end process;
|
|
address <= index;
|
|
end Behavioral;
|