769 lines
74 KiB
Plaintext
769 lines
74 KiB
Plaintext
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*** Running vivado
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with args -log VGA_top.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source VGA_top.tcl
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****** Vivado v2018.3 (64-bit)
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**** SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
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**** IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
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** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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source VGA_top.tcl -notrace
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Command: synth_design -top VGA_top -part xc7z010clg400-1
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Starting synth_design
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Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010'
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INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010'
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INFO: Launching helper process for spawning children vivado processes
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INFO: Helper process launched with PID 8152
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---------------------------------------------------------------------------------
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Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 467.723 ; gain = 93.676
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---------------------------------------------------------------------------------
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INFO: [Synth 8-638] synthesizing module 'VGA_top' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/VGA_top.vhd:48]
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INFO: [Synth 8-637] synthesizing blackbox instance 'U0' of component 'clk_wiz_0' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/VGA_top.vhd:217]
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INFO: [Synth 8-3491] module 'GeneSync' declared at 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/GeneSync.vhd:8' bound to instance 'SYNC' of component 'GeneSync' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/VGA_top.vhd:235]
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INFO: [Synth 8-638] synthesizing module 'GeneSync' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/GeneSync.vhd:17]
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WARNING: [Synth 8-312] ignoring unsynthesizable construct: non-synthesizable procedure call [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/GeneSync.vhd:45]
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INFO: [Synth 8-256] done synthesizing module 'GeneSync' (1#1) [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/GeneSync.vhd:17]
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INFO: [Synth 8-3491] module 'GeneRGB_V1' declared at 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/GeneRGB_V1.vhd:37' bound to instance 'RGB' of component 'GeneRGB_V1' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/VGA_top.vhd:244]
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INFO: [Synth 8-638] synthesizing module 'GeneRGB_V1' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/GeneRGB_V1.vhd:47]
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INFO: [Synth 8-256] done synthesizing module 'GeneRGB_V1' (2#1) [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/GeneRGB_V1.vhd:47]
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Parameter nbBits bound to: 25 - type: integer
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INFO: [Synth 8-3491] module 'Diviseur' declared at 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Diviseur.vhd:34' bound to instance 'UPD_CLK_DIV' of component 'Diviseur' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/VGA_top.vhd:254]
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INFO: [Synth 8-638] synthesizing module 'Diviseur' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Diviseur.vhd:42]
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Parameter nbBits bound to: 25 - type: integer
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INFO: [Synth 8-256] done synthesizing module 'Diviseur' (3#1) [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Diviseur.vhd:42]
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Parameter addressSize bound to: 11 - type: integer
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INFO: [Synth 8-3491] module 'Gene_Snake' declared at 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:39' bound to instance 'SNAKE' of component 'Gene_Snake' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/VGA_top.vhd:265]
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INFO: [Synth 8-638] synthesizing module 'Gene_Snake' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:63]
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Parameter addressSize bound to: 11 - type: integer
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INFO: [Synth 8-226] default block is never used [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109]
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INFO: [Synth 8-226] default block is never used [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109]
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INFO: [Synth 8-226] default block is never used [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109]
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INFO: [Synth 8-226] default block is never used [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109]
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INFO: [Synth 8-226] default block is never used [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109]
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INFO: [Synth 8-226] default block is never used [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109]
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INFO: [Synth 8-226] default block is never used [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109]
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INFO: [Synth 8-226] default block is never used [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109]
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INFO: [Synth 8-226] default block is never used [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109]
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WARNING: [Synth 8-6014] Unused sequential element iterInd_reg was removed. [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:97]
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WARNING: [Synth 8-6014] Unused sequential element sX_reg was removed. [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:100]
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WARNING: [Synth 8-6014] Unused sequential element sY_reg was removed. [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:101]
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WARNING: [Synth 8-6014] Unused sequential element sOff_reg was removed. [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:103]
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INFO: [Synth 8-256] done synthesizing module 'Gene_Snake' (4#1) [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:63]
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Parameter snakeDataSize bound to: 24 - type: integer
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INFO: [Synth 8-3491] module 'RAMController' declared at 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/RAMController.vhd:9' bound to instance 'RAMCTRL' of component 'RAMController' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/VGA_top.vhd:284]
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INFO: [Synth 8-638] synthesizing module 'RAMController' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/RAMController.vhd:37]
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Parameter snakeDataSize bound to: 24 - type: integer
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Parameter length bound to: 1200 - type: integer
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Parameter addressSize bound to: 11 - type: integer
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Parameter dataSize bound to: 24 - type: integer
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INFO: [Synth 8-3491] module 'snakeRam' declared at 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/snakeRam.vhd:37' bound to instance 'SNAKE_RAM' of component 'snakeRam' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/RAMController.vhd:61]
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INFO: [Synth 8-638] synthesizing module 'snakeRam' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/snakeRam.vhd:54]
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Parameter length bound to: 1200 - type: integer
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Parameter addressSize bound to: 11 - type: integer
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Parameter dataSize bound to: 24 - type: integer
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INFO: [Synth 8-256] done synthesizing module 'snakeRam' (5#1) [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/snakeRam.vhd:54]
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Parameter length bound to: 1200 - type: integer
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Parameter addressSize bound to: 11 - type: integer
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Parameter dataSize bound to: 11 - type: integer
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INFO: [Synth 8-3491] module 'snakeRam' declared at 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/snakeRam.vhd:37' bound to instance 'MAT_RAM' of component 'snakeRam' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/RAMController.vhd:79]
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INFO: [Synth 8-638] synthesizing module 'snakeRam__parameterized1' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/snakeRam.vhd:54]
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Parameter length bound to: 1200 - type: integer
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Parameter addressSize bound to: 11 - type: integer
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Parameter dataSize bound to: 11 - type: integer
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INFO: [Synth 8-256] done synthesizing module 'snakeRam__parameterized1' (5#1) [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/snakeRam.vhd:54]
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INFO: [Synth 8-256] done synthesizing module 'RAMController' (6#1) [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/RAMController.vhd:37]
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Parameter dataSize bound to: 24 - type: integer
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INFO: [Synth 8-3491] module 'updateSnake' declared at 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:37' bound to instance 'UPD' of component 'updateSnake' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/VGA_top.vhd:309]
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INFO: [Synth 8-638] synthesizing module 'updateSnake' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:56]
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Parameter dataSize bound to: 24 - type: integer
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WARNING: [Synth 8-5825] expecting unsigned expression [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:112]
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WARNING: [Synth 8-6014] Unused sequential element cSnake_reg[X] was removed. [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:93]
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WARNING: [Synth 8-6014] Unused sequential element cSnake_reg[Y] was removed. [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:93]
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WARNING: [Synth 8-6014] Unused sequential element cSnake_reg[dirX] was removed. [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:93]
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WARNING: [Synth 8-6014] Unused sequential element cSnake_reg[dirY] was removed. [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:93]
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WARNING: [Synth 8-6014] Unused sequential element cSnake_reg[isDefined] was removed. [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:93]
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WARNING: [Synth 8-6014] Unused sequential element isUpdating_reg was removed. [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:69]
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WARNING: [Synth 8-6014] Unused sequential element updateIndex_reg was removed. [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:70]
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INFO: [Synth 8-256] done synthesizing module 'updateSnake' (7#1) [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:56]
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Parameter addressSize bound to: 10 - type: integer
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Parameter length bound to: 768 - type: integer
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Parameter dataSize bound to: 24 - type: integer
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Parameter fileName bound to: C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sprites/sprites.mem - type: string
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INFO: [Synth 8-3491] module 'spritesRom' declared at 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/spritesRom.vhd:36' bound to instance 'ROM' of component 'spritesRom' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/VGA_top.vhd:326]
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INFO: [Synth 8-638] synthesizing module 'spritesRom' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/spritesRom.vhd:47]
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Parameter addressSize bound to: 10 - type: integer
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Parameter length bound to: 768 - type: integer
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Parameter dataSize bound to: 24 - type: integer
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Parameter fileName bound to: C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sprites/sprites.mem - type: string
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INFO: [Synth 8-256] done synthesizing module 'spritesRom' (8#1) [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/spritesRom.vhd:47]
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INFO: [Synth 8-256] done synthesizing module 'VGA_top' (9#1) [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/VGA_top.vhd:48]
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WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[10]
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WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[9]
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WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[8]
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WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[7]
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WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[6]
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WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[5]
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WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[4]
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WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[3]
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WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[2]
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WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[1]
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WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[0]
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WARNING: [Synth 8-3331] design updateSnake has unconnected port clk_lente
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WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[9]
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WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[8]
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WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[7]
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WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[6]
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WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[5]
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WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[4]
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WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[3]
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WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[2]
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WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[1]
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WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[0]
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WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[8]
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WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[7]
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WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[6]
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WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[5]
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WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[4]
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WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[3]
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WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[2]
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WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[1]
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WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[0]
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WARNING: [Synth 8-3331] design VGA_top has unconnected port led[3]
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---------------------------------------------------------------------------------
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Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 528.090 ; gain = 154.043
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---------------------------------------------------------------------------------
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Report Check Netlist:
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+------+------------------+-------+---------+-------+------------------+
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| |Item |Errors |Warnings |Status |Description |
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+------+------------------+-------+---------+-------+------------------+
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|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
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+------+------------------+-------+---------+-------+------------------+
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---------------------------------------------------------------------------------
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Start Handling Custom Attributes
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 528.090 ; gain = 154.043
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 528.090 ; gain = 154.043
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---------------------------------------------------------------------------------
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INFO: [Device 21-403] Loading part xc7z010clg400-1
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INFO: [Project 1-570] Preparing netlist for logic optimization
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Processing XDC Constraints
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Initializing timing engine
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Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0/clk_wiz_1_in_context.xdc] for cell 'U0'
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Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0/clk_wiz_1_in_context.xdc] for cell 'U0'
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Parsing XDC File [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/ZYBO_Master.xdc]
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Finished Parsing XDC File [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/ZYBO_Master.xdc]
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/ZYBO_Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/VGA_top_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/VGA_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Parsing XDC File [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/synth_1/dont_touch.xdc]
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Finished Parsing XDC File [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/synth_1/dont_touch.xdc]
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 876.688 ; gain = 0.000
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Completed Processing XDC Constraints
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 876.688 ; gain = 0.000
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INFO: [Project 1-111] Unisim Transformation Summary:
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No Unisim elements were transformed.
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 876.688 ; gain = 0.000
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Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 876.688 ; gain = 0.000
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---------------------------------------------------------------------------------
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Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:22 . Memory (MB): peak = 876.688 ; gain = 502.641
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Loading Part and Timing Information
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---------------------------------------------------------------------------------
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Loading part: xc7z010clg400-1
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---------------------------------------------------------------------------------
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Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:22 . Memory (MB): peak = 876.688 ; gain = 502.641
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Applying 'set_property' XDC Constraints
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---------------------------------------------------------------------------------
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Applied set_property IO_BUFFER_TYPE = NONE for H125MHz. (constraint file c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0/clk_wiz_1_in_context.xdc, line 3).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for H125MHz. (constraint file c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0/clk_wiz_1_in_context.xdc, line 4).
|
|
Applied set_property DONT_TOUCH = true for U0. (constraint file auto generated constraint, line ).
|
|
---------------------------------------------------------------------------------
|
|
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:22 . Memory (MB): peak = 876.688 ; gain = 502.641
|
|
---------------------------------------------------------------------------------
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109]
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <multiplier> is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109]
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109]
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <multiplier> is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109]
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98]
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <multiplier> is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98]
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109]
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <multiplier> is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109]
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98]
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <multiplier> is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98]
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109]
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <multiplier> is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109]
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98]
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <multiplier> is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98]
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109]
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <multiplier> is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109]
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98]
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <multiplier> is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98]
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109]
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <multiplier> is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109]
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98]
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <multiplier> is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98]
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109]
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <multiplier> is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109]
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98]
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <multiplier> is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98]
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109]
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <multiplier> is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109]
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98]
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <multiplier> is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98]
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109]
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <multiplier> is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109]
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98]
|
|
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <multiplier> is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98]
|
|
INFO: [Synth 8-5544] ROM "sOff" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|
INFO: [Synth 8-5544] ROM "sOff" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|
INFO: [Synth 8-5544] ROM "sOff" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|
INFO: [Synth 8-5544] ROM "sOff" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|
INFO: [Synth 8-5544] ROM "sOff" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|
INFO: [Synth 8-5544] ROM "sOff" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|
INFO: [Synth 8-5544] ROM "sOff" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|
INFO: [Synth 8-5544] ROM "sOff" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|
INFO: [Synth 8-5544] ROM "sOff" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
|
|
INFO: [Synth 8-5545] ROM "running" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
|
|
INFO: [Synth 8-5545] ROM "dataReady" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
|
|
INFO: [Synth 8-5545] ROM "clkCount" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
|
|
INFO: [Synth 8-5546] ROM "writeEnable" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5544] ROM "writeEnable" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
|
INFO: [Synth 8-5546] ROM "mem" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-3971] The signal mem_reg was recognized as a true dual port RAM template.
|
|
INFO: [Synth 8-3971] The signal mem_reg was recognized as a true dual port RAM template.
|
|
WARNING: [Synth 8-327] inferring latch for variable 'currentSnake_reg[isDefined]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:108]
|
|
WARNING: [Synth 8-327] inferring latch for variable 'currentSnake_reg[dirY]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:108]
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|
WARNING: [Synth 8-327] inferring latch for variable 'currentSnake_reg[dirX]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:108]
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|
WARNING: [Synth 8-327] inferring latch for variable 'currentSnake_reg[Y]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:108]
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|
WARNING: [Synth 8-327] inferring latch for variable 'currentSnake_reg[X]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:108]
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|
WARNING: [Synth 8-327] inferring latch for variable 'matAddress_reg' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:122]
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|
---------------------------------------------------------------------------------
|
|
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:23 . Memory (MB): peak = 876.688 ; gain = 502.641
|
|
---------------------------------------------------------------------------------
|
|
|
|
Report RTL Partitions:
|
|
+-+--------------+------------+----------+
|
|
| |RTL Partition |Replication |Instances |
|
|
+-+--------------+------------+----------+
|
|
+-+--------------+------------+----------+
|
|
---------------------------------------------------------------------------------
|
|
Start RTL Component Statistics
|
|
---------------------------------------------------------------------------------
|
|
Detailed RTL Component Info :
|
|
+---Adders :
|
|
2 Input 32 Bit Adders := 1
|
|
2 Input 11 Bit Adders := 2
|
|
3 Input 11 Bit Adders := 9
|
|
2 Input 10 Bit Adders := 21
|
|
3 Input 10 Bit Adders := 18
|
|
2 Input 9 Bit Adders := 20
|
|
2 Input 8 Bit Adders := 1
|
|
2 Input 7 Bit Adders := 2
|
|
2 Input 6 Bit Adders := 1
|
|
2 Input 4 Bit Adders := 1
|
|
+---Registers :
|
|
32 Bit Registers := 1
|
|
24 Bit Registers := 12
|
|
11 Bit Registers := 13
|
|
10 Bit Registers := 1
|
|
8 Bit Registers := 1
|
|
6 Bit Registers := 2
|
|
5 Bit Registers := 3
|
|
4 Bit Registers := 1
|
|
1 Bit Registers := 8
|
|
+---RAMs :
|
|
28K Bit RAMs := 1
|
|
12K Bit RAMs := 1
|
|
+---Muxes :
|
|
2 Input 32 Bit Muxes := 1
|
|
2 Input 24 Bit Muxes := 2
|
|
769 Input 24 Bit Muxes := 1
|
|
2 Input 12 Bit Muxes := 9
|
|
2 Input 11 Bit Muxes := 12
|
|
2 Input 10 Bit Muxes := 45
|
|
2 Input 9 Bit Muxes := 4
|
|
2 Input 8 Bit Muxes := 5
|
|
2 Input 7 Bit Muxes := 1
|
|
2 Input 6 Bit Muxes := 2
|
|
2 Input 5 Bit Muxes := 4
|
|
2 Input 4 Bit Muxes := 1
|
|
4 Input 4 Bit Muxes := 1
|
|
2 Input 1 Bit Muxes := 14
|
|
9 Input 1 Bit Muxes := 2
|
|
3 Input 1 Bit Muxes := 2
|
|
---------------------------------------------------------------------------------
|
|
Finished RTL Component Statistics
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start RTL Hierarchical Component Statistics
|
|
---------------------------------------------------------------------------------
|
|
Hierarchical RTL Component report
|
|
Module GeneSync
|
|
Detailed RTL Component Info :
|
|
+---Adders :
|
|
2 Input 11 Bit Adders := 1
|
|
2 Input 10 Bit Adders := 2
|
|
2 Input 9 Bit Adders := 1
|
|
+---Registers :
|
|
11 Bit Registers := 1
|
|
10 Bit Registers := 1
|
|
+---Muxes :
|
|
2 Input 10 Bit Muxes := 3
|
|
2 Input 9 Bit Muxes := 3
|
|
Module GeneRGB_V1
|
|
Detailed RTL Component Info :
|
|
+---Muxes :
|
|
2 Input 6 Bit Muxes := 1
|
|
2 Input 5 Bit Muxes := 2
|
|
Module Gene_Snake
|
|
Detailed RTL Component Info :
|
|
+---Adders :
|
|
3 Input 11 Bit Adders := 9
|
|
2 Input 10 Bit Adders := 18
|
|
3 Input 10 Bit Adders := 18
|
|
2 Input 9 Bit Adders := 18
|
|
+---Registers :
|
|
8 Bit Registers := 1
|
|
6 Bit Registers := 2
|
|
5 Bit Registers := 3
|
|
1 Bit Registers := 3
|
|
+---Muxes :
|
|
2 Input 12 Bit Muxes := 9
|
|
2 Input 11 Bit Muxes := 9
|
|
2 Input 10 Bit Muxes := 42
|
|
2 Input 8 Bit Muxes := 1
|
|
2 Input 6 Bit Muxes := 1
|
|
2 Input 5 Bit Muxes := 2
|
|
2 Input 1 Bit Muxes := 2
|
|
9 Input 1 Bit Muxes := 2
|
|
Module snakeRam
|
|
Detailed RTL Component Info :
|
|
+---Registers :
|
|
24 Bit Registers := 10
|
|
+---RAMs :
|
|
28K Bit RAMs := 1
|
|
Module snakeRam__parameterized1
|
|
Detailed RTL Component Info :
|
|
+---Registers :
|
|
11 Bit Registers := 10
|
|
+---RAMs :
|
|
12K Bit RAMs := 1
|
|
Module RAMController
|
|
Detailed RTL Component Info :
|
|
+---Adders :
|
|
2 Input 32 Bit Adders := 1
|
|
2 Input 8 Bit Adders := 1
|
|
2 Input 7 Bit Adders := 2
|
|
2 Input 6 Bit Adders := 1
|
|
+---Registers :
|
|
32 Bit Registers := 1
|
|
1 Bit Registers := 2
|
|
+---Muxes :
|
|
2 Input 32 Bit Muxes := 1
|
|
2 Input 11 Bit Muxes := 2
|
|
2 Input 9 Bit Muxes := 1
|
|
2 Input 8 Bit Muxes := 3
|
|
2 Input 7 Bit Muxes := 1
|
|
2 Input 1 Bit Muxes := 3
|
|
Module updateSnake
|
|
Detailed RTL Component Info :
|
|
+---Adders :
|
|
2 Input 11 Bit Adders := 1
|
|
2 Input 10 Bit Adders := 1
|
|
2 Input 9 Bit Adders := 1
|
|
2 Input 4 Bit Adders := 1
|
|
+---Registers :
|
|
24 Bit Registers := 1
|
|
11 Bit Registers := 2
|
|
4 Bit Registers := 1
|
|
1 Bit Registers := 3
|
|
+---Muxes :
|
|
2 Input 24 Bit Muxes := 2
|
|
2 Input 11 Bit Muxes := 1
|
|
2 Input 8 Bit Muxes := 1
|
|
2 Input 4 Bit Muxes := 1
|
|
4 Input 4 Bit Muxes := 1
|
|
2 Input 1 Bit Muxes := 9
|
|
3 Input 1 Bit Muxes := 2
|
|
Module spritesRom
|
|
Detailed RTL Component Info :
|
|
+---Registers :
|
|
24 Bit Registers := 1
|
|
+---Muxes :
|
|
769 Input 24 Bit Muxes := 1
|
|
---------------------------------------------------------------------------------
|
|
Finished RTL Hierarchical Component Statistics
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Part Resource Summary
|
|
---------------------------------------------------------------------------------
|
|
Part Resources:
|
|
DSPs: 80 (col length:40)
|
|
BRAMs: 120 (col length: RAMB18 40 RAMB36 20)
|
|
---------------------------------------------------------------------------------
|
|
Finished Part Resource Summary
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Cross Boundary and Area Optimization
|
|
---------------------------------------------------------------------------------
|
|
Warning: Parallel synthesis criteria is not met
|
|
INFO: [Synth 8-5545] ROM "clkCount" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
|
|
INFO: [Synth 8-5545] ROM "running" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
|
|
INFO: [Synth 8-5545] ROM "dataReady" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
|
|
INFO: [Synth 8-4471] merging register 'index_reg[10:0]' into 'index_reg[10:0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:74]
|
|
INFO: [Synth 8-5544] ROM "writeEnable" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
|
INFO: [Synth 8-5546] ROM "writeEnable" won't be mapped to RAM because it is too sparse
|
|
WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[10]
|
|
WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[9]
|
|
WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[8]
|
|
WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[7]
|
|
WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[6]
|
|
WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[5]
|
|
WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[4]
|
|
WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[3]
|
|
WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[2]
|
|
WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[1]
|
|
WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[0]
|
|
WARNING: [Synth 8-3331] design updateSnake has unconnected port clk_lente
|
|
WARNING: [Synth 8-3331] design Gene_Snake has unconnected port currentSnakes[0][dirX][0]
|
|
WARNING: [Synth 8-3331] design Gene_Snake has unconnected port currentSnakes[1][dirX][0]
|
|
WARNING: [Synth 8-3331] design Gene_Snake has unconnected port currentSnakes[2][dirX][0]
|
|
WARNING: [Synth 8-3331] design Gene_Snake has unconnected port currentSnakes[3][dirX][0]
|
|
WARNING: [Synth 8-3331] design Gene_Snake has unconnected port currentSnakes[4][dirX][0]
|
|
WARNING: [Synth 8-3331] design Gene_Snake has unconnected port currentSnakes[5][dirX][0]
|
|
WARNING: [Synth 8-3331] design Gene_Snake has unconnected port currentSnakes[6][dirX][0]
|
|
WARNING: [Synth 8-3331] design Gene_Snake has unconnected port currentSnakes[7][dirX][0]
|
|
WARNING: [Synth 8-3331] design Gene_Snake has unconnected port currentSnakes[8][dirX][0]
|
|
WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[9]
|
|
WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[8]
|
|
WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[7]
|
|
WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[6]
|
|
WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[5]
|
|
WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[4]
|
|
WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[3]
|
|
WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[2]
|
|
WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[1]
|
|
WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[0]
|
|
WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[8]
|
|
WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[7]
|
|
WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[6]
|
|
WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[5]
|
|
WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[4]
|
|
WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[3]
|
|
WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[2]
|
|
WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[1]
|
|
WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[0]
|
|
WARNING: [Synth 8-3331] design VGA_top has unconnected port led[3]
|
|
INFO: [Synth 8-3971] The signal SNAKE_RAM/mem_reg was recognized as a true dual port RAM template.
|
|
INFO: [Synth 8-4652] Swapped enable and write-enable on 16 RAM instances of RAM SNAKE_RAM/mem_reg to conserve power
|
|
INFO: [Synth 8-3971] The signal MAT_RAM/mem_reg was recognized as a true dual port RAM template.
|
|
INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM MAT_RAM/mem_reg to conserve power
|
|
INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[X][2]' (LD) to 'UPD/currentSnake_reg[X][9]'
|
|
INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[X][3]' (LD) to 'UPD/currentSnake_reg[Y][3]'
|
|
INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[isDefined]' (LD) to 'UPD/currentSnake_reg[dirX][0]'
|
|
INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[dirX][0]' (LD) to 'UPD/currentSnake_reg[dirX][1]'
|
|
INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[Y][0]' (LD) to 'UPD/currentSnake_reg[X][9]'
|
|
INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[Y][1]' (LD) to 'UPD/currentSnake_reg[X][9]'
|
|
INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[Y][2]' (LD) to 'UPD/currentSnake_reg[X][9]'
|
|
INFO: [Synth 8-3333] propagating constant 1 across sequential element (UPD/\currentSnake_reg[Y][3] )
|
|
INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[Y][4]' (LD) to 'UPD/currentSnake_reg[X][9]'
|
|
INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[Y][5]' (LD) to 'UPD/currentSnake_reg[X][9]'
|
|
INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[Y][6]' (LD) to 'UPD/currentSnake_reg[X][9]'
|
|
INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[Y][7]' (LD) to 'UPD/currentSnake_reg[X][9]'
|
|
INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[Y][8]' (LD) to 'UPD/currentSnake_reg[X][9]'
|
|
INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[X][0]' (LD) to 'UPD/currentSnake_reg[X][9]'
|
|
INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[X][1]' (LD) to 'UPD/currentSnake_reg[X][9]'
|
|
INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[X][8]' (LD) to 'UPD/currentSnake_reg[X][9]'
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (UPD/\currentSnake_reg[X][9] )
|
|
INFO: [Synth 8-3886] merging instance 'ROM/data_reg[8]' (FD) to 'ROM/data_reg[9]'
|
|
INFO: [Synth 8-3886] merging instance 'ROM/data_reg[11]' (FD) to 'ROM/data_reg[12]'
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (ROM/\data_reg[12] )
|
|
INFO: [Synth 8-3886] merging instance 'ROM/data_reg[2]' (FD) to 'ROM/data_reg[3]'
|
|
INFO: [Synth 8-3886] merging instance 'ROM/data_reg[19]' (FD) to 'ROM/data_reg[20]'
|
|
INFO: [Synth 8-3886] merging instance 'ROM/data_reg[3]' (FD) to 'ROM/data_reg[4]'
|
|
INFO: [Synth 8-3886] merging instance 'ROM/data_reg[4]' (FD) to 'ROM/data_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'ROM/data_reg[5]' (FD) to 'ROM/data_reg[6]'
|
|
INFO: [Synth 8-3886] merging instance 'ROM/data_reg[6]' (FD) to 'ROM/data_reg[7]'
|
|
INFO: [Synth 8-3886] merging instance 'SNAKE/snakeColor_reg[B][0]' (FDC) to 'SNAKE/snakeColor_reg[B][1]'
|
|
INFO: [Synth 8-3886] merging instance 'SNAKE/snakeColor_reg[A][2]' (FDC) to 'SNAKE/snakeColor_reg[A][3]'
|
|
INFO: [Synth 8-3886] merging instance 'SNAKE/snakeColor_reg[R][0]' (FDC) to 'SNAKE/snakeColor_reg[R][1]'
|
|
INFO: [Synth 8-3886] merging instance 'SNAKE/snakeColor_reg[A][3]' (FDC) to 'SNAKE/snakeColor_reg[A][4]'
|
|
INFO: [Synth 8-3886] merging instance 'SNAKE/snakeColor_reg[A][4]' (FDC) to 'SNAKE/snakeColor_reg[A][5]'
|
|
INFO: [Synth 8-3886] merging instance 'SNAKE/snakeColor_reg[A][5]' (FDC) to 'SNAKE/snakeColor_reg[A][6]'
|
|
INFO: [Synth 8-3886] merging instance 'SNAKE/snakeColor_reg[A][6]' (FDC) to 'SNAKE/snakeColor_reg[A][7]'
|
|
WARNING: [Synth 8-3332] Sequential element (currentSnake_reg[Y][3]) is unused and will be removed from module updateSnake.
|
|
WARNING: [Synth 8-3332] Sequential element (currentSnake_reg[X][9]) is unused and will be removed from module updateSnake.
|
|
---------------------------------------------------------------------------------
|
|
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:33 . Memory (MB): peak = 876.688 ; gain = 502.641
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start ROM, RAM, DSP and Shift Register Reporting
|
|
---------------------------------------------------------------------------------
|
|
|
|
Block RAM: Preliminary Mapping Report (see note below)
|
|
-------NONE-------
|
|
Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once.
|
|
---------------------------------------------------------------------------------
|
|
Finished ROM, RAM, DSP and Shift Register Reporting
|
|
---------------------------------------------------------------------------------
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_2_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_2_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_4_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_4_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_5_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_5_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_6_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_6_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_7_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_7_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_8_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_8_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_9_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_9_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM MAT_RAM/mem_reg to conserve power
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_2/MAT_RAM/mem_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_2/MAT_RAM/mem_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_2/MAT_RAM/mem_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_2/MAT_RAM/mem_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_2/MAT_RAM/mem_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_2/MAT_RAM/mem_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_2/MAT_RAM/mem_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_2/MAT_RAM/mem_reg_8 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_2/MAT_RAM/mem_reg_9 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
|
|
Report RTL Partitions:
|
|
+-+--------------+------------+----------+
|
|
| |RTL Partition |Replication |Instances |
|
|
+-+--------------+------------+----------+
|
|
+-+--------------+------------+----------+
|
|
---------------------------------------------------------------------------------
|
|
Start Applying XDC Timing Constraints
|
|
---------------------------------------------------------------------------------
|
|
INFO: [Synth 8-5578] Moved timing constraint from pin 'U0/clk_out1' to pin 'U0/bbstub_clk_out1/O'
|
|
INFO: [Synth 8-5819] Moved 1 constraints on hierarchical pins to their respective driving/loading pins
|
|
---------------------------------------------------------------------------------
|
|
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:26 ; elapsed = 00:00:39 . Memory (MB): peak = 876.688 ; gain = 502.641
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Timing Optimization
|
|
---------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3971] The signal SNAKE_RAM/mem_reg was recognized as a true dual port RAM template.
|
|
---------------------------------------------------------------------------------
|
|
Finished Timing Optimization : Time (s): cpu = 00:00:30 ; elapsed = 00:00:43 . Memory (MB): peak = 976.145 ; gain = 602.098
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start ROM, RAM, DSP and Shift Register Reporting
|
|
---------------------------------------------------------------------------------
|
|
|
|
Block RAM: Final Mapping Report
|
|
-------NONE-------
|
|
---------------------------------------------------------------------------------
|
|
Finished ROM, RAM, DSP and Shift Register Reporting
|
|
---------------------------------------------------------------------------------
|
|
|
|
Report RTL Partitions:
|
|
+-+--------------+------------+----------+
|
|
| |RTL Partition |Replication |Instances |
|
|
+-+--------------+------------+----------+
|
|
+-+--------------+------------+----------+
|
|
---------------------------------------------------------------------------------
|
|
Start Technology Mapping
|
|
---------------------------------------------------------------------------------
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_2_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_2_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_4_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_4_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_5_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_5_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_6_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_6_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_7_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_7_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_8_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_8_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_9_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_9_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/MAT_RAM/mem_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/MAT_RAM/mem_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/MAT_RAM/mem_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/MAT_RAM/mem_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/MAT_RAM/mem_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/MAT_RAM/mem_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/MAT_RAM/mem_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/MAT_RAM/mem_reg_8 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-6837] The timing for the instance RAMCTRL/MAT_RAM/mem_reg_9 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
|
---------------------------------------------------------------------------------
|
|
Finished Technology Mapping : Time (s): cpu = 00:00:31 ; elapsed = 00:00:44 . Memory (MB): peak = 976.145 ; gain = 602.098
|
|
---------------------------------------------------------------------------------
|
|
|
|
Report RTL Partitions:
|
|
+-+--------------+------------+----------+
|
|
| |RTL Partition |Replication |Instances |
|
|
+-+--------------+------------+----------+
|
|
+-+--------------+------------+----------+
|
|
---------------------------------------------------------------------------------
|
|
Start IO Insertion
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Flattening Before IO Insertion
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Flattening Before IO Insertion
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Final Netlist Cleanup
|
|
---------------------------------------------------------------------------------
|
|
INFO: [Synth 8-6064] Net led[1] is driving 54 big block pins (URAM, BRAM and DSP loads). Created 6 replicas of its driver.
|
|
---------------------------------------------------------------------------------
|
|
Finished Final Netlist Cleanup
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished IO Insertion : Time (s): cpu = 00:00:32 ; elapsed = 00:00:45 . Memory (MB): peak = 976.145 ; gain = 602.098
|
|
---------------------------------------------------------------------------------
|
|
|
|
Report Check Netlist:
|
|
+------+------------------+-------+---------+-------+------------------+
|
|
| |Item |Errors |Warnings |Status |Description |
|
|
+------+------------------+-------+---------+-------+------------------+
|
|
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
|
+------+------------------+-------+---------+-------+------------------+
|
|
---------------------------------------------------------------------------------
|
|
Start Renaming Generated Instances
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Renaming Generated Instances : Time (s): cpu = 00:00:32 ; elapsed = 00:00:45 . Memory (MB): peak = 976.145 ; gain = 602.098
|
|
---------------------------------------------------------------------------------
|
|
|
|
Report RTL Partitions:
|
|
+-+--------------+------------+----------+
|
|
| |RTL Partition |Replication |Instances |
|
|
+-+--------------+------------+----------+
|
|
+-+--------------+------------+----------+
|
|
---------------------------------------------------------------------------------
|
|
Start Rebuilding User Hierarchy
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:32 ; elapsed = 00:00:45 . Memory (MB): peak = 976.145 ; gain = 602.098
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Renaming Generated Ports
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Renaming Generated Ports : Time (s): cpu = 00:00:32 ; elapsed = 00:00:45 . Memory (MB): peak = 976.145 ; gain = 602.098
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Handling Custom Attributes
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Handling Custom Attributes : Time (s): cpu = 00:00:32 ; elapsed = 00:00:45 . Memory (MB): peak = 976.145 ; gain = 602.098
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Renaming Generated Nets
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Renaming Generated Nets : Time (s): cpu = 00:00:32 ; elapsed = 00:00:45 . Memory (MB): peak = 976.145 ; gain = 602.098
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Writing Synthesis Report
|
|
---------------------------------------------------------------------------------
|
|
|
|
Report BlackBoxes:
|
|
+------+--------------+----------+
|
|
| |BlackBox name |Instances |
|
|
+------+--------------+----------+
|
|
|1 |clk_wiz_0 | 1|
|
|
+------+--------------+----------+
|
|
|
|
Report Cell Usage:
|
|
+------+-----------------+------+
|
|
| |Cell |Count |
|
|
+------+-----------------+------+
|
|
|1 |clk_wiz_0_bbox_0 | 1|
|
|
|2 |CARRY4 | 266|
|
|
|3 |LUT1 | 12|
|
|
|4 |LUT2 | 275|
|
|
|5 |LUT3 | 323|
|
|
|6 |LUT4 | 365|
|
|
|7 |LUT5 | 358|
|
|
|8 |LUT6 | 447|
|
|
|9 |MUXF7 | 19|
|
|
|10 |MUXF8 | 1|
|
|
|11 |RAMB18E1_1 | 9|
|
|
|12 |RAMB36E1 | 9|
|
|
|13 |RAMB36E1_1 | 9|
|
|
|14 |FDCE | 62|
|
|
|15 |FDPE | 10|
|
|
|16 |FDRE | 114|
|
|
|17 |FDSE | 1|
|
|
|18 |LD | 17|
|
|
|19 |LDC | 6|
|
|
|20 |IBUF | 1|
|
|
|21 |OBUF | 21|
|
|
|22 |OBUFT | 1|
|
|
+------+-----------------+------+
|
|
|
|
Report Instance Areas:
|
|
+------+--------------+-------------------------+------+
|
|
| |Instance |Module |Cells |
|
|
+------+--------------+-------------------------+------+
|
|
|1 |top | | 2327|
|
|
|2 | ROM |spritesRom | 13|
|
|
|3 | RAMCTRL |RAMController | 1346|
|
|
|4 | MAT_RAM |snakeRam__parameterized1 | 9|
|
|
|5 | SNAKE_RAM |snakeRam | 1282|
|
|
|6 | SNAKE |Gene_Snake | 375|
|
|
|7 | SYNC |GeneSync | 344|
|
|
|8 | UPD |updateSnake | 155|
|
|
|9 | UPD_CLK_DIV |Diviseur | 70|
|
|
+------+--------------+-------------------------+------+
|
|
---------------------------------------------------------------------------------
|
|
Finished Writing Synthesis Report : Time (s): cpu = 00:00:32 ; elapsed = 00:00:45 . Memory (MB): peak = 976.145 ; gain = 602.098
|
|
---------------------------------------------------------------------------------
|
|
Synthesis finished with 0 errors, 0 critical warnings and 49 warnings.
|
|
Synthesis Optimization Runtime : Time (s): cpu = 00:00:25 ; elapsed = 00:00:28 . Memory (MB): peak = 976.145 ; gain = 253.500
|
|
Synthesis Optimization Complete : Time (s): cpu = 00:00:32 ; elapsed = 00:00:45 . Memory (MB): peak = 976.145 ; gain = 602.098
|
|
INFO: [Project 1-571] Translating synthesized netlist
|
|
INFO: [Netlist 29-17] Analyzing 336 Unisim elements for replacement
|
|
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
|
INFO: [Project 1-570] Preparing netlist for logic optimization
|
|
INFO: [Opt 31-140] Inserted 1 IBUFs to IO ports without IO buffers.
|
|
INFO: [Opt 31-138] Pushed 1 inverter(s) to 17 load pin(s).
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 976.145 ; gain = 0.000
|
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
|
A total of 23 instances were transformed.
|
|
LD => LDCE (inverted pins: G): 17 instances
|
|
LDC => LDCE: 6 instances
|
|
|
|
INFO: [Common 17-83] Releasing license: Synthesis
|
|
209 Infos, 94 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|
synth_design completed successfully
|
|
synth_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:48 . Memory (MB): peak = 976.145 ; gain = 613.590
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 976.145 ; gain = 0.000
|
|
WARNING: [Constraints 18-5210] No constraints selected for write.
|
|
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
|
INFO: [Common 17-1381] The checkpoint 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/synth_1/VGA_top.dcp' has been generated.
|
|
INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_synth.rpt -pb VGA_top_utilization_synth.pb
|
|
INFO: [Common 17-206] Exiting Vivado at Tue Jan 4 12:18:30 2022...
|