n_INIT mux

ReceptionTrame_lib/receptionTrame_op.vhd

@@ -5,7 +5,8 @@ USE ieee.numeric_std.all;
 
 ENTITY receptionTrame_op IS
   GENERIC(
-    N: integer := 1200
+    N: integer := 1200;
+    N_WIDTH : integer := 0
   );
   PORT(
     H: IN std_logic;
@@ -44,16 +45,28 @@ SIGNAL LinSynchro_int : std_logic;
 SIGNAL octetRecu_int : std_logic_vector(7 downto 0);
 SIGNAL nbDataField_INIT_int : integer := 0;
 SIGNAL nbDataField_INIT : unsigned(2 downto 0);
+SIGNAL n_INIT : unsigned(n_WIDTH - 1 downto 0);
 
 COMPONENT D_FF
   PORT(
     H: IN std_logic;
+    H_EN: IN std_logic;
     D: IN std_logic;
     nRst: IN std_logic;
     Q: OUT std_logic
   );
 END COMPONENT;
 
+COMPONENT D_FF_BANK IS
+  PORT(
+    H: IN std_logic;
+    H_EN: IN std_logic;
+    nRst : IN std_logic;
+    D: IN std_logic_vector;
+    Q: OUT std_logic_vector
+  );
+END COMPONENT;
+
 COMPONENT shift_register
   GENERIC (
     WIDTH: integer
@@ -93,6 +106,7 @@ octetRecu <= octetRecu_int;
 Lin_in_sync : D_FF
   PORT MAP(
     H => H,
+    H_EN => '1',
     D => Lin,
     nRst => nCLR,
     Q => LinSynchro_int
@@ -139,4 +153,21 @@ nbDataField_cmp : counter
     max => nbData_0
   );
 
+-- Identifier register
+idReg : D_FF_BANK
+  PORT MAP(
+    H => H,
+    H_EN => identifier_EN,
+    nRst => nClr,
+    D => octetRecu_int(5 downto 0),
+    Q => identifier
+  );
+
+-- n_INIT mux
+WITH n_SELECT SELECT
+  n_INIT <= 
+    to_unsigned(N - 1, N_WIDTH) when '0',
+    to_unsigned(N / 2, N_WIDTH) when '1',
+    (others => '0') when others;
+  
 END ARCHITECTURE arch;

STDLIB_lib/D_FF.vhd

@@ -5,6 +5,7 @@ USE ieee.std_logic_arith.all;
 ENTITY D_FF IS
   PORT(
     H: IN std_logic;
+    H_EN: IN std_logic;
     D: IN std_logic;
     nRst: IN std_logic;
     Q: OUT std_logic
@@ -17,7 +18,7 @@ dff: PROCESS(H, nRst)
 BEGIN
   if(nRst = '0') THEN
     Q <= '0';
-  ELSIF(rising_edge(H)) THEN
+  ELSIF(rising_edge(H) and H_EN = '1') THEN
     Q <= D;
   END IF;
 END PROCESS dff;

STDLIB_lib/D_FF_bank.vhd

@@ -5,6 +5,7 @@ USE ieee.std_logic_arith.all;
 ENTITY D_FF_BANK IS
   PORT(
     H: IN std_logic;
+    H_EN: IN std_logic;
     nRst : IN std_logic;
     D: IN std_logic_vector;
     Q: OUT std_logic_vector
@@ -15,6 +16,7 @@ ARCHITECTURE arch OF D_FF_BANK IS
 COMPONENT D_FF
   PORT(
     H: IN std_logic;
+    H_EN: IN std_logic;
     D: IN std_logic;
     nRst: IN std_logic;
     Q: OUT std_logic
@@ -26,6 +28,7 @@ BEGIN
 bank_generate : for i in D'RANGE generate
   DFF_X : D_FF port map(
     H => H,
+    H_EN => H_EN,
     D => D(i),
     nRst => nRst,
     Q => Q(i)

STDLIB_lib/stdlib_tb.vhd

@@ -32,6 +32,7 @@ SIGNAL CNT_max : std_logic;
 COMPONENT D_FF
   PORT(
     H: IN std_logic;
+    H_EN: IN std_logic;
     D: IN std_logic;
     nRst: IN std_logic;
     Q: OUT std_logic
@@ -41,6 +42,7 @@ END COMPONENT;
 COMPONENT D_FF_BANK
   PORT(
     H: IN std_logic;
+    H_EN: IN std_logic;
     D: IN std_logic_vector;
     nRst: IN std_logic;
     Q: OUT std_logic_vector
@@ -174,6 +176,7 @@ END PROCESS CNT_test;
 U0 : D_FF
   PORT MAP (
     H => CLK,
+    H_EN => '1',
     D => D_FF_D,
     nRst => D_FF_Rst,
     Q => D_FF_Q
@@ -182,6 +185,7 @@ U0 : D_FF
 U1 : D_FF_BANK
   PORT MAP(
     H => CLK,
+    H_EN => '1',
     D => D_FFb_D,
     nRst => D_FFb_Rst,
     Q => D_FFb_Q