counter

ReceptionTrame_lib/receptionTrame_op.vhd

@@ -100,4 +100,6 @@ WITH octetRecu_int(5 downto 4) SELECT
     7 when "11",
     0 when others;
 
+-- nbDataField counter
+
 END ARCHITECTURE arch;

STDLIB_lib/STDLIB_lib.core

@@ -8,6 +8,7 @@ filesets:
       - D_FF.vhd
       - D_FF_bank.vhd
       - shift_register.vhd
+      - counter.vhd
     file_type: vhdlSource
 
   tb:
@@ -33,7 +34,6 @@ targets:
       ghdl:
         analyze_options:
           - -fsynopsys
-          - --std=08
         run_options:
           - --wave=waveform.ghw --stop-time=2us
     parameters:

STDLIB_lib/counter.vhd

@@ -0,0 +1,47 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+ENTITY counter IS
+  GENERIC(
+    WIDTH: integer;
+    MAX_VAL: integer
+  );
+  PORT(
+    H: IN std_logic;
+    H_EN: IN std_logic;
+    nRst: IN std_logic;
+    INIT: IN unsigned(WIDTH-1 downto 0);
+    LOAD: IN std_logic;
+    upnDown: IN std_logic;
+
+    val: OUT unsigned(WIDTH-1 downto 0);
+    max: OUT std_logic
+  );
+END counter;
+
+ARCHITECTURE arch OF counter IS
+SIGNAL cmp: unsigned(WIDTH-1 downto 0);
+BEGIN
+
+val <= cmp;
+max <= '1' when cmp = MAX_VAL else '0';
+
+main : PROCESS(H, nRst)
+BEGIN
+  if(nRst = '0') then
+    cmp <= to_unsigned(0, WIDTH);
+  elsif(rising_edge(H)) then
+    if(LOAD = '1') then
+      cmp <= INIT;
+    elsif(cmp /= MAX_VAL) then
+      if(upnDown = '1') then
+        cmp <= cmp + 1;
+      else
+        cmp <= cmp - 1;
+      end if;
+    end if;
+  end if;
+END PROCESS main;
+
+END ARCHITECTURE arch;

STDLIB_lib/stdlib_tb.vhd

@@ -1,6 +1,7 @@
 LIBRARY ieee;
 USE ieee.std_logic_1164.all;
-USE ieee.std_logic_arith.all;
+-- USE ieee.std_logic_arith.all;
+use IEEE.NUMERIC_STD.all;
 
 ENTITY stdlib_tb IS
   GENERIC(
@@ -23,6 +24,11 @@ SIGNAL SR_D : std_logic;
 SIGNAL SR_Rst : std_logic;
 SIGNAL SR_Q : std_logic_vector(7 downto 0);
 
+SIGNAL CNT_Rst : std_logic;
+SIGNAL CNT_INIT : unsigned(2 downto 0);
+SIGNAL CNT_LOAD : std_logic;
+SIGNAL CNT_max : std_logic;
+
 COMPONENT D_FF
   PORT(
     H: IN std_logic;
@@ -54,6 +60,24 @@ COMPONENT shift_register
   );
 END COMPONENT;
 
+COMPONENT counter
+  GENERIC(
+    WIDTH: integer;
+    MAX_VAL: integer
+  );
+  PORT(
+    H: IN std_logic;
+    H_EN: IN std_logic;
+    nRst: IN std_logic;
+    INIT: IN unsigned(WIDTH-1 downto 0);
+    LOAD: IN std_logic;
+    upnDown: IN std_logic;
+
+    val: OUT unsigned(WIDTH-1 downto 0);
+    max: OUT std_logic
+  );
+END COMPONENT;
+
 BEGIN
 
 CLK_gen : PROCESS
@@ -121,6 +145,32 @@ BEGIN
   assert SR_Q = "00000000" report "shft register reset error" severity error;
 END PROCESS SR_test;
 
+CNT_test : PROCESS
+BEGIN
+  CNT_Rst <= '0';
+  CNT_INIT <= to_unsigned(7, 3);
+  
+  WAIT UNTIL CLK = '1';
+  CNT_Rst <= '1';
+  
+  WAIT UNTIL CLK = '1';
+  assert CNT_max = '1' report "counter reset error" severity error;
+  CNT_LOAD <= '1';
+  
+  WAIT UNTIL CLK = '1';
+  WAIT UNTIL CLK = '0';
+  CNT_LOAD <= '0';
+  WAIT UNTIL CLK = '1';
+
+  for i in 6 downto 0 loop
+    assert CNT_max = '0' report "counter count down error" severity error;
+    WAIT UNTIL CLK = '1';
+  end loop;
+
+  assert CNT_max = '1' report "counter count down to zero error" severity error;
+  
+END PROCESS CNT_test;
+
 U0 : D_FF
   PORT MAP (
     H => CLK,
@@ -149,4 +199,20 @@ U2 : shift_register
     Q => SR_Q
   );
 
+U3 : counter
+  GENERIC MAP(
+    WIDTH => 3,
+    MAX_VAL => 0
+  )
+  PORT MAP(
+    H => CLK,
+    H_EN => '1',
+    nRst => CNT_Rst,
+    INIT => CNT_INIT,
+    LOAD => CNT_LOAD,
+    upnDown => '0',
+    val => OPEN,
+    max => CNT_max
+  );
+
 END ARCHITECTURE arch;