290 lines
9.2 KiB
VHDL
290 lines
9.2 KiB
VHDL
-- VHDL Entity RecepteurLIN_lib.RecepteurLIN.symbol
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--
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-- Created:
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-- by - e208835u.UNKNOWN (irb013-09)
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-- at - 12:48:09 17/10/2023
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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ENTITY RecepteurLIN IS
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PORT(
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CnD : IN std_logic;
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H : IN std_logic;
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LIN : IN std_logic;
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RnW : IN std_logic;
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nCLR : IN std_logic;
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nCS : IN std_logic;
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M_Received : OUT std_logic;
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D07 : INOUT std_logic_vector (7 DOWNTO 0)
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);
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-- Declarations
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END RecepteurLIN ;
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--
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-- VHDL Architecture RecepteurLIN_lib.RecepteurLIN.struct
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--
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-- Created:
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-- by - e208835u.UNKNOWN (irb013-09)
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-- at - 12:48:09 17/10/2023
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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-- LIBRARY RecepteurLIN_lib;
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ARCHITECTURE struct OF RecepteurLIN IS
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-- Architecture declarations
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-- Internal signal declarations
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SIGNAL Errors_SET : std_logic_vector(3 DOWNTO 1);
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SIGNAL EtatLu : std_logic_vector(7 DOWNTO 0);
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SIGNAL EtatLu_RST : std_logic;
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SIGNAL MessageReceived_SET : std_logic;
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SIGNAL NbByteDec : std_logic;
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SIGNAL NbByteInc : std_logic;
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SIGNAL NbRecByte_RST : std_logic;
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SIGNAL RecByte : std_logic_vector(7 DOWNTO 0);
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SIGNAL RecByte_RST : std_logic;
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SIGNAL RecByte_WR : std_logic;
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SIGNAL SelAdr : std_logic_vector(7 DOWNTO 0);
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SIGNAL dout : std_logic;
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SIGNAL ffout : std_logic_vector(7 DOWNTO 0);
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SIGNAL rena : std_logic;
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-- ModuleWare signal declarations(v1.12) for instance 'U_1' of 'fifo'
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TYPE mw_U_1sreg IS ARRAY (11 DOWNTO 0) OF std_logic_vector(7 DOWNTO 0);
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SIGNAL mw_U_1addr_cval : INTEGER RANGE 0 TO 11;
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SIGNAL mw_U_1addr_nval : INTEGER RANGE 0 TO 11;
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SIGNAL mw_U_1reg_cval : mw_U_1sreg;
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SIGNAL mw_U_1reg_nval : mw_U_1sreg;
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-- Component Declarations
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COMPONENT FrameReception
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PORT (
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H : IN std_logic ;
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Lin : IN std_logic ;
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SelAdr : IN std_logic_vector (7 DOWNTO 0);
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nRST : IN std_logic ;
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ErrorSet : OUT std_logic_vector (3 DOWNTO 1);
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MsgRcv_SET : OUT std_logic ;
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NbRecByte_Inc : OUT std_logic ;
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RecByte : OUT std_logic_vector (7 DOWNTO 0);
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RecByte_RST : OUT std_logic ;
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RecByte_WR : OUT std_logic
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);
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END COMPONENT;
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COMPONENT InterfaceMicroprocesseur
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PORT (
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CnD : IN std_logic ;
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EtatLu : IN std_logic_vector (7 DOWNTO 0);
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H : IN std_logic ;
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OctetLu : IN std_logic_vector (7 DOWNTO 0);
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RnW : IN std_logic ;
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nCS : IN std_logic ;
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nRST : IN std_logic ;
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DecNbOctet : OUT std_logic ;
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EtatLu_RST : OUT std_logic ;
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M_Received : OUT std_logic ;
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OctetLu_RD : OUT std_logic ;
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SelAdr : OUT std_logic_vector (7 DOWNTO 0);
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D07 : INOUT std_logic_vector (7 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT InternalState
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PORT (
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Errors_SET : IN std_logic_vector (3 DOWNTO 1);
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EtatLu_RST : IN std_logic ;
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H : IN std_logic ;
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MessageReceived_SET : IN std_logic ;
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NbByteDec : IN std_logic ;
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NbByteInc : IN std_logic ;
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NbRecByte_RST : IN std_logic ;
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nCLR : IN std_logic ;
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EtatLu : OUT std_logic_vector (7 DOWNTO 0)
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);
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END COMPONENT;
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-- Optional embedded configurations
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-- pragma synthesis_off
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-- FOR ALL : FrameReception USE ENTITY RecepteurLIN_lib.FrameReception;
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-- FOR ALL : InterfaceMicroprocesseur USE ENTITY RecepteurLIN_lib.InterfaceMicroprocesseur;
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-- FOR ALL : InternalState USE ENTITY RecepteurLIN_lib.InternalState;
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-- pragma synthesis_on
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BEGIN
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-- ModuleWare code(v1.12) for instance 'U_1' of 'fifo'
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ffout <= mw_U_1reg_cval(0);
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u_1seq1_proc: PROCESS (H)
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BEGIN
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IF (H'EVENT AND H='1') THEN
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FOR i IN 0 TO 11 LOOP
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mw_U_1reg_cval(i)(7 DOWNTO 0) <= mw_U_1reg_nval(i)(7 DOWNTO 0);
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END LOOP;
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END IF;
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END PROCESS u_1seq1_proc;
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u_1seq2_proc: PROCESS (H, dout)
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BEGIN
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IF (dout = '1') THEN
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mw_U_1addr_cval <= 0;
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ELSIF (H'EVENT AND H='1') THEN
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mw_U_1addr_cval <= mw_U_1addr_nval;
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END IF;
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END PROCESS u_1seq2_proc;
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u_1combo_proc: PROCESS (dout, rena, RecByte_WR, mw_U_1addr_cval, mw_U_1reg_cval, RecByte)
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VARIABLE temp_rena : std_logic;
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VARIABLE temp_wena : std_logic;
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VARIABLE temp_full : std_logic;
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VARIABLE temp_empty : std_logic;
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BEGIN
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IF (mw_U_1addr_cval = 11) THEN
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temp_full := '1';
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temp_empty := '0';
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ELSIF (mw_U_1addr_cval = 0) THEN
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temp_full := '0';
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temp_empty := '1';
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ELSE
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temp_full := '0';
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temp_empty := '0';
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END IF;
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temp_rena := NOT(dout) AND rena AND NOT(temp_empty);
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temp_wena := NOT(dout) AND RecByte_WR AND NOT(temp_full);
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IF (temp_wena = '1') THEN
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mw_U_1addr_nval <= mw_U_1addr_cval + 1;
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ELSIF (temp_rena = '1') THEN
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mw_U_1addr_nval <= mw_U_1addr_cval - 1;
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ELSE
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mw_U_1addr_nval <= mw_U_1addr_cval;
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END IF;
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IF (temp_wena = '1') THEN
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mw_U_1reg_nval(0)(7 DOWNTO 0) <= mw_U_1reg_cval(0)(7 DOWNTO 0);
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FOR i IN 0 TO 10 LOOP
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IF (mw_U_1addr_cval = i) THEN
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mw_U_1reg_nval(i+1)(7 DOWNTO 0) <= RecByte;
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ELSE
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mw_U_1reg_nval(i+1)(7 DOWNTO 0) <= mw_U_1reg_cval(i+1)(7 DOWNTO 0);
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END IF;
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END LOOP;
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ELSIF (temp_wena = '0') THEN
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IF (temp_rena = '1') THEN
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FOR i IN 0 TO 10 LOOP
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mw_U_1reg_nval(i)(7 DOWNTO 0) <= mw_U_1reg_cval(i+1)(7 DOWNTO 0);
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END LOOP;
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mw_U_1reg_nval(11)(7 DOWNTO 0) <= mw_U_1reg_cval(11)(7 DOWNTO 0);
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ELSIF (temp_rena = '0') THEN
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FOR i IN 0 TO 11 LOOP
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mw_U_1reg_nval(i)(7 DOWNTO 0) <= mw_U_1reg_cval(i)(7 DOWNTO 0);
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END LOOP;
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ELSE
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FOR i IN 0 TO 11 LOOP
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mw_U_1reg_nval(i)(7 DOWNTO 0) <= (OTHERS => 'X');
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END LOOP;
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END IF;
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ELSE
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FOR i IN 0 TO 11 LOOP
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mw_U_1reg_nval(i)(7 DOWNTO 0) <= (OTHERS => 'X');
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END LOOP;
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END IF;
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END PROCESS u_1combo_proc;
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-- ModuleWare code(v1.12) for instance 'U_4' of 'pbuf'
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u_4seq_proc: PROCESS (RecByte_RST)
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BEGIN
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IF (RecByte_RST ='1' ) THEN
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dout <= '1';
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ELSIF (RecByte_RST ='H' ) THEN
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dout <= '1';
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ELSIF (RecByte_RST ='0' ) THEN
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dout <= '0';
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ELSIF (RecByte_RST ='L' ) THEN
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dout <= '0';
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ELSIF (RecByte_RST ='U' ) THEN
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dout <= 'U';
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ELSIF (RecByte_RST ='X' ) THEN
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dout <= 'X';
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ELSIF (RecByte_RST ='Z' ) THEN
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dout <= 'X';
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END IF;
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END PROCESS u_4seq_proc;
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-- ModuleWare code(v1.12) for instance 'U_5' of 'pbuf'
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u_5seq_proc: PROCESS (RecByte_RST)
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BEGIN
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IF (RecByte_RST ='1' ) THEN
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NbRecByte_RST <= '1';
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ELSIF (RecByte_RST ='H' ) THEN
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NbRecByte_RST <= '1';
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ELSIF (RecByte_RST ='0' ) THEN
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NbRecByte_RST <= '0';
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ELSIF (RecByte_RST ='L' ) THEN
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NbRecByte_RST <= '0';
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ELSIF (RecByte_RST ='U' ) THEN
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NbRecByte_RST <= 'U';
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ELSIF (RecByte_RST ='X' ) THEN
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NbRecByte_RST <= 'X';
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ELSIF (RecByte_RST ='Z' ) THEN
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NbRecByte_RST <= 'X';
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END IF;
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END PROCESS u_5seq_proc;
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-- Instance port mappings.
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FrameRec : FrameReception
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PORT MAP (
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H => H,
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Lin => LIN,
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SelAdr => SelAdr,
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nRST => nCLR,
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ErrorSet => Errors_SET,
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MsgRcv_SET => MessageReceived_SET,
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NbRecByte_Inc => NbByteInc,
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RecByte => RecByte,
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RecByte_RST => RecByte_RST,
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RecByte_WR => RecByte_WR
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);
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IntuP : InterfaceMicroprocesseur
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PORT MAP (
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CnD => CnD,
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EtatLu => EtatLu,
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H => H,
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OctetLu => ffout,
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RnW => RnW,
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nCS => nCS,
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nRST => nCLR,
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DecNbOctet => NbByteDec,
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EtatLu_RST => EtatLu_RST,
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M_Received => M_Received,
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OctetLu_RD => rena,
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SelAdr => SelAdr,
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D07 => D07
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);
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IntState : InternalState
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PORT MAP (
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Errors_SET => Errors_SET,
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EtatLu_RST => EtatLu_RST,
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H => H,
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MessageReceived_SET => MessageReceived_SET,
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NbByteDec => NbByteDec,
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NbByteInc => NbByteInc,
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NbRecByte_RST => NbRecByte_RST,
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nCLR => nCLR,
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EtatLu => EtatLu
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);
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END struct;
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