51 lines
1.0 KiB
VHDL
51 lines
1.0 KiB
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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ENTITY receptionTrame IS
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PORT(
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H: IN std_logic;
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nCLR: IN std_logic;
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Lin: IN std_logic
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);
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END receptionTrame;
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ARCHITECTURE arch OF receptionTrame IS
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COMPONENT receptionTrame_op
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GENERIC(
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N: integer := 1200;
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N_WIDTH : integer := 11
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);
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PORT(
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H: IN std_logic;
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nCLR: IN std_logic;
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Lin: IN std_logic;
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octetRecu_EN : IN std_logic;
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n_SELECT: IN std_logic;
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n_LOAD: IN std_logic;
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n_EN: IN std_logic;
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nbBit_SELECT: IN std_logic;
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nbBit_LOAD: IN std_logic;
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nbBit_EN: IN std_logic;
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identifier_EN: IN std_logic;
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nbData_LOAD: IN std_logic;
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nbData_EN: IN std_logic;
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LinSynchro: OUT std_logic;
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n_0: OUT std_logic;
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nbBit_0: OUT std_logic;
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nbData_0: OUT std_logic;
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identifier: OUT std_logic_vector(5 downto 0);
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octetRecu: OUT std_logic_vector(7 downto 0)
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);
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END COMPONENT;
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BEGIN
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END ARCHITECTURE arch; |