111 lines
1.9 KiB
VHDL
111 lines
1.9 KiB
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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ENTITY receptionTrame_tb IS
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GENERIC(
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CLOCK_PERIOD: time := 52 us;
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UC_CLK_PERIOD: time := 43 ns
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);
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END receptionTrame_tb;
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ARCHITECTURE arch of receptionTrame_tb IS
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COMPONENT receptionTrame
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PORT(
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H: IN std_logic;
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nCLR: IN std_logic;
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Lin: IN std_logic;
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AdrSel: IN std_logic_vector;
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RecByte: OUT std_logic_vector(7 downto 0);
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RecByte_WR: OUT std_logic;
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RecBytes_RST: OUT std_logic;
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Err_SET: OUT std_logic_vector(2 downto 0);
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NbByteInc: OUT std_logic;
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MsgReceived_SET: OUT std_logic;
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NbRecByte_RST: OUT std_logic
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);
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END COMPONENT;
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SIGNAL H: std_logic;
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SIGNAL Lin: std_logic;
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BEGIN
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clkGen : PROCESS
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BEGIN
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H <= '1';
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WAIT FOR UC_CLK_PERIOD / 2;
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H <= '0';
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WAIT FOR UC_CLK_PERIOD / 2;
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END PROCESS clkGen;
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linFrame : PROCESS
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BEGIN
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Lin <= '1';
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WAIT FOR 100 us;
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-- Sync Break
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Lin <= '0';
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WAIT FOR 14 * CLOCK_PERIOD;
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Lin <= '1';
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WAIT FOR 2 * CLOCK_PERIOD;
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-- Sync field
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for i in 4 downto 0 loop
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Lin <= '0';
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WAIT FOR CLOCK_PERIOD;
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Lin <= '1';
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WAIT FOR CLOCK_PERIOD;
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end loop;
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-- ID field (0x0, 2 data byte)
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Lin <= '0';
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WAIT FOR CLOCK_PERIOD;
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Lin <= '0';
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WAIT FOR 8 * CLOCK_PERIOD;
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Lin <= '1';
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WAIT FOR CLOCK_PERIOD;
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-- data fields (both 0x00)
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Lin <= '0';
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WAIT FOR 9 * CLOCK_PERIOD;
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Lin <= '1';
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WAIT FOR CLOCK_PERIOD;
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Lin <= '0';
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WAIT FOR 9 * CLOCK_PERIOD;
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Lin <= '1';
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WAIT FOR CLOCK_PERIOD;
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-- checksum (0x0)
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Lin <= '0';
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WAIT FOR 9 * CLOCK_PERIOD;
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Lin <= '1';
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WAIT FOR CLOCK_PERIOD;
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report "Finished" severity failure ;
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END PROCESS;
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U0 : receptionTrame
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PORT MAP(
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H => H,
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nCLR => '1',
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Lin => Lin,
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AdrSel => "000000",
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RecByte => OPEN,
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RecByte_WR => OPEN,
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RecBytes_RST => OPEN,
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Err_SET => OPEN,
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NbByteInc => OPEN,
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MsgReceived_SET => OPEN,
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NbRecByte_RST => OPEN
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);
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END ARCHITECTURE arch;
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