137 lines
3.9 KiB
VHDL
137 lines
3.9 KiB
VHDL
-- VHDL Entity RecepteurLIN_lib.InterfaceMicroprocesseur_SousTest.symbol
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--
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-- Created:
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-- by - e208835u.UNKNOWN (irb121-03)
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-- at - 10:37:09 12/09/2023
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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ENTITY InterfaceMicroprocesseur_SousTest IS
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-- Declarations
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END InterfaceMicroprocesseur_SousTest ;
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--
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-- VHDL Architecture RecepteurLIN_lib.InterfaceMicroprocesseur_SousTest.struct
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--
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-- Created:
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-- by - e208835u.UNKNOWN (irb121-03)
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-- at - 10:59:28 12/09/2023
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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-- LIBRARY RecepteurLIN_lib;
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ARCHITECTURE struct OF InterfaceMicroprocesseur_SousTest IS
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-- Architecture declarations
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-- Internal signal declarations
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SIGNAL CnD : std_logic;
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SIGNAL D07 : std_logic_vector(7 DOWNTO 0);
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SIGNAL H : std_logic;
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SIGNAL M_Received : std_logic;
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SIGNAL RnW : std_logic;
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SIGNAL dout : std_logic_vector(7 DOWNTO 0);
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SIGNAL dout1 : std_logic_vector(7 DOWNTO 0);
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SIGNAL nCS : std_logic;
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SIGNAL nRST : std_logic;
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-- Component Declarations
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COMPONENT EnvTest_InterfaceMicroprocesseur
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GENERIC (
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CLOCK_PERIOD : time := 50 ns;
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RESET_OFFSET : time := 500 ns;
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RESET_DURATION : time := 300 ns;
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ACCESS_TIME : time := 40 ns;
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HOLD_TIME : time := 70 ns
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);
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PORT (
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M_Received : IN std_logic ;
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CnD : OUT std_logic ;
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H : OUT std_logic ;
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RnW : OUT std_logic ;
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nCS : OUT std_logic ;
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nRST : OUT std_logic ;
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D07 : INOUT std_logic_vector (7 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT InterfaceMicroprocesseur
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PORT (
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CnD : IN std_logic ;
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EtatLu : IN std_logic_vector (7 DOWNTO 0);
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H : IN std_logic ;
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OctetLu : IN std_logic_vector (7 DOWNTO 0);
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RnW : IN std_logic ;
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nCS : IN std_logic ;
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nRST : IN std_logic ;
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DecNbOctet : OUT std_logic ;
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EtatLu_RST : OUT std_logic ;
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M_Received : OUT std_logic ;
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OctetLu_RD : OUT std_logic ;
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SelAdr : OUT std_logic_vector (7 DOWNTO 0);
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D07 : INOUT std_logic_vector (7 DOWNTO 0)
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);
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END COMPONENT;
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-- Optional embedded configurations
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-- pragma synthesis_off
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-- FOR ALL : EnvTest_InterfaceMicroprocesseur USE ENTITY RecepteurLIN_lib.EnvTest_InterfaceMicroprocesseur;
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-- FOR ALL : InterfaceMicroprocesseur USE ENTITY RecepteurLIN_lib.InterfaceMicroprocesseur;
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-- pragma synthesis_on
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BEGIN
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-- ModuleWare code(v1.12) for instance 'U_2' of 'constval'
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dout <= "00001000";
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-- ModuleWare code(v1.12) for instance 'U_3' of 'constval'
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dout1 <= "00001010";
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-- Instance port mappings.
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U_0 : EnvTest_InterfaceMicroprocesseur
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GENERIC MAP (
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CLOCK_PERIOD => 50 ns,
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RESET_OFFSET => 500 ns,
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RESET_DURATION => 300 ns,
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ACCESS_TIME => 40 ns,
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HOLD_TIME => 70 ns
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)
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PORT MAP (
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M_Received => M_Received,
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CnD => CnD,
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H => H,
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RnW => RnW,
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nCS => nCS,
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nRST => nRST,
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D07 => D07
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);
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U_1 : InterfaceMicroprocesseur
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PORT MAP (
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CnD => CnD,
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EtatLu => dout1,
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H => H,
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OctetLu => dout,
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RnW => RnW,
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nCS => nCS,
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nRST => nRST,
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DecNbOctet => OPEN,
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EtatLu_RST => OPEN,
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M_Received => M_Received,
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OctetLu_RD => OPEN,
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SelAdr => OPEN,
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D07 => D07
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);
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END struct;
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