63 lines
1.5 KiB
VHDL
63 lines
1.5 KiB
VHDL
-- VHDL Entity RecepteurLIN_lib.decoder.interface
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--
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-- Created:
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-- by - e208835u.UNKNOWN (irb121-06)
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-- at - 16:35:13 19/09/2023
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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ENTITY decoder IS
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PORT(
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RecByte : IN std_logic_vector (5 DOWNTO 4);
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DataFieldNb_INIT : OUT std_logic_vector (2 DOWNTO 0)
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);
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-- Declarations
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END decoder ;
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--
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-- VHDL Architecture RecepteurLIN_lib.decoder.tbl
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--
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-- Created:
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-- by - e208835u.UNKNOWN (irb121-06)
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-- at - 16:41:56 19/09/2023
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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ARCHITECTURE tbl OF decoder IS
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-- Architecture declarations
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BEGIN
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-----------------------------------------------------------------
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truth_process_proc: PROCESS(RecByte)
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-----------------------------------------------------------------
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BEGIN
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-- Block 1
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IF (RecByte(5 DOWNTO 4) = "00") THEN
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DataFieldNb_INIT <= "001";
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ELSIF (RecByte(5 DOWNTO 4) = "01") THEN
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DataFieldNb_INIT <= "001";
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ELSIF (RecByte(5 DOWNTO 4) = "10") THEN
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DataFieldNb_INIT <= "011";
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ELSIF (RecByte(5 DOWNTO 4) = "11") THEN
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DataFieldNb_INIT <= "111";
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END IF;
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END PROCESS truth_process_proc;
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-- Architecture concurrent statements
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END tbl;
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