107 lines
2.7 KiB
VHDL
107 lines
2.7 KiB
VHDL
-- VHDL Entity RecepteurLIN_lib.FrameReception_UnderTest.symbol
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--
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-- Created:
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-- by - e208835U.UNKNOWN (irb121-02)
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-- at - 11:35:03 26/09/2023
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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ENTITY FrameReception_UnderTest IS
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-- Declarations
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END FrameReception_UnderTest ;
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--
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-- VHDL Architecture RecepteurLIN_lib.FrameReception_UnderTest.struct
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--
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-- Created:
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-- by - e208835u.UNKNOWN (irb013-09)
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-- at - 10:39:28 10/10/2023
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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-- LIBRARY LIN_Rec_Test_Env_2022_IP;
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-- LIBRARY RecepteurLIN_lib;
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ARCHITECTURE struct OF FrameReception_UnderTest IS
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-- Architecture declarations
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-- Internal signal declarations
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SIGNAL LIN : std_logic;
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SIGNAL M_Received : std_logic;
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SIGNAL Master_Clk : std_logic;
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SIGNAL Reset_bar : std_logic;
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-- Component Declarations
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COMPONENT LIN_Receiver_Env
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GENERIC (
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sur_ech : integer
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);
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PORT (
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M_Received : IN std_logic;
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C_Dbar : OUT std_logic;
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Cs_bar : OUT std_logic;
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LIN : OUT std_logic;
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Master_Clk : OUT std_logic;
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R_Wbar : OUT std_logic;
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Reset_bar : OUT std_logic;
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Data_Bus : INOUT std_logic_vector ( 7 DOWNTO 0 )
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);
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END COMPONENT;
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COMPONENT FrameReception
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PORT (
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H : IN std_logic ;
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Lin : IN std_logic ;
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nRST : IN std_logic ;
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RecByte : OUT std_logic_vector (7 DOWNTO 0);
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RecByte_RST : OUT std_logic ;
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RecByte_WR : OUT std_logic
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);
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END COMPONENT;
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-- Optional embedded configurations
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-- pragma synthesis_off
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-- FOR ALL : FrameReception USE ENTITY RecepteurLIN_lib.FrameReception;
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-- FOR ALL : LIN_Receiver_Env USE ENTITY LIN_Rec_Test_Env_2022_IP.LIN_Receiver_Env;
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-- pragma synthesis_on
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BEGIN
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-- Instance port mappings.
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U_1 : LIN_Receiver_Env
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GENERIC MAP (
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sur_ech => 1024
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)
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PORT MAP (
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M_Received => M_Received,
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C_Dbar => OPEN,
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Cs_bar => OPEN,
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LIN => LIN,
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Master_Clk => Master_Clk,
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R_Wbar => OPEN,
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Reset_bar => Reset_bar,
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Data_Bus => OPEN
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);
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U_0 : FrameReception
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PORT MAP (
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H => Master_Clk,
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Lin => LIN,
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nRST => Reset_bar,
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RecByte => OPEN,
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RecByte_RST => OPEN,
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RecByte_WR => OPEN
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);
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END struct;
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