25 lines
390 B
VHDL
25 lines
390 B
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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ENTITY D_FF IS
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PORT(
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H: IN std_logic;
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D: IN std_logic;
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nRst: IN std_logic;
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Q: OUT std_logic
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);
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END D_FF;
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ARCHITECTURE arch of D_FF IS
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BEGIN
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dff: PROCESS(H, nRst)
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BEGIN
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if(nRst = '0') THEN
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Q <= '0';
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ELSIF(rising_edge(H)) THEN
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Q <= D;
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END IF;
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END PROCESS dff;
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END ARCHITECTURE arch; |