104 lines
1.9 KiB
VHDL
104 lines
1.9 KiB
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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ENTITY stdlib_tb IS
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GENERIC(
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CLOCK_PERIOD : time := 10 ns
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);
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END stdlib_tb;
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ARCHITECTURE arch of stdlib_tb IS
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SIGNAL CLK : std_logic;
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SIGNAL D_FF_D : std_logic;
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SIGNAL D_FF_Rst : std_logic;
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SIGNAL D_FF_Q : std_logic;
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SIGNAL D_FFb_D : std_logic_vector(7 downto 0);
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SIGNAL D_FFb_Rst : std_logic;
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SIGNAL D_FFb_Q : std_logic_vector(7 downto 0);
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COMPONENT D_FF
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PORT(
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H: IN std_logic;
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D: IN std_logic;
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nRst: IN std_logic;
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Q: OUT std_logic
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);
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END COMPONENT;
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COMPONENT D_FF_BANK
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PORT(
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H: IN std_logic;
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D: IN std_logic_vector;
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nRst: IN std_logic;
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Q: OUT std_logic_vector
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);
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END COMPONENT;
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BEGIN
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CLK_gen : PROCESS
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BEGIN
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CLK <= '0';
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WAIT FOR CLOCK_PERIOD/2;
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CLK <= '1';
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WAIT FOR CLOCK_PERIOD/2;
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END PROCESS CLK_gen;
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D_FF_test : PROCESS
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BEGIN
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D_FF_Rst <= '0';
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WAIT UNTIL CLK = '1';
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D_FF_Rst <= '1';
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D_FF_D <= '1';
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WAIT UNTIL CLK = '0';
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assert D_FF_Q = '0' report "D_FF set before clk" severity error;
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WAIT UNTIL CLK = '0';
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assert D_FF_Q = '1' report "D_FF not set" severity error;
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D_FF_Rst <= '0';
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WAIT UNTIL CLK = '0';
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assert D_FF_Q = '0' report "D_FF reset error" severity error;
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END PROCESS D_FF_test;
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D_FFb_test : PROCESS
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BEGIN
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D_FFb_Rst <= '0';
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WAIT UNTIL CLK = '1';
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D_FFb_Rst <= '1';
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D_FFb_D <= "01010101";
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WAIT UNTIL CLK = '0';
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assert D_FFb_Q = "00000000" report "D_FF_bank set before clk" severity error;
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WAIT UNTIL CLK = '0';
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assert D_FFb_Q = "01010101" report "D_FF_bank not set" severity error;
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D_FFb_Rst <= '0';
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WAIT UNTIL CLK = '0';
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assert D_FFb_Q = "00000000" report "D_FF_bank reset error" severity error;
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END PROCESS D_FFb_test;
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U0 : D_FF
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PORT MAP (
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H => CLK,
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D => D_FF_D,
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nRst => D_FF_Rst,
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Q => D_FF_Q
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);
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U1 : D_FF_BANK PORT MAP(
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H => CLK,
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D => D_FFb_D,
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nRst => D_FFb_Rst,
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Q => D_FFb_Q
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);
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END ARCHITECTURE arch; |