33 lines
625 B
VHDL
33 lines
625 B
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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ENTITY shift_register IS
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GENERIC(
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WIDTH: integer
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);
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PORT(
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H: IN std_logic;
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H_EN: IN std_logic;
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nRst : IN std_logic;
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D: IN std_logic;
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Q: OUT std_logic_vector
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);
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END shift_register;
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ARCHITECTURE arch of shift_register IS
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SIGNAL data : std_logic_vector(WIDTH-1 downto 0) := (others => '0');
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BEGIN
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Q <= data;
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sr: PROCESS(H, nRst)
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BEGIN
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if(nRst = '0') THEN
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data <= (others => '0');
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ELSIF(rising_edge(H) and H_EN = '1') THEN
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data <= data(WIDTH-2 downto 0) & D;
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END IF;
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END PROCESS sr;
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END ARCHITECTURE arch; |