pomme

sources_snake/GeneRGB_V1.vhd

@@ -41,7 +41,9 @@ entity GeneRGB_V1 is
            R : out STD_LOGIC_VECTOR (4 downto 0);
            G : out STD_LOGIC_VECTOR (5 downto 0);
            B : out STD_LOGIC_VECTOR (4 downto 0);
-           snakeIn : in color);
+           snakeIn : in color;
+           pommeIn : in color
+           );
 end GeneRGB_V1;
 
 architecture Behavioral of GeneRGB_V1 is
@@ -49,15 +51,18 @@ architecture Behavioral of GeneRGB_V1 is
 begin
 
 process(X,Y,IMG,snakeIn)
+variable snakeCol,pommeCol : color;
 begin
     if (IMG='0') then
         R<=(others=>'0');
         B<=(others=>'0');
         G<=(others=>'0');
     else
-        R<=std_logic_vector(snakeIn.R and resize(shift_right(snakeIn.A,3),5));
-        G<=std_logic_vector(snakeIn.G and resize(shift_right(snakeIn.A,2),6));
-        B<=std_logic_vector(snakeIn.B and resize(shift_right(snakeIn.A,3),5));
+        snakeCol := pValue(snakeIn);
+        pommeCol := pValue(pommeIn);
+        R<=std_logic_vector(to_unsigned(min_int(to_integer(snakeCol.R) + to_integer(pommeCol.R),31),5));
+        G<=std_logic_vector(to_unsigned(min_int(to_integer(snakeCol.G) + to_integer(pommeCol.G),63),6));
+        B<=std_logic_vector(to_unsigned(min_int(to_integer(snakeCol.B) + to_integer(pommeCol.B),31),5));
     end if;
 end process;
 end Behavioral;

sources_snake/VGA_top.vhd

@@ -37,6 +37,7 @@ use ourTypes.types.all;
 entity VGA_top is
     Port ( H125MHz : in STD_LOGIC;
            resetGeneral : in std_logic;
+           resetPomme : in std_logic;
            led : out std_logic_vector (3 downto 0);
            vga_hs : out STD_LOGIC;
            vga_vs : out STD_LOGIC;
@@ -85,7 +86,9 @@ component GeneRGB_V1  is
 		   R     : out std_logic_vector(4 downto 0);
            G     : out std_logic_vector(5 downto 0);
            B     : out std_logic_vector(4 downto 0);
-           snakeIn : in color);
+           snakeIn : in color;
+           pommeIn : in color
+           );
 end component;
 
 component Gene_Snake
@@ -133,10 +136,42 @@ Port (
         button_up : in STD_LOGIC;
         button_down : in STD_LOGIC;
         button_left : in STD_LOGIC;
-        button_right : in STD_LOGIC
+        button_right : in STD_LOGIC;
+        
+        pommeCE : out std_logic;
+        pommeX  : unsigned(5 downto 0);
+        pommeY : unsigned(4 downto 0)
         );
 end component updateSnake;
 
+component pomme
+generic ( dataSize : integer := to_stdlogicvector(dummyPos)'length);
+Port (
+    clk : in std_logic;
+    pxl_clk : in std_logic;
+    reset : in std_logic;
+    
+    CE : in std_logic;
+    
+    X : in unsigned (9 downto 0);
+    Y : in unsigned (8 downto 0);
+    
+    posX : out unsigned(5 downto 0);
+    posY : out unsigned(4 downto 0);
+    
+    colorOut : out color;
+    
+    address : out unsigned(SNAKE_ADDRESS_SIZE-1 downto 0) := (others => '0');
+    data : in std_logic_vector(dataSize-1 downto 0);
+    
+    matAddress : out unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
+    matData : in std_logic_vector(SNAKE_ADDRESS_SIZE-1 downto 0) := (others => '0');
+    
+    ROMAddress : out unsigned(7 downto 0) := (others => '0');
+    ROMData : in std_logic_vector(SPRITES_DATA_SIZE-1 downto 0)
+);
+end component pomme;
+
 component RAMController
 generic( snakeDataSize : integer := to_stdlogicvector(dummyPos)'length);
 Port ( X : in unsigned(5 downto 0);
@@ -215,9 +250,26 @@ signal matupdRAMDataOut : std_logic_vector(SNAKE_ADDRESS_SIZE-1 downto 0);
 signal matupdRAMWE : std_logic;
 signal matupdRAMRE : std_logic;
 
+signal RAMAddress : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
+signal RAMDataIn : std_logic_vector(to_stdlogicvector(dummyPos)'length-1 downto 0);
+signal matRAMAddress : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
+signal matRAMDataIn : std_logic_vector(SNAKE_ADDRESS_SIZE-1 downto 0);
+
 signal spritesROMAddress : unsigned(SPRITES_ADDRESS_SIZE-1 downto 0);
 signal spritesROMData : std_logic_vector(SPRITES_DATA_SIZE-1 downto 0);
 
+signal pommeROMAddress : unsigned(7 downto 0);
+signal pommeROMData : std_logic_vector(SPRITES_DATA_SIZE-1 downto 0);
+
+signal pommeCE : std_logic;
+signal pommeX : unsigned(5 downto 0);
+signal pommeY : unsigned(4 downto 0);
+signal pommeColor : color;
+
+signal pommeAddress : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
+signal pommeData : std_logic_vector(to_stdlogicvector(dummyPos)'length-1 downto 0);
+signal pommeMatAddress : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
+signal pommeMatData : std_logic_vector(SNAKE_ADDRESS_SIZE-1 downto 0);
 --signal clk_latch : std_logic;
 
 begin
@@ -260,7 +312,9 @@ RGB : GeneRGB_V1
     R     => vga_r,
     G     => vga_g,
     B     => vga_b,
-    snakeIn => snakeColor);
+    snakeIn => snakeColor,
+    pommeIn => pommeColor
+    );
     
 UPD_CLK_DIV : Diviseur
     -- pxl_clock 25MHz, clk_lente ~60Hz, 1 coup sur clk_lente = 25e6/60 = 4.2e5 coups sur pxl_clk. ln(4.2e5)/ln(2)=18.6, donc on prend 19bits
@@ -308,14 +362,14 @@ RAMCTRL : RAMController
         dataReady => dataReady,
         
         matWE => matupdRAMWE,
-        matWaddress => matupdRAMAddress,
+        matWaddress => matRAMAddress,
         matWdata => matupdRAMDataOut,
-        matRdata => matupdRAMDataIn,
+        matRdata => matRAMDataIn,
         
         listWE => updateRAMWE,
-        listWAddress => updateRAMAddress,
+        listWAddress => RAMAddress,
         listWData => updateRAMDataOut,
-        listRData => updateRAMDataIn
+        listRData => RAMDataIn
    );
 
 UPD : updateSnake
@@ -337,15 +391,79 @@ UPD : updateSnake
         button_up => button_up,
         button_down => button_down,
         button_left => button_left,
-        button_right => button_right
+        button_right => button_right,
+        
+        pommeCE => pommeCE,
+        pommeX => pommeX,
+        pommeY => pommeY
+    );
+
+APPLE : pomme
+    port map (
+        clk => H125MHz,
+        pxl_clk => pxl_clk,
+        reset => resetPomme,
+        CE => pommeCE,
+        X => Xpxl,
+        Y => Ypxl,
+        posX => pommeX,
+        posY => pommeY,
+        colorOut => pommeColor,
+        address => pommeAddress,
+        data => pommeData,
+        matAddress => pommeMatAddress,
+        matData => pommeMatData,
+        ROMAddress => pommeROMAddress,
+        ROMData => pommeROMData
     );
     
  ROM : spritesROM
+    generic map(
+        addressSize => SPRITES_ADDRESS_SIZE,
+        length => SPRITES_DATA_LENGTH,
+        dataSize => SPRITES_DATA_SIZE,
+        fileName => "../projet-electronique/sprites/sprites.mem" --pour l'implementation
+        --fileName => "../sprites/sprites.mem" --pour la simulation
+    )
     port map(
         address => spritesROMAddress,
         data => spritesROMData,
         clk => H125MHz
     );
+ POMMEROM : spritesROM
+    generic map(
+        addressSize => 8,
+        length => 256,
+        dataSize => SPRITES_DATA_SIZE,
+        fileName => "../projet-electronique/sprites/pomme.mem" --pour l'implementation
+        --fileName => "../sprites/pomme.mem" --pour la simulation
+    )
+    port map(
+        address => pommeROMAddress,
+        data => pommeROMData,
+        clk => H125MHz
+    );
+
+process(pommeCE,updateRAMAddress,pommeMatAddress,RAMDataIn,matUpdRAMAddress,matRAMDataIn)
+begin
+    if(pommeCE = '0') then
+        RAMAddress <= updateRAMAddress;
+        updateRAMDataIn <= RAMDataIn;
+        matRAMAddress <= matUpdRAMAddress;
+        matUpdRAMDataIn <= matRAMDataIn;
+        
+        pommeData <= (others => '0');
+        pommeMatData <= (others => '0');
+    else
+        RAMAddress <= pommeAddress;
+        pommeData <= RAMDataIn;
+        matRAMAddress <= pommeMatAddress;
+        pommeMatData <= matRAMDataIn;
+        
+        updateRAMDataIn <= (others => '0');
+        matUpdRAMDataIn <= (others => '0');
+    end if;
+end process;
 
 led(0) <= resetGeneral;
 led(1) <= updateRAMWE;

sources_snake/ZYBO_Master.xdc

@@ -14,9 +14,9 @@ create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports H125
 set_property PACKAGE_PIN G15 [get_ports resetGeneral]
 set_property IOSTANDARD LVCMOS33 [get_ports resetGeneral]
 
-# #IO_L24P_T3_34
-# set_property PACKAGE_PIN P15 [get_ports {sw[1]}]
-# set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
+ #IO_L24P_T3_34
+ set_property PACKAGE_PIN P15 [get_ports resetPomme]
+ set_property IOSTANDARD LVCMOS33 [get_ports resetPomme]
 
 # #IO_L4N_T0_34
 # set_property PACKAGE_PIN W13 [get_ports {sw[2]}]

sources_snake/pomme.vhd

@@ -0,0 +1,127 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 01/08/2022 10:04:42 PM
+-- Design Name: 
+-- Module Name: pomme - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+library ourTypes;
+use ourTypes.types.all;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity pomme is
+    generic ( dataSize : integer);
+    Port (
+        clk : in std_logic;
+        pxl_clk : in std_logic;
+        reset : in std_logic;
+        
+        CE : in std_logic;
+        
+        X : in unsigned (9 downto 0);
+        Y : in unsigned (8 downto 0);
+        
+        posX : out unsigned(5 downto 0);
+        posY : out unsigned(4 downto 0);
+        
+        colorOut : out color;
+        
+        address : out unsigned(SNAKE_ADDRESS_SIZE-1 downto 0) := (others => '0');
+        data : in std_logic_vector(dataSize-1 downto 0);
+        
+        matAddress : out unsigned(SNAKE_ADDRESS_SIZE-1 downto 0) := (others => '0');
+        matData : in std_logic_vector(SNAKE_ADDRESS_SIZE-1 downto 0) := (others => '0');
+        
+        ROMAddress : out unsigned(7 downto 0) := (others => '0');
+        ROMData : in std_logic_vector(SPRITES_DATA_SIZE-1 downto 0)
+    );
+end pomme;
+
+architecture Behavioral of pomme is
+signal Xpos : unsigned(9 downto 0) := (others => '0');
+signal Ypos : unsigned(8 downto 0) := (others => '0');
+constant FINISHED : unsigned(3 downto 0) := to_unsigned(15,4);
+signal state : unsigned(3 downto 0) := (others => '0');
+signal pommeHere : std_logic;
+begin
+process(clk,reset,CE)
+begin
+    if(reset = '0') then
+        state <= to_unsigned(0,4);
+    elsif(CE = '0') then
+        if(state /= FINISHED) then
+            state <= to_unsigned(0,4);
+        else
+            state <= FINISHED;
+        end if;
+    elsif(rising_edge(clk)) then
+        if(state /= FINISHED) then
+            state <= state + 1;
+        else
+            state <= FINISHED;
+        end if;
+        if(state = 0) then
+            Xpos <= (((Xpos + 733) rem 640) and "1111110000") or "0000001000";
+            Ypos <= (((Ypos + 587) rem 480) and "111110000") or "000001000";
+        elsif(state = 1) then
+            matAddress <= to_unsigned(to_integer(Ypos(Ypos'HIGH downto 4)) * 40 + to_integer(Xpos(Xpos'HIGH downto 4)),SNAKE_ADDRESS_SIZE);
+        elsif(state = 3) then
+            address <= unsigned(matData);
+        elsif(state = 5) then
+            if(to_pos(data).isDefined = '1') then
+                state <= to_unsigned(0,4);
+            else
+                state <= FINISHED;
+            end if;
+        end if;
+    end if;
+end process;
+
+process(pxl_clk)
+variable sX,sY : integer;
+begin
+    if(rising_edge(pxl_clk)) then
+        if(pommeHere = '1') then
+            colorOut <= to_color(ROMData);
+        else
+            colorOut <= (others => (others => '0'));
+        end if;
+        pommeHere <= '0';
+        
+        if(to_integer(X)>=TO_INTEGER(Xpos)-8 and to_integer(X)<TO_INTEGER(Xpos)+8 and to_integer(Y)>=TO_INTEGER(Ypos)-8 and to_integer(Y)<TO_INTEGER(Ypos)+8) then
+            pommeHere <= '1';
+            sX := (to_integer(X) - to_integer(Xpos)) + 8;
+            sY := (to_integer(Y) - to_integer(Ypos)) + 8;
+            ROMAddress <= to_unsigned(sY*16+sX,8);
+        end if;
+    end if;
+end process;
+
+posX <= Xpos(Xpos'HIGH downto 4);
+posY <= Ypos(Ypos'HIGH downto 4);
+end Behavioral;

sources_snake/testBench.vhd

@@ -11,12 +11,19 @@ architecture Behavioral of testbench is
 	component VGA_top is
 		Port ( H125MHz : in STD_LOGIC;
 		       resetGeneral : in std_logic;
+               resetPomme : in std_logic;
 		       led : out std_logic_vector (3 downto 0);
 		       vga_hs : out STD_LOGIC;
 		       vga_vs : out STD_LOGIC;
 		       vga_r : out STD_LOGIC_VECTOR (4 downto 0);
 		       vga_g : out STD_LOGIC_VECTOR (5 downto 0);
-		       vga_b : out STD_LOGIC_VECTOR (4 downto 0));
+		       vga_b : out STD_LOGIC_VECTOR (4 downto 0);
+               
+               button_up : in STD_LOGIC;
+               button_down : in STD_LOGIC;
+               button_left : in STD_LOGIC;
+               button_right : in STD_LOGIC
+    );
 	end component;
 	constant clk_period : time := 8 ns;
 	signal clk : std_logic := '0';
@@ -29,12 +36,19 @@ begin
 	U0 : VGA_top
 	port map(H125MHz => clk,
 		 resetGeneral => '1',
+         resetPomme => '1',
 		 led => open,
 		 vga_hs => HS,
 		 vga_vs => VS,
 		 vga_r => R,
 		 vga_g => G,
-		 vga_b => B);
+		 vga_b => B,
+     
+         button_up => '0',
+         button_down => '0',
+         button_left => '0',
+         button_right => '0'
+     );
 
 	clk <= not clk after clk_period/2;
 

sources_snake/types.vhd

@@ -41,6 +41,9 @@ package types is
     function to_pos(input : std_logic_vector_array) return nSnakes;
     
     function constrain(input : integer; min : integer; max : integer) return integer;
+    function min_int(input : integer;val : integer) return integer;
+    
+    function pValue(c : color) return color;
 end package;
 
 package body types is
@@ -108,4 +111,27 @@ package body types is
         end if;
         return output;
     end constrain;
+    
+    
+    function min_int(input : integer;val : integer) return integer is
+    variable output : integer;
+    begin
+        if(input > val) then
+            output := val;
+        else
+            output := input;
+        end if;
+        return output;
+    end min_int;
+    
+    function pValue(c : color) return color is
+    variable output : color;
+    begin
+        output.R := unsigned(c.R and resize(shift_right(c.A,3),5));
+        output.G := unsigned(c.G and resize(shift_right(c.A,2),6));
+        output.B := unsigned(c.B and resize(shift_right(c.A,3),5));
+        output.A := c.A;
+        return output;
+    end pValue;
+    
 end package body;

sources_snake/updateSnake.vhd

@@ -54,7 +54,11 @@ entity updateSnake is
         button_up : in STD_LOGIC;
         button_down : in STD_LOGIC;
         button_left : in STD_LOGIC;
-        button_right : in STD_LOGIC
+        button_right : in STD_LOGIC;
+        
+        pommeCE : out std_logic := '0';
+        pommeX  : unsigned(5 downto 0);
+        pommeY : unsigned(4 downto 0)
         );
 end updateSnake;
 
@@ -198,6 +202,13 @@ begin
             matDataOut <= std_logic_vector(to_unsigned(to_integer(indext),SNAKE_ADDRESS_SIZE));
             address <= indext;
         end if;
+        
+        
+        if(update = '1' and isUpdating = '0') then
+            pommeCE <= '1';
+        else
+            pommeCE <= '0';
+        end if;
     end if;
     
     if(updateIndex = MAX_SNAKE) then

sprites/pomme.mem

@@ -0,0 +1,256 @@
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