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This commit is contained in:
leo 2023-09-26 11:35:03 +02:00
parent 42d8cb4253
commit 898727d9cf
Signed by: leo
GPG Key ID: 0DD993BFB2B307DB
2 changed files with 169 additions and 156 deletions
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116
ReceptionTrame_lib/receptionTrame.vhd
View File

@ -6,12 +6,43 @@ ENTITY receptionTrame IS
PORT(
H: IN std_logic;
nCLR: IN std_logic;
Lin: IN std_logic
Lin: IN std_logic;
AdrSel: IN std_logic_vector;
RecByte: OUT std_logic_vector(7 downto 0);
RecByte_WR: OUT std_logic;
RecBytes_RST: OUT std_logic;
Err_SET: OUT std_logic_vector(2 downto 0);
NbByteInc: OUT std_logic;
MsgReceived_SET: OUT std_logic;
NbRecByte_RST: OUT std_logic
);
END receptionTrame;
ARCHITECTURE arch OF receptionTrame IS
COMPONENT receptionTrame_op
SIGNAL octetRecu_EN : std_logic;
SIGNAL n_SELECT: std_logic;
SIGNAL n_LOAD: std_logic;
SIGNAL n_EN: std_logic;
SIGNAL nbBit_SELECT: std_logic;
SIGNAL nbBit_LOAD: std_logic;
SIGNAL nbBit_EN: std_logic;
SIGNAL identifier_EN: std_logic;
SIGNAL nbData_LOAD: std_logic;
SIGNAL nbData_EN: std_logic;
SIGNAL LinSynchro: std_logic;
SIGNAL n_0: std_logic;
SIGNAL nbBit_0: std_logic;
SIGNAL nbData_0: std_logic;
COMPONENT receptionTrame_op
GENERIC(
N: integer := 1200;
N_WIDTH : integer := 11
@ -45,7 +76,86 @@ ARCHITECTURE arch OF receptionTrame IS
identifier: OUT std_logic_vector(5 downto 0);
octetRecu: OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
END COMPONENT;
COMPONENT receptionTrame_com
PORT(
H: IN std_logic;
nRST: IN std_logic;
LinSynchro: IN std_logic;
octetRecu_EN: OUT std_logic;
n_SELECT: OUT std_logic;
n_LOAD: OUT std_logic;
n_EN: OUT std_logic;
nbBit_SELECT: OUT std_logic;
nbBit_LOAD: OUT std_logic;
nbBit_EN: OUT std_logic;
identifier_EN: OUT std_logic;
nbData_LOAD: OUT std_logic;
nbData_EN: OUT std_logic;
n_0: IN std_logic;
nbBit_0: IN std_logic;
nbData_0: IN std_logic
);
END COMPONENT receptionTrame_com;
BEGIN
U0 : receptionTrame_op
GENERIC MAP(
N => 1200,
N_WIDTH => 11
)
PORT MAP(
H => H,
nCLR => '1',
Lin => Lin,
octetRecu_EN => octetRecu_EN,
n_SELECT => n_SELECT,
n_LOAD => n_LOAD,
n_EN => n_EN,
nbBit_SELECT => nbBit_SELECT,
nbBit_LOAD => nbBit_LOAD,
nbBit_EN => nbBit_EN,
identifier_EN => identifier_EN,
nbData_LOAD => nbData_LOAD,
nbData_EN => nbData_EN,
LinSynchro => LinSynchro,
n_0 => n_0,
nbBit_0 => nbBit_0,
nbData_0 => nbData_0
);
U1 : receptionTrame_com
PORT MAP(
H => H,
nRST => '1',
LinSynchro => LinSynchro,
octetRecu_EN => octetRecu_EN,
n_SELECT => n_SELECT,
n_LOAD => n_LOAD,
n_EN => n_EN,
nbBit_SELECT => nbBit_SELECT,
nbBit_LOAD => nbBit_LOAD,
nbBit_EN => nbBit_EN,
identifier_EN => identifier_EN,
nbData_LOAD => nbData_LOAD,
nbData_EN => nbData_EN,
n_0 => n_0,
nbBit_0 => nbBit_0,
nbData_0 => nbData_0
);
END ARCHITECTURE arch;

155
ReceptionTrame_lib/receptionTrame_tb.vhd
View File

@ -10,145 +10,30 @@ ENTITY receptionTrame_tb IS
END receptionTrame_tb;
ARCHITECTURE arch of receptionTrame_tb IS
SIGNAL Lin: std_logic;
SIGNAL H: std_logic;
SIGNAL octetRecu_EN : std_logic;
SIGNAL n_SELECT: std_logic;
SIGNAL n_LOAD: std_logic;
SIGNAL n_EN: std_logic;
SIGNAL nbBit_SELECT: std_logic;
SIGNAL nbBit_LOAD: std_logic;
SIGNAL nbBit_EN: std_logic;
SIGNAL identifier_EN: std_logic;
SIGNAL nbData_LOAD: std_logic;
SIGNAL nbData_EN: std_logic;
SIGNAL LinSynchro: std_logic;
SIGNAL n_0: std_logic;
SIGNAL nbBit_0: std_logic;
SIGNAL nbData_0: std_logic;
COMPONENT receptionTrame_op
GENERIC(
N: integer := 1200;
N_WIDTH : integer := 11
);
COMPONENT receptionTrame
PORT(
H: IN std_logic;
nCLR: IN std_logic;
Lin: IN std_logic;
octetRecu_EN : IN std_logic;
AdrSel: IN std_logic_vector;
n_SELECT: IN std_logic;
n_LOAD: IN std_logic;
n_EN: IN std_logic;
RecByte: OUT std_logic_vector(7 downto 0);
RecByte_WR: OUT std_logic;
RecBytes_RST: OUT std_logic;
nbBit_SELECT: IN std_logic;
nbBit_LOAD: IN std_logic;
nbBit_EN: IN std_logic;
identifier_EN: IN std_logic;
nbData_LOAD: IN std_logic;
nbData_EN: IN std_logic;
LinSynchro: OUT std_logic;
n_0: OUT std_logic;
nbBit_0: OUT std_logic;
nbData_0: OUT std_logic;
identifier: OUT std_logic_vector(5 downto 0);
octetRecu: OUT std_logic_vector(7 downto 0)
Err_SET: OUT std_logic_vector(2 downto 0);
NbByteInc: OUT std_logic;
MsgReceived_SET: OUT std_logic;
NbRecByte_RST: OUT std_logic
);
END COMPONENT;
COMPONENT receptionTrame_com
PORT(
H: IN std_logic;
nRST: IN std_logic;
LinSynchro: IN std_logic;
SIGNAL H: std_logic;
SIGNAL Lin: std_logic;
octetRecu_EN: OUT std_logic;
n_SELECT: OUT std_logic;
n_LOAD: OUT std_logic;
n_EN: OUT std_logic;
nbBit_SELECT: OUT std_logic;
nbBit_LOAD: OUT std_logic;
nbBit_EN: OUT std_logic;
identifier_EN: OUT std_logic;
nbData_LOAD: OUT std_logic;
nbData_EN: OUT std_logic;
n_0: IN std_logic;
nbBit_0: IN std_logic;
nbData_0: IN std_logic
);
END COMPONENT receptionTrame_com;
BEGIN
U0 : receptionTrame_op
GENERIC MAP(
N => 1200,
N_WIDTH => 11
)
PORT MAP(
H => H,
nCLR => '1',
Lin => Lin,
octetRecu_EN => octetRecu_EN,
n_SELECT => n_SELECT,
n_LOAD => n_LOAD,
n_EN => n_EN,
nbBit_SELECT => nbBit_SELECT,
nbBit_LOAD => nbBit_LOAD,
nbBit_EN => nbBit_EN,
identifier_EN => identifier_EN,
nbData_LOAD => nbData_LOAD,
nbData_EN => nbData_EN,
LinSynchro => LinSynchro,
n_0 => n_0,
nbBit_0 => nbBit_0,
nbData_0 => nbData_0
);
U1 : receptionTrame_com
PORT MAP(
H => H,
nRST => '1',
LinSynchro => LinSynchro,
octetRecu_EN => octetRecu_EN,
n_SELECT => n_SELECT,
n_LOAD => n_LOAD,
n_EN => n_EN,
nbBit_SELECT => nbBit_SELECT,
nbBit_LOAD => nbBit_LOAD,
nbBit_EN => nbBit_EN,
identifier_EN => identifier_EN,
nbData_LOAD => nbData_LOAD,
nbData_EN => nbData_EN,
n_0 => n_0,
nbBit_0 => nbBit_0,
nbData_0 => nbData_0
);
clkGen : PROCESS
BEGIN
H <= '1';
@ -204,4 +89,22 @@ BEGIN
END PROCESS;
U0 : receptionTrame
PORT MAP(
H => H,
nCLR => '1',
Lin => Lin,
AdrSel => "000000",
RecByte => OPEN,
RecByte_WR => OPEN,
RecBytes_RST => OPEN,
Err_SET => OPEN,
NbByteInc => OPEN,
MsgReceived_SET => OPEN,
NbRecByte_RST => OPEN
);
END ARCHITECTURE arch;