leo/linreceiver-vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

sync field start

Browse Source
This commit is contained in:
leo 2023-09-26 10:21:18 +02:00
parent 9383e1c441
commit 9b37bc7894
Signed by: leo
GPG Key ID: 0DD993BFB2B307DB
2 changed files with 32 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

34
ReceptionTrame_lib/receptionTrame_com.vhd
View File

@ -60,8 +60,8 @@ CASE cState IS
END IF;
WHEN syncBreak1 =>
if(LinSynchro = '0') THEN
if(n_0 = '1') THEN
if(n_0 = '1') THEN
if(LinSynchro = '1') THEN
nState <= syncFieldWait;
else
nState <= waiting;
@ -116,7 +116,7 @@ BEGIN
n_LOAD <= '1';
n_SELECT <= '0';
else
-- ERROR sync
-- ERROR sync break
end if;
else
if(n_0 = '1') then
@ -130,6 +130,34 @@ BEGIN
n_EN <= '1';
nbBit_LOAD <= '0';
end if;
WHEN syncBreak1 =>
if(n_0 = '1') then
if(LinSynchro = '0') then
-- ERROR sync stop
end if;
else
n_LOAD <= '0';
n_EN <= '1';
end if;
WHEN syncFieldWait =>
if(LinSynchro = '0') then
n_LOAD <= '1';
n_SELECT <= '1';
end if;
WHEN syncFieldStart =>
if(n_0 = '1') then
if(LinSynchro = '0') then
n_SELECT <= '0';
n_LOAD <= '1';
nbBit_SELECT <= '1';
nbBit_LOAD <= '1';
else
-- ERROR start bit
end if;
else
n_LOAD <= '0';
n_EN <= '1';
end if;
WHEN others =>
end CASE;

2
ReceptionTrame_lib/receptionTrame_tb.vhd
View File

@ -5,7 +5,7 @@ USE ieee.std_logic_arith.all;
ENTITY receptionTrame_tb IS
GENERIC(
CLOCK_PERIOD: time := 52 us;
UC_CLK_PERIOD: time := 10 ns
UC_CLK_PERIOD: time := 40 ns
);
END receptionTrame_tb;