310 lines
9.5 KiB
VHDL
310 lines
9.5 KiB
VHDL
-- VHDL Entity RecepteurLIN_lib.FrameReceptionOP.symbol
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--
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-- Created:
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-- by - e208835u.UNKNOWN (irb121-06)
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-- at - 17:02:12 19/09/2023
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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ENTITY FrameReceptionOP IS
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GENERIC(
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N : std_logic_vector := "10000000000"
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);
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PORT(
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BitsNb_EN : IN std_logic;
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BitsNb_LOAD : IN std_logic;
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BitsNb_SELECT : IN std_logic;
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DataFieldNb_EN : IN std_logic;
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DataFieldNb_LOAD : IN std_logic;
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H : IN std_logic;
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IdentifierField_EN : IN std_logic;
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Lin : IN std_logic;
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RecByte_EN : IN std_logic;
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nCLR : IN std_logic;
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n_EN : IN std_logic;
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n_LOAD : IN std_logic;
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n_SELECT : IN std_logic;
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BitsNb_0 : OUT std_logic;
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DataFieldNb : OUT std_logic_vector (2 DOWNTO 0);
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DataFieldNb_0 : OUT std_logic;
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IdentifierField : OUT std_logic_vector (5 DOWNTO 0);
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LinSynchro : OUT std_logic;
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RecByte : OUT std_logic_vector (7 DOWNTO 0);
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n_0 : OUT std_logic
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);
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-- Declarations
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END FrameReceptionOP ;
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--
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-- VHDL Architecture RecepteurLIN_lib.FrameReceptionOP.struct
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--
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-- Created:
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-- by - e208835u.UNKNOWN (irb121-02)
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-- at - 12:28:45 03/10/2023
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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-- LIBRARY RecepteurLIN_lib;
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ARCHITECTURE struct OF FrameReceptionOP IS
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-- Architecture declarations
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-- Internal signal declarations
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SIGNAL BitsNb : std_logic_vector(3 DOWNTO 0);
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SIGNAL BitsNb_INIT : std_logic_vector(3 DOWNTO 0);
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SIGNAL DataFieldNb_INIT : std_logic_vector(2 DOWNTO 0);
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SIGNAL dout : std_logic;
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SIGNAL dout1 : std_logic_vector(3 DOWNTO 0);
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SIGNAL dout2 : std_logic_vector(3 DOWNTO 0);
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SIGNAL dout3 : std_logic_vector(10 DOWNTO 0);
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SIGNAL dout4 : std_logic_vector(10 DOWNTO 0);
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SIGNAL n_INIT : std_logic_vector(10 DOWNTO 0);
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SIGNAL pas_n : std_logic_vector(10 DOWNTO 0);
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-- Implicit buffer signal declarations
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SIGNAL LinSynchro_internal : std_logic;
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SIGNAL RecByte_internal : std_logic_vector (7 DOWNTO 0);
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-- ModuleWare signal declarations(v1.12) for instance 'U_3' of 'cntr'
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SIGNAL mw_U_3n_cnt : std_logic_vector(10 DOWNTO 0);
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SIGNAL mw_U_3c_cnt : std_logic_vector(10 DOWNTO 0);
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-- ModuleWare signal declarations(v1.12) for instance 'U_7' of 'cntr'
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SIGNAL mw_U_7n_cnt : std_logic_vector(3 DOWNTO 0);
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SIGNAL mw_U_7c_cnt : std_logic_vector(3 DOWNTO 0);
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-- ModuleWare signal declarations(v1.12) for instance 'U_13' of 'cntr'
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SIGNAL mw_U_13n_cnt : std_logic_vector(2 DOWNTO 0);
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SIGNAL mw_U_13c_cnt : std_logic_vector(2 DOWNTO 0);
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-- ModuleWare signal declarations(v1.12) for instance 'U_0' of 'dff'
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SIGNAL mw_U_0reg_cval : std_logic;
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-- ModuleWare signal declarations(v1.12) for instance 'U_11' of 'dff'
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SIGNAL mw_U_11reg_cval : std_logic_vector(5 DOWNTO 0);
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-- ModuleWare signal declarations(v1.12) for instance 'U_1' of 'shiftsp'
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SIGNAL mw_U_1reg_cval : std_logic_vector(7 DOWNTO 0);
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SIGNAL mw_U_1reg_nval : std_logic_vector(7 DOWNTO 0);
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-- Component Declarations
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COMPONENT decoder
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PORT (
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RecByte : IN std_logic_vector (5 DOWNTO 4);
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DataFieldNb_INIT : OUT std_logic_vector (2 DOWNTO 0)
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);
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END COMPONENT;
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-- Optional embedded configurations
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-- pragma synthesis_off
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-- FOR ALL : decoder USE ENTITY RecepteurLIN_lib.decoder;
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-- pragma synthesis_on
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BEGIN
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-- ModuleWare code(v1.12) for instance 'U_3' of 'cntr'
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pas_n <= mw_U_3c_cnt;
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u_3clock_proc: PROCESS (H, nCLR)
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BEGIN
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IF (nCLR = '0') THEN
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mw_U_3c_cnt <= "00000000000";
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ELSIF (H'EVENT AND H='1') THEN
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IF (n_EN = '1') THEN
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mw_U_3c_cnt <= mw_U_3n_cnt;
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END IF;
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END IF;
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END PROCESS u_3clock_proc;
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u_3combo_proc: PROCESS (n_LOAD, n_INIT, mw_U_3c_cnt)
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BEGIN
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IF (n_LOAD = '1') THEN
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mw_U_3n_cnt <= n_INIT;
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ELSE
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IF (mw_U_3c_cnt = "00000000000") THEN
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mw_U_3n_cnt <= "11111111111";
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ELSE
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mw_U_3n_cnt <= (unsigned(mw_U_3c_cnt) - '1');
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END IF;
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END IF;
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END PROCESS u_3combo_proc;
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u_3max_drive_proc: PROCESS (mw_U_3c_cnt)
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BEGIN
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n_0 <= '0';
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IF (mw_U_3c_cnt = "00000000000") THEN
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n_0 <= '1';
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END IF;
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END PROCESS u_3max_drive_proc;
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-- ModuleWare code(v1.12) for instance 'U_7' of 'cntr'
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BitsNb <= mw_U_7c_cnt;
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u_7clock_proc: PROCESS (H, nCLR)
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BEGIN
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IF (nCLR = '0') THEN
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mw_U_7c_cnt <= "0000";
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ELSIF (H'EVENT AND H='1') THEN
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IF (BitsNb_EN = '1') THEN
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mw_U_7c_cnt <= mw_U_7n_cnt;
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END IF;
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END IF;
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END PROCESS u_7clock_proc;
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u_7combo_proc: PROCESS (BitsNb_LOAD, BitsNb_INIT, mw_U_7c_cnt)
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BEGIN
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IF (BitsNb_LOAD = '1') THEN
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mw_U_7n_cnt <= BitsNb_INIT;
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ELSE
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IF (mw_U_7c_cnt = "0000") THEN
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mw_U_7n_cnt <= "1111";
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ELSE
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mw_U_7n_cnt <= (unsigned(mw_U_7c_cnt) - '1');
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END IF;
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END IF;
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END PROCESS u_7combo_proc;
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u_7max_drive_proc: PROCESS (mw_U_7c_cnt)
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BEGIN
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BitsNb_0 <= '0';
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IF (mw_U_7c_cnt = "0000") THEN
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BitsNb_0 <= '1';
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END IF;
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END PROCESS u_7max_drive_proc;
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-- ModuleWare code(v1.12) for instance 'U_13' of 'cntr'
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DataFieldNb <= mw_U_13c_cnt;
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u_13clock_proc: PROCESS (H, nCLR)
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BEGIN
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IF (nCLR = '0') THEN
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mw_U_13c_cnt <= "000";
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ELSIF (H'EVENT AND H='1') THEN
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IF (DataFieldNb_EN = '1') THEN
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mw_U_13c_cnt <= mw_U_13n_cnt;
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END IF;
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END IF;
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END PROCESS u_13clock_proc;
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u_13combo_proc: PROCESS (DataFieldNb_LOAD, DataFieldNb_INIT, mw_U_13c_cnt)
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BEGIN
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IF (DataFieldNb_LOAD = '1') THEN
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mw_U_13n_cnt <= DataFieldNb_INIT;
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ELSE
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IF (mw_U_13c_cnt = "000") THEN
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mw_U_13n_cnt <= "111";
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ELSE
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mw_U_13n_cnt <= (unsigned(mw_U_13c_cnt) - '1');
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END IF;
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END IF;
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END PROCESS u_13combo_proc;
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u_13max_drive_proc: PROCESS (mw_U_13c_cnt)
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BEGIN
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DataFieldNb_0 <= '0';
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IF (mw_U_13c_cnt = "000") THEN
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DataFieldNb_0 <= '1';
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END IF;
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END PROCESS u_13max_drive_proc;
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-- ModuleWare code(v1.12) for instance 'U_5' of 'constval'
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dout4 <= "10000010001";
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-- ModuleWare code(v1.12) for instance 'U_6' of 'constval'
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dout3 <= "01000001001";
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-- ModuleWare code(v1.12) for instance 'U_9' of 'constval'
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dout2 <= "1100";
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-- ModuleWare code(v1.12) for instance 'U_10' of 'constval'
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dout1 <= "1000";
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-- ModuleWare code(v1.12) for instance 'U_0' of 'dff'
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LinSynchro_internal <= mw_U_0reg_cval;
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u_0seq_proc: PROCESS (H, nCLR)
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BEGIN
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IF (nCLR = '0') THEN
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mw_U_0reg_cval <= '0';
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ELSIF (H'EVENT AND H='1') THEN
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mw_U_0reg_cval <= Lin;
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END IF;
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END PROCESS u_0seq_proc;
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-- ModuleWare code(v1.12) for instance 'U_11' of 'dff'
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IdentifierField <= mw_U_11reg_cval;
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u_11seq_proc: PROCESS (H, nCLR)
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BEGIN
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IF (nCLR = '0') THEN
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mw_U_11reg_cval <= "000000";
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ELSIF (H'EVENT AND H='1') THEN
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IF (IdentifierField_EN = '1') THEN
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mw_U_11reg_cval <= RecByte_internal(5 DOWNTO 0);
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END IF;
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END IF;
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END PROCESS u_11seq_proc;
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-- ModuleWare code(v1.12) for instance 'U_2' of 'gnd'
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dout <= '0';
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-- ModuleWare code(v1.12) for instance 'U_4' of 'mux'
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u_4combo_proc: PROCESS(dout4, dout3, n_SELECT)
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BEGIN
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CASE n_SELECT IS
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WHEN '0' => n_INIT <= dout4;
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WHEN '1' => n_INIT <= dout3;
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WHEN OTHERS => n_INIT <= (OTHERS => 'X');
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END CASE;
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END PROCESS u_4combo_proc;
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-- ModuleWare code(v1.12) for instance 'U_8' of 'mux'
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u_8combo_proc: PROCESS(dout2, dout1, BitsNb_SELECT)
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BEGIN
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CASE BitsNb_SELECT IS
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WHEN '0' => BitsNb_INIT <= dout2;
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WHEN '1' => BitsNb_INIT <= dout1;
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WHEN OTHERS => BitsNb_INIT <= (OTHERS => 'X');
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END CASE;
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END PROCESS u_8combo_proc;
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-- ModuleWare code(v1.12) for instance 'U_1' of 'shiftsp'
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RecByte_internal <= mw_U_1reg_cval;
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u_1seq_proc: PROCESS (H, nCLR)
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BEGIN
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IF (nCLR = '0') THEN
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mw_U_1reg_cval <= "00000000";
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ELSIF (H'EVENT AND H='1') THEN
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IF (RecByte_EN = '1') THEN
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mw_U_1reg_cval <= mw_U_1reg_nval;
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END IF;
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END IF;
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END PROCESS u_1seq_proc;
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u_1combo_proc: PROCESS (dout, LinSynchro_internal, mw_U_1reg_cval)
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VARIABLE temp_dout : std_logic_vector(9 DOWNTO 0);
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BEGIN
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IF (dout = '0') THEN
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temp_dout := LinSynchro_internal & LinSynchro_internal & mw_U_1reg_cval;
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ELSIF (dout = '1') THEN
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temp_dout := mw_U_1reg_cval & LinSynchro_internal & LinSynchro_internal;
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ELSE
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temp_dout := (OTHERS => 'X');
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END IF;
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mw_U_1reg_nval <= temp_dout(8 DOWNTO 1);
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END PROCESS u_1combo_proc;
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-- Instance port mappings.
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U_12 : decoder
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PORT MAP (
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RecByte => RecByte_internal(5 DOWNTO 4),
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DataFieldNb_INIT => DataFieldNb_INIT
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);
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-- Implicit buffered output assignments
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LinSynchro <= LinSynchro_internal;
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RecByte <= RecByte_internal;
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END struct;
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