pomme effect
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97c06ebc8a
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@ -36,7 +36,8 @@ entity Diviseur is
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Port ( clk_in : in STD_LOGIC;
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Port ( clk_in : in STD_LOGIC;
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reset : in STD_LOGIC;
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reset : in STD_LOGIC;
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max : in unsigned (nbBits-1 downto 0);
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max : in unsigned (nbBits-1 downto 0);
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clk_out : out STD_LOGIC);
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clk_out : out STD_LOGIC
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);
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end Diviseur;
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end Diviseur;
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architecture Behavioral of Diviseur is
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architecture Behavioral of Diviseur is
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@ -50,7 +50,7 @@ architecture Behavioral of GeneRGB_V1 is
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begin
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begin
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process(X,Y,IMG,snakeIn)
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process(X,Y,IMG,snakeIn,pommeIn)
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variable snakeCol,pommeCol : color;
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variable snakeCol,pommeCol : color;
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begin
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begin
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if (IMG='0') then
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if (IMG='0') then
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@ -37,7 +37,6 @@ use ourTypes.types.all;
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entity VGA_top is
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entity VGA_top is
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Port ( H125MHz : in STD_LOGIC;
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Port ( H125MHz : in STD_LOGIC;
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resetGeneral : in std_logic;
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resetGeneral : in std_logic;
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resetPomme : in std_logic;
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led : out std_logic_vector (3 downto 0);
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led : out std_logic_vector (3 downto 0);
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vga_hs : out STD_LOGIC;
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vga_hs : out STD_LOGIC;
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vga_vs : out STD_LOGIC;
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vga_vs : out STD_LOGIC;
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@ -139,8 +138,13 @@ Port (
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button_right : in STD_LOGIC;
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button_right : in STD_LOGIC;
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pommeCE : out std_logic;
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pommeCE : out std_logic;
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pommeX : unsigned(5 downto 0);
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pommeX : in unsigned(5 downto 0);
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pommeY : unsigned(4 downto 0)
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pommeY : in unsigned(4 downto 0);
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resetPomme : out std_logic;
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tailIndex : out unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
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lost : out std_logic
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);
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);
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end component updateSnake;
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end component updateSnake;
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@ -265,11 +269,16 @@ signal pommeCE : std_logic;
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signal pommeX : unsigned(5 downto 0);
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signal pommeX : unsigned(5 downto 0);
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signal pommeY : unsigned(4 downto 0);
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signal pommeY : unsigned(4 downto 0);
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signal pommeColor : color;
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signal pommeColor : color;
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signal pommeReset : std_logic;
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signal pommeAddress : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
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signal pommeAddress : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
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signal pommeData : std_logic_vector(to_stdlogicvector(dummyPos)'length-1 downto 0);
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signal pommeData : std_logic_vector(to_stdlogicvector(dummyPos)'length-1 downto 0);
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signal pommeMatAddress : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
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signal pommeMatAddress : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
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signal pommeMatData : std_logic_vector(SNAKE_ADDRESS_SIZE-1 downto 0);
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signal pommeMatData : std_logic_vector(SNAKE_ADDRESS_SIZE-1 downto 0);
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signal tailIndex : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
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signal lost : std_logic;
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--signal clk_latch : std_logic;
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--signal clk_latch : std_logic;
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begin
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begin
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@ -325,6 +334,7 @@ UPD_CLK_DIV : Diviseur
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max => to_unsigned(420000,25),
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max => to_unsigned(420000,25),
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--max => to_unsigned(25000000,25),
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--max => to_unsigned(25000000,25),
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--max => to_unsigned(1000,25),
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--max => to_unsigned(1000,25),
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--max => (others => '0'),
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clk_out => clk_lente
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clk_out => clk_lente
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);
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);
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@ -338,7 +348,7 @@ SNAKE : Gene_Snake
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listRefs => listRefs,
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listRefs => listRefs,
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updateOrder => pxl_clk,
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updateOrder => pxl_clk,
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dataReady => dataReady,
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dataReady => dataReady,
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tailIndex => to_unsigned(12,SNAKE_ADDRESS_SIZE),
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tailIndex => tailIndex,
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cCaseX => cCaseX,
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cCaseX => cCaseX,
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cCaseY => cCaseY,
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cCaseY => cCaseY,
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dataRequest => dataRequest,
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dataRequest => dataRequest,
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@ -395,14 +405,19 @@ UPD : updateSnake
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pommeCE => pommeCE,
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pommeCE => pommeCE,
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pommeX => pommeX,
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pommeX => pommeX,
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pommeY => pommeY
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pommeY => pommeY,
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resetPomme => pommeReset,
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tailIndex => tailIndex,
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lost => lost
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);
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);
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APPLE : pomme
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APPLE : pomme
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port map (
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port map (
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clk => H125MHz,
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clk => H125MHz,
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pxl_clk => pxl_clk,
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pxl_clk => pxl_clk,
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reset => resetPomme,
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reset => pommeReset,
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CE => pommeCE,
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CE => pommeCE,
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X => Xpxl,
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X => Xpxl,
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Y => Ypxl,
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Y => Ypxl,
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@ -444,7 +459,7 @@ APPLE : pomme
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clk => H125MHz
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clk => H125MHz
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);
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);
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process(pommeCE,updateRAMAddress,pommeMatAddress,RAMDataIn,matUpdRAMAddress,matRAMDataIn)
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process(pommeCE,updateRAMAddress,pommeAddress,pommeMatAddress,RAMDataIn,matUpdRAMAddress,matRAMDataIn)
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begin
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begin
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if(pommeCE = '0') then
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if(pommeCE = '0') then
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RAMAddress <= updateRAMAddress;
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RAMAddress <= updateRAMAddress;
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@ -468,4 +483,5 @@ end process;
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led(0) <= resetGeneral;
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led(0) <= resetGeneral;
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led(1) <= updateRAMWE;
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led(1) <= updateRAMWE;
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led(2) <= clk_lente;
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led(2) <= clk_lente;
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led(3) <= lost;
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end Behavioral;
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end Behavioral;
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@ -14,9 +14,9 @@ create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports H125
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set_property PACKAGE_PIN G15 [get_ports resetGeneral]
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set_property PACKAGE_PIN G15 [get_ports resetGeneral]
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set_property IOSTANDARD LVCMOS33 [get_ports resetGeneral]
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set_property IOSTANDARD LVCMOS33 [get_ports resetGeneral]
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#IO_L24P_T3_34
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# #IO_L24P_T3_34
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set_property PACKAGE_PIN P15 [get_ports resetPomme]
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# set_property PACKAGE_PIN P15 [get_ports resetPomme]
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set_property IOSTANDARD LVCMOS33 [get_ports resetPomme]
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# set_property IOSTANDARD LVCMOS33 [get_ports resetPomme]
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# #IO_L4N_T0_34
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# #IO_L4N_T0_34
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# set_property PACKAGE_PIN W13 [get_ports {sw[2]}]
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# set_property PACKAGE_PIN W13 [get_ports {sw[2]}]
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@ -69,7 +69,8 @@ constant FINISHED : unsigned(3 downto 0) := to_unsigned(15,4);
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signal state : unsigned(3 downto 0) := (others => '0');
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signal state : unsigned(3 downto 0) := (others => '0');
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signal pommeHere : std_logic;
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signal pommeHere : std_logic;
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begin
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begin
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process(clk,reset,CE)
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process(clk,reset,CE,state)
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variable randInd : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0) := (others => '0');
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begin
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begin
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if(reset = '0') then
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if(reset = '0') then
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state <= to_unsigned(0,4);
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state <= to_unsigned(0,4);
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@ -86,8 +87,9 @@ begin
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state <= FINISHED;
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state <= FINISHED;
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end if;
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end if;
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if(state = 0) then
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if(state = 0) then
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Xpos <= (((Xpos + 733) rem 640) and "1111110000") or "0000001000";
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randInd := (randInd + 937) rem MAX_SNAKE;
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Ypos <= (((Ypos + 587) rem 480) and "111110000") or "000001000";
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Xpos <= (randInd(5 downto 0) rem 40) & "1000";
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Ypos <= resize(randInd rem 30,5) & "1000";
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elsif(state = 1) then
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elsif(state = 1) then
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matAddress <= to_unsigned(to_integer(Ypos(Ypos'HIGH downto 4)) * 40 + to_integer(Xpos(Xpos'HIGH downto 4)),SNAKE_ADDRESS_SIZE);
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matAddress <= to_unsigned(to_integer(Ypos(Ypos'HIGH downto 4)) * 40 + to_integer(Xpos(Xpos'HIGH downto 4)),SNAKE_ADDRESS_SIZE);
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elsif(state = 3) then
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elsif(state = 3) then
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@ -57,8 +57,13 @@ entity updateSnake is
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button_right : in STD_LOGIC;
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button_right : in STD_LOGIC;
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pommeCE : out std_logic := '0';
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pommeCE : out std_logic := '0';
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pommeX : unsigned(5 downto 0);
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pommeX : in unsigned(5 downto 0);
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pommeY : unsigned(4 downto 0)
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pommeY : in unsigned(4 downto 0);
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resetPomme : out std_logic := '1';
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tailIndex : out unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
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lost : out std_logic := '0'
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);
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);
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end updateSnake;
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end updateSnake;
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@ -66,17 +71,19 @@ architecture Behavioral of updateSnake is
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signal index : unsigned(SNAKE_ADDRESS_SIZE downto 0) := to_unsigned(0,SNAKE_ADDRESS_SIZE+1);
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signal index : unsigned(SNAKE_ADDRESS_SIZE downto 0) := to_unsigned(0,SNAKE_ADDRESS_SIZE+1);
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signal isUpdating: std_logic := '0';
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signal isUpdating: std_logic := '0';
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signal updateIndex : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0) := (others => '0');
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signal updateIndex : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0) := (others => '0');
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signal state : unsigned(3 downto 0) := (others => '0');
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signal state : unsigned(4 downto 0) := (others => '0');
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signal nbOfEls : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0) := to_unsigned(12,SNAKE_ADDRESS_SIZE);
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begin
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begin
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process(updateIndex, clk_rapide, clk_lente,reset,index) --process de reset
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process(updateIndex, clk_rapide, clk_lente,reset,index) --process de reset
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variable cSnake : pos; --current snake, celui qu'on met à jour
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variable cSnake : pos; --current snake, celui qu'on met à jour
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variable lSnake : pos; --last snake, sauvegarde de l'état précédent
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variable lSnake : pos; --last snake, sauvegarde de l'état précédent
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variable pSnake : pos; --previous snake, snake precedent dans la chaine
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variable pSnake : pos; --previous snake, snake precedent dans la chaine (on s'en sert aussi de stockage temp pour ajouter un el)
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variable currentSnake : pos;
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variable currentSnake : pos;
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variable update : std_logic := '0';
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variable update : std_logic := '0';
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variable indext : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0) := to_unsigned(0,SNAKE_ADDRESS_SIZE);
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variable indext : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0) := to_unsigned(0,SNAKE_ADDRESS_SIZE);
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variable updateIndext : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0) := (others => '0');
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variable updateIndext : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0) := (others => '0');
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constant PROG_END : unsigned(3 downto 0) := to_unsigned(15,4);
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variable addEl : std_logic := '0';
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constant PROG_END : unsigned(4 downto 0) := to_unsigned(31,5);
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begin
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begin
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if rising_edge(clk_lente) then
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if rising_edge(clk_lente) then
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@ -130,7 +137,7 @@ begin
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writeEnable <= '1';
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writeEnable <= '1';
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else
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else
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address <= updateIndext-1;
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address <= updateIndext-1;
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state <= to_unsigned(9,4);
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state <= to_unsigned(9,5);
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end if;
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end if;
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else
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else
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dataOut <= to_stdlogicvector(cSnake);
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dataOut <= to_stdlogicvector(cSnake);
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@ -146,6 +153,11 @@ begin
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matWriteEnable <= '1';
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matWriteEnable <= '1';
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matAddress <= to_unsigned(to_integer(cSnake.Y(cSnake.Y'high downto 4)) * 40 + to_integer(cSnake.X(cSnake.X'high downto 4)),SNAKE_ADDRESS_SIZE);
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matAddress <= to_unsigned(to_integer(cSnake.Y(cSnake.Y'high downto 4)) * 40 + to_integer(cSnake.X(cSnake.X'high downto 4)),SNAKE_ADDRESS_SIZE);
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matDataOut <= std_logic_vector(updateIndext);
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matDataOut <= std_logic_vector(updateIndext);
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if(cSnake.X(cSnake.X'high downto 4) = pommeX and cSnake.Y(cSnake.Y'high downto 4) = pommeY) then
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resetPomme <= '0';
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addEl := '1';
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end if;
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else
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else
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state <= PROG_END; --jump end
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state <= PROG_END; --jump end
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end if;
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end if;
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@ -158,7 +170,12 @@ begin
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matWriteEnable <= '1';
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matWriteEnable <= '1';
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matDataOut <= std_logic_vector(to_unsigned(MAX_SNAKE-1,SNAKE_ADDRESS_SIZE));
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matDataOut <= std_logic_vector(to_unsigned(MAX_SNAKE-1,SNAKE_ADDRESS_SIZE));
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end if;
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end if;
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state <= PROG_END; --jump end
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if(addEl = '1') then
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state <= to_unsigned(12,5);
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resetPomme <= '1';
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else
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state <= PROG_END; --jump end
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end if;
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elsif(state = 10) then -- PROPAGATION DE LA DIRECTION
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elsif(state = 10) then -- PROPAGATION DE LA DIRECTION
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pSnake := to_pos(dataIn);
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pSnake := to_pos(dataIn);
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@ -167,18 +184,37 @@ begin
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dataOut <= to_stdlogicvector(cSnake);
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dataOut <= to_stdlogicvector(cSnake);
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writeEnable <= '1';
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writeEnable <= '1';
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address <= updateIndext;
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address <= updateIndext;
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state <= to_unsigned(3,4); --on peut ptet directement jump à la fin?
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state <= to_unsigned(3,5); --on peut ptet directement jump à la fin?
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elsif(state = 12) then
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address <= nbOfEls;
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matWriteEnable <= '0';
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nbOfEls <= nbOfEls + 1;
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elsif(state = 14) then
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pSnake := to_pos(dataIn);
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pSnake.X := to_unsigned(to_integer(pSnake.X) - 16 * to_integer(pSnake.dirX),10);
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pSnake.Y := to_unsigned(to_integer(pSnake.Y) - 16 * to_integer(pSnake.dirY),9);
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dataOut <= to_stdlogicvector(pSnake);
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address <= nbOfEls;
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matDataOut <= std_logic_vector(nbOfEls);
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matAddress <= to_unsigned(to_integer(pSnake.Y(pSnake.Y'high downto 4)) * 40 + to_integer(pSnake.X(pSnake.X'high downto 4)),SNAKE_ADDRESS_SIZE);
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elsif(state = 15) then
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writeEnable <= '1';
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matWriteEnable <= '1';
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addEl := '0';
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state <= PROG_END;
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elsif(state = PROG_END) then --END
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elsif(state = PROG_END) then --END
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matWriteEnable <= '0';
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matWriteEnable <= '0';
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writeEnable <= '0';
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writeEnable <= '0';
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updateIndex <= updateIndex + 1;
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updateIndex <= updateIndex + 1;
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state <= to_unsigned(0,4);
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state <= to_unsigned(0,5);
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end if;
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end if;
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end if;
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end if;
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if update = '0' then
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if update = '0' then
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if(indext = 0) then
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if(indext = 0) then
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nbOfEls <= to_unsigned(12,SNAKE_ADDRESS_SIZE);
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currentSnake.X := to_unsigned(8+to_integer(indext)*16,10);
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currentSnake.X := to_unsigned(8+to_integer(indext)*16,10);
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currentSnake.Y := to_unsigned(8,9);
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currentSnake.Y := to_unsigned(8,9);
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currentSnake.dirX := to_signed(0,2);
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currentSnake.dirX := to_signed(0,2);
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@ -214,7 +250,9 @@ begin
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if(updateIndex = MAX_SNAKE) then
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if(updateIndex = MAX_SNAKE) then
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isUpdating <= '0';
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isUpdating <= '0';
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updateIndex <= to_unsigned(0,SNAKE_ADDRESS_SIZE);
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updateIndex <= to_unsigned(0,SNAKE_ADDRESS_SIZE);
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state <= to_unsigned(0,4);
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state <= to_unsigned(0,5);
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end if;
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end if;
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end process;
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end process;
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tailIndex <= nbOfEls;
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end Behavioral;
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end Behavioral;
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