leo/linreceiver-vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

sync field data

Browse Source
This commit is contained in:
leo 2023-09-26 10:33:29 +02:00
parent 9b37bc7894
commit 7e5d636cd0
Signed by: leo
GPG Key ID: 0DD993BFB2B307DB
2 changed files with 25 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
ReceptionTrame_lib/receptionTrame_com.vhd
View File

@ -7,6 +7,8 @@ ENTITY receptionTrame_com IS
H: IN std_logic;
nRST: IN std_logic;
LinSynchro: IN std_logic;
octetRecu_EN: OUT std_logic;
n_SELECT: OUT std_logic;
n_LOAD: OUT std_logic;
@ -158,6 +160,24 @@ BEGIN
n_LOAD <= '0';
n_EN <= '1';
end if;
WHEN syncFieldData =>
if(nbBit_0 = '1') then
n_SELECT <= '0';
n_LOAD <= '1';
octetRecu_EN <= '0';
else
if(n_0 = '1') then
n_LOAD <= '1';
n_SELECT <= '0';
nbBit_EN <= '1';
octetRecu_EN <= '1';
else
n_LOAD <= '0';
nbBit_EN <= '0';
octetRecu_EN <= '0';
end if;
nbBit_LOAD <= '0';
end if;
WHEN others =>
end CASE;

6
ReceptionTrame_lib/receptionTrame_tb.vhd
View File

@ -5,7 +5,7 @@ USE ieee.std_logic_arith.all;
ENTITY receptionTrame_tb IS
GENERIC(
CLOCK_PERIOD: time := 52 us;
UC_CLK_PERIOD: time := 40 ns
UC_CLK_PERIOD: time := 43 ns
);
END receptionTrame_tb;
@ -74,6 +74,8 @@ COMPONENT receptionTrame_com
H: IN std_logic;
nRST: IN std_logic;
LinSynchro: IN std_logic;
octetRecu_EN: OUT std_logic;
n_SELECT: OUT std_logic;
n_LOAD: OUT std_logic;
@ -126,6 +128,8 @@ U1 : receptionTrame_com
H => H,
nRST => '1',
LinSynchro => LinSynchro,
octetRecu_EN => octetRecu_EN,
n_SELECT => n_SELECT,
n_LOAD => n_LOAD,