stdlib

InterfaceMicroprocesseur_lib/InterfaceMicroprocesseur.core

@@ -21,7 +21,6 @@ targets:
       - rtl
     toplevel: InterfaceMicroprocesseur
     parameters:
-      - clk_freq_hz
 
   sim:
     <<: *default

ReceptionTrame_lib/ReceptionTrame.core

@@ -0,0 +1,47 @@
+CAPI=2:
+name: ETN4:recepteurLIN:ReceptionTrame:1.0.0
+description: Fonction reception trame LIN
+
+filesets:
+  rtl:
+    files:
+      - receptionTrame_op.vhd
+    file_type: vhdlSource
+
+  tb:
+    files:
+    file_type: vhdlSource
+
+
+targets:
+  default: &default
+    filesets:
+      - rtl
+    toplevel: receptionTrame
+    parameters:
+
+  sim:
+    <<: *default
+    description: Simulate the design
+    default_tool: ghdl
+    filesets_append:
+      - tb
+    toplevel: receptionTrame_tb
+    tools:
+      ghdl:
+        analyze_options:
+          - -fsynopsys
+        run_options:
+          - --wave=waveform.ghw --stop-time=2us
+    parameters:
+
+  synth:
+    <<: *default
+    description: Synthesize the design
+    default_tool: vivado
+    filesets_append:
+    tools:
+      vivado:
+        part: xc7a35tcpg236-1
+        pnr: none
+    parameters:

ReceptionTrame_lib/receptionTrame_op.vhd

@@ -0,0 +1,55 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ENTITY receptionTrame IS
+  GENERIC(
+    N: integer := 1200;
+  );
+  PORT(
+    H: IN std_logic; 
+    nCLR: IN std_logic;
+    Lin: IN std_logic;
+    
+    n_SELECT: IN std_logic;
+    n_LOAD: IN std_logic;
+    n_EN: IN std_logic;
+
+    nbBit_SELECT: IN std_logic;
+    nbBit_LOAD: IN std_logic;
+    nbBit_EN: IN std_logic;
+
+    identifier_EN: IN std_logic;
+
+    nbData_LOAD: IN std_logic;
+    nbData_EN: IN std_logic;
+
+    LinSynchro: OUT std_logic;
+    
+    n_0: OUT std_logic;
+    nbBit_0: OUT std_logic;
+    nbData_0: OUT std_logic;
+
+    identifier: OUT std_logic_vector(5 downto 0);
+    octetRecu: OUT std_logic_vector(7 downto 0);
+  );
+
+END receptionTrame;
+
+ARCHITECTURE arch OF receptionTrame IS
+
+BEGIN
+
+-- Lin sync D-FF, with asynchronous reset
+LinSync : PROCESS(nCLR, H)
+BEGIN
+  IF(nCLR = '0') THEN
+    LinSynchro <= '0';
+  ELSIF(rising_edge(H)) THEN
+    LinSynchro <= Lin;
+  END IF;
+END PROCESS LinSync;
+
+
+
+END ARCHITECTURE arch;

STDLIB_lib/D_FF.vhd

@@ -0,0 +1,25 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ENTITY D_FF IS
+  PORT(
+    H: IN std_logic;
+    D: IN std_logic;
+    nRst: IN std_logic;
+    Q: OUT std_logic
+  );
+END D_FF;
+ARCHITECTURE arch of D_FF IS
+BEGIN
+
+dff: PROCESS(H, nRst)
+BEGIN
+  if(nRst = '0') THEN
+    Q <= '0';
+  ELSIF(rising_edge(H)) THEN
+    Q <= D;
+  END IF;
+END PROCESS dff;
+
+END ARCHITECTURE arch;

STDLIB_lib/D_FF_bank.vhd

@@ -0,0 +1,35 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ENTITY D_FF_BANK IS
+  PORT(
+    H: IN std_logic;
+    nRst : IN std_logic;
+    D: IN std_logic_vector;
+    Q: OUT std_logic_vector
+  );
+END D_FF_BANK;
+
+ARCHITECTURE arch OF D_FF_BANK IS
+COMPONENT D_FF
+  PORT(
+    H: IN std_logic;
+    D: IN std_logic;
+    nRst: IN std_logic;
+    Q: OUT std_logic
+  );
+END COMPONENT;
+
+BEGIN
+
+bank_generate : for i in D'RANGE generate
+  DFF_X : D_FF port map(
+    H => H,
+    D => D(i),
+    nRst => nRst,
+    Q => Q(i)
+  );
+end generate;
+
+END ARCHITECTURE arch;

STDLIB_lib/STDLIB_lib.core

@@ -0,0 +1,38 @@
+CAPI=2:
+name: ETN4:STDLIB:STDLIB:1.0.0
+description: Basic functions (FF, registers, counters, ...)
+
+filesets:
+  rtl:
+    files:
+      - D_FF.vhd
+      - D_FF_bank.vhd
+    file_type: vhdlSource
+
+  tb:
+    files:
+      - stdlib_tb.vhd
+    file_type: vhdlSource
+
+targets:
+  default: &default
+    filesets:
+      - rtl
+    toplevel:
+    parameters:
+
+  sim:
+    <<: *default
+    description: Simulate the design
+    default_tool: ghdl
+    filesets_append:
+      - tb
+    toplevel: stdlib_tb
+    tools:
+      ghdl:
+        analyze_options:
+          - -fsynopsys
+          - --std=08
+        run_options:
+          - --wave=waveform.ghw --stop-time=2us
+    parameters:

STDLIB_lib/stdlib_tb.vhd

@@ -0,0 +1,104 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ENTITY stdlib_tb IS
+  GENERIC(
+    CLOCK_PERIOD : time := 10 ns
+  );
+END stdlib_tb;
+
+ARCHITECTURE arch of stdlib_tb IS
+SIGNAL CLK : std_logic;
+
+SIGNAL D_FF_D : std_logic;
+SIGNAL D_FF_Rst : std_logic;
+SIGNAL D_FF_Q : std_logic;
+
+SIGNAL D_FFb_D : std_logic_vector(7 downto 0);
+SIGNAL D_FFb_Rst : std_logic;
+SIGNAL D_FFb_Q : std_logic_vector(7 downto 0);
+
+COMPONENT D_FF
+  PORT(
+    H: IN std_logic;
+    D: IN std_logic;
+    nRst: IN std_logic;
+    Q: OUT std_logic
+  );
+END COMPONENT;
+
+COMPONENT D_FF_BANK
+  PORT(
+    H: IN std_logic;
+    D: IN std_logic_vector;
+    nRst: IN std_logic;
+    Q: OUT std_logic_vector
+  );
+END COMPONENT;
+
+BEGIN
+
+CLK_gen : PROCESS
+BEGIN
+  CLK <= '0';
+  WAIT FOR CLOCK_PERIOD/2;
+  CLK <= '1';
+  WAIT FOR CLOCK_PERIOD/2;
+END PROCESS CLK_gen;
+
+D_FF_test : PROCESS
+BEGIN
+  D_FF_Rst <= '0';
+  
+  WAIT UNTIL CLK = '1';
+  D_FF_Rst <= '1';
+  D_FF_D <= '1';
+  
+  WAIT UNTIL CLK = '0';
+  assert D_FF_Q = '0' report "D_FF set before clk" severity error;
+
+  WAIT UNTIL CLK = '0';
+  assert D_FF_Q = '1' report "D_FF not set" severity error;
+  D_FF_Rst <= '0';
+  
+  WAIT UNTIL CLK = '0';
+  assert D_FF_Q = '0' report "D_FF reset error" severity error;
+END PROCESS D_FF_test;
+
+D_FFb_test : PROCESS
+BEGIN
+  D_FFb_Rst <= '0';
+  
+  WAIT UNTIL CLK = '1';
+  D_FFb_Rst <= '1';
+  D_FFb_D <= "01010101";
+  
+  WAIT UNTIL CLK = '0';
+  assert D_FFb_Q = "00000000" report "D_FF_bank set before clk" severity error;
+
+  WAIT UNTIL CLK = '0';
+  assert D_FFb_Q = "01010101" report "D_FF_bank not set" severity error;
+  D_FFb_Rst <= '0';
+  
+  WAIT UNTIL CLK = '0';
+  assert D_FFb_Q = "00000000" report "D_FF_bank reset error" severity error;
+END PROCESS D_FFb_test;
+
+
+U0 : D_FF
+  PORT MAP (
+    H => CLK,
+    D => D_FF_D,
+    nRst => D_FF_Rst,
+    Q => D_FF_Q
+  );
+
+U1 : D_FF_BANK PORT MAP(
+  H => CLK,
+  D => D_FFb_D,
+  nRst => D_FFb_Rst,
+  Q => D_FFb_Q
+);
+
+END ARCHITECTURE arch;

fusesoc.conf

@@ -10,3 +10,9 @@ sync-uri = InterfaceMicroprocesseur_lib
 sync-type = local
 auto-sync = true
 
+[library.STDLIB]
+location = /home/leo/Sketchbook/VHDL/LIN_receiver/RecepteurLIN_lib/STDLIB_lib
+sync-uri = STDLIB_lib
+sync-type = local
+auto-sync = true
+