NbDataField counter

ReceptionTrame_lib/receptionTrame_op.vhd

@@ -1,6 +1,7 @@
 LIBRARY ieee;
 USE ieee.std_logic_1164.all;
-USE ieee.std_logic_arith.all;
+-- USE ieee.std_logic_arith.all;
+USE ieee.numeric_std.all;
 
 ENTITY receptionTrame_op IS
   GENERIC(
@@ -41,7 +42,8 @@ END receptionTrame_op;
 ARCHITECTURE arch OF receptionTrame_op IS
 SIGNAL LinSynchro_int : std_logic;
 SIGNAL octetRecu_int : std_logic_vector(7 downto 0);
-SIGNAL nbDataField_INIT : integer;
+SIGNAL nbDataField_INIT_int : integer := 0;
+SIGNAL nbDataField_INIT : unsigned(2 downto 0);
 
 COMPONENT D_FF
   PORT(
@@ -64,6 +66,24 @@ COMPONENT shift_register
     Q: OUT std_logic_vector
   );
 END COMPONENT;
+
+COMPONENT counter
+  GENERIC(
+    WIDTH: integer;
+    MAX_VAL: integer
+  );
+  PORT(
+    H: IN std_logic;
+    H_EN: IN std_logic;
+    nRst: IN std_logic;
+    INIT: IN unsigned(WIDTH-1 downto 0);
+    LOAD: IN std_logic;
+    upnDown: IN std_logic;
+
+    val: OUT unsigned(WIDTH-1 downto 0);
+    max: OUT std_logic
+  );
+END COMPONENT;
 BEGIN
 
 LinSynchro <= LinSynchro_int;
@@ -93,13 +113,30 @@ Lin_para : shift_register
 
 -- Decoder
 WITH octetRecu_int(5 downto 4) SELECT
-  nbDataField_INIT <= 
+  nbDataField_INIT_int <= 
     1 when "00",
     1 when "01",
     3 when "10",
     7 when "11",
     0 when others;
 
+nbDataField_INIT <= to_unsigned(nbDataField_INIT_int, 3);
+
 -- nbDataField counter
+nbDataField_cmp : counter
+  GENERIC MAP(
+    WIDTH => 3,
+    MAX_VAL => 0
+  )
+  PORT MAP(
+    H => H,
+    H_EN => nbData_EN,
+    nRst => nCLR,
+    INIT => nbDataField_INIT,
+    LOAD => nbData_LOAD,
+    upnDown => '0',
+    val => OPEN,
+    max => nbData_0
+  );
 
 END ARCHITECTURE arch;

ReceptionTrame_lib/receptionTrame_tb.vhd

@@ -68,10 +68,10 @@ U0 : receptionTrame_op
     n_LOAD => '0',
     n_EN => '0',
     nbBit_SELECT => '0',
-    nbBit_LOAD => '0',
-    nbBit_EN => '0',
+    nbBit_LOAD => '1',
+    nbBit_EN => '1',
     identifier_EN => '0',
-    nbData_LOAD => '0',
-    nbData_EN => '0'
+    nbData_LOAD => '1',
+    nbData_EN => '1'
   );
 END ARCHITECTURE arch;

STDLIB_lib/counter.vhd

@@ -31,7 +31,7 @@ main : PROCESS(H, nRst)
 BEGIN
   if(nRst = '0') then
     cmp <= to_unsigned(0, WIDTH);
-  elsif(rising_edge(H)) then
+  elsif(rising_edge(H) and H_EN = '1') then
     if(LOAD = '1') then
       cmp <= INIT;
     elsif(cmp /= MAX_VAL) then

STDLIB_lib/shift_register.vhd

@@ -25,7 +25,7 @@ sr: PROCESS(H, nRst)
 BEGIN
   if(nRst = '0') THEN
     data <= (others => '0');
-  ELSIF(rising_edge(H)) THEN
+  ELSIF(rising_edge(H) and H_EN = '1') THEN
     data <= data(WIDTH-2 downto 0) & D;
   END IF;
 END PROCESS sr;